From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 4E9DD3858C78 for ; Fri, 24 Mar 2023 14:12:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4E9DD3858C78 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679667135; x=1711203135; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=DrR04XmNEVlhkFYxJEWEHkaKOI05k09NRKzeF95tG78=; b=QSrntHKJBBAlPlvLOEvZIbaTpxIYeiAlJlbkK1CBAFfiLI0hH4kM9zNl HZ9dgugznQrRZL8RPZfYyUjc3TVaoETpU5u2pzKBPtKiiGCbowvjEMF2P SAk6qMBdo06pW5LBCApxrmJhi5gEwqIKQbKsPkAfyLDzCKVTNyOv65qoE zKW5aI3s0rUNU0j0Sln1RahuEv+f0ek3gXbLnJPsiFcGpy+GZ0FWbNNwd f5eOoNsvSQI4knk/Jepi4IXxpncKb+NZnHc/eWvPs/Ubq0M5TRfvLMSsX JsPFNDZc+u0rXAn/u5BXr3z6imCpCFFQSUE/J5hAnr1MI9/7ElwXfwjvU A==; X-IronPort-AV: E=McAfee;i="6600,9927,10659"; a="319434932" X-IronPort-AV: E=Sophos;i="5.98,288,1673942400"; d="scan'208";a="319434932" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2023 07:12:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10659"; a="715238757" X-IronPort-AV: E=Sophos;i="5.98,288,1673942400"; d="scan'208";a="715238757" Received: from pli-ubuntu.sh.intel.com ([10.239.46.88]) by orsmga001.jf.intel.com with ESMTP; 24 Mar 2023 07:12:00 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, hongtao.liu@intel.com Subject: [PATCH] RTL: Bugfix for wrong code with v16hi compare & mask Date: Fri, 24 Mar 2023 22:11:57 +0800 Message-Id: <20230324141157.1646192-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_PASS,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li Fix the bug of the incorrect code generation for the below code sample. typedef unsigned short __attribute__((__vector_size__ (32))) V; typedef unsigned short u16; void foo (V m, u16 *ret) { V v = 6 > ((V) { 2049, 8 } & m); *ret = v[0]; // + a + b + c + d; } Before this patch. addi sp,sp,-64 ld a5,0(a0) li a4,528384 addi a4,a4,-2047 and a5,a5,a4 // slli a5,a5,48 <- eliminated by mistake // srli a5,a5,48 <- eliminated by mistake sltiu a5,a5,6 negw a5,a5 sh a5,0(a1) After this patch. addi sp,sp,-64 ld a5,0(a0) li a4,528384 addi a4,a4,-2047 and a5,a5,a4 slli a5,a5,48 srli a5,a5,48 sltiu a5,a5,6 negw a5,a5 sh a5,0(a1) The simplify_comparation for the AND operation will try to simplify below RTL code from: (and:DI (subreg:DI (reg:HI 154) 0) (const_int 0x801)) to: (subreg:DI (and (reg:HI 154) (const_int 0x801)) 0) If reg:HI 154 is 0x801 and reg:DI 154 is 0x80801, the RTL will be simplified continuely to: (subreg:DI (reg:HI 154) 0) That will loss the chance to clean the upper bits of the reg:DI 154, which result in the slli/srli to be eliminated. This patch will try 2 times when simplify_gen_binary for both the reg:HI 154 and the reg:DI 154, and only perform the operation if the returned simplified RTX equals. PR 109040 gcc/ChangeLog: * combine.cc (simplify_comparison): gcc/testsuite/ChangeLog: * gcc.dg/pr109040.c: New test. Signed-off-by: Pan Li Co-authored-by: Hongtao Liu --- gcc/combine.cc | 14 +++++++++++--- gcc/testsuite/gcc.target/riscv/pr109040.c | 14 ++++++++++++++ 2 files changed, 25 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr109040.c diff --git a/gcc/combine.cc b/gcc/combine.cc index 053879500b7..7a62c95ddc8 100644 --- a/gcc/combine.cc +++ b/gcc/combine.cc @@ -12681,10 +12681,18 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1) && c1 != mask && c1 != GET_MODE_MASK (tmode)) { - op0 = simplify_gen_binary (AND, tmode, - SUBREG_REG (XEXP (op0, 0)), + rtx op0_exp0 = XEXP (op0, 0); + machine_mode op0_exp0_mode = GET_MODE (op0_exp0); + rtx op0_subreg = simplify_gen_binary (AND, tmode, + SUBREG_REG (op0_exp0), gen_int_mode (c1, tmode)); - op0 = gen_lowpart (mode, op0); + rtx op0_reg = simplify_gen_binary (AND, GET_MODE (op0_exp0), + op0_exp0, + gen_int_mode (c1, op0_exp0_mode)); + if (!rtx_equal_p (op0_subreg, op0_reg)) + break; + + op0 = gen_lowpart (mode, op0_reg); continue; } } diff --git a/gcc/testsuite/gcc.target/riscv/pr109040.c b/gcc/testsuite/gcc.target/riscv/pr109040.c new file mode 100644 index 00000000000..079b2156364 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr109040.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O2 -fno-schedule-insns -fno-schedule-insns2" } */ + +typedef unsigned short __attribute__((__vector_size__ (32))) V; +typedef unsigned short u16; + +void +foo (V m, u16 *ret) +{ + V v = 6 > ((V) { 2049, 8 } & m); + *ret = v[0]; +} + +/* { dg-final { scan-assembler-times {slli\s+a[0-9]+,\s*a[0-9]+,\s*48\s+srli\s+a[0-9]+,\s*a[0-9]+,\s*48} 1 } } */ -- 2.34.1