From: Christoph Muellner <christoph.muellner@vrull.eu>
To: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
JuzheZhong <juzhe.zhong@rivai.ai>,
Jojo R <rjiejie@linux.alibaba.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH] target/109296 - riscv: Add missing mode specifiers for XTheadMemPair
Date: Mon, 27 Mar 2023 13:04:22 +0200 [thread overview]
Message-ID: <20230327110422.3353876-1-christoph.muellner@vrull.eu> (raw)
From: Christoph Müllner <christoph.muellner@vrull.eu>
This patch adds missing mode specifiers for XTheadMemPair INSNs.
gcc/ChangeLog:
PR target/109296
* config/riscv/thead.md: Add missing mode specifiers.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gcc/config/riscv/thead.md | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 63c4af6f77d..0623607d3dc 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -321,10 +321,10 @@ (define_insn "*th_mempair_store_<GPR:mode>2"
;; MEMPAIR load DI extended signed SI
(define_insn "*th_mempair_load_extendsidi2"
- [(set (match_operand 0 "register_operand" "=r")
- (sign_extend:DI (match_operand 1 "memory_operand" "m")))
- (set (match_operand 2 "register_operand" "=r")
- (sign_extend:DI (match_operand 3 "memory_operand" "m")))]
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extend:DI (match_operand:SI 1 "memory_operand" "m")))
+ (set (match_operand:DI 2 "register_operand" "=r")
+ (sign_extend:DI (match_operand:SI 3 "memory_operand" "m")))]
"TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
&& th_mempair_operands_p (operands, true, SImode)"
{ return th_mempair_output_move (operands, true, SImode, SIGN_EXTEND); }
@@ -334,10 +334,10 @@ (define_insn "*th_mempair_load_extendsidi2"
;; MEMPAIR load DI extended unsigned SI
(define_insn "*th_mempair_load_zero_extendsidi2"
- [(set (match_operand 0 "register_operand" "=r")
- (zero_extend:DI (match_operand 1 "memory_operand" "m")))
- (set (match_operand 2 "register_operand" "=r")
- (zero_extend:DI (match_operand 3 "memory_operand" "m")))]
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (match_operand:SI 1 "memory_operand" "m")))
+ (set (match_operand:DI 2 "register_operand" "=r")
+ (zero_extend:DI (match_operand:SI 3 "memory_operand" "m")))]
"TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
&& th_mempair_operands_p (operands, true, SImode)"
{ return th_mempair_output_move (operands, true, SImode, ZERO_EXTEND); }
--
2.39.2
next reply other threads:[~2023-03-27 11:04 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-27 11:04 Christoph Muellner [this message]
2023-03-27 11:55 ` Kito Cheng
2023-03-27 12:19 ` Philipp Tomsich
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