From: Segher Boessenkool <segher@kernel.crashing.org>
To: Xionghu Luo <xionghuluo@tencent.com>
Cc: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com,
wschmidt@linux.ibm.com, guojiufu@linux.ibm.com,
linkw@gcc.gnu.org
Subject: Re: [PATCH v4] rs6000: Fix incorrect RTL for Power LE when removing the UNSPECS [PR106069]
Date: Thu, 30 Mar 2023 14:30:51 -0500 [thread overview]
Message-ID: <20230330193051.GS25951@gate.crashing.org> (raw)
In-Reply-To: <20230210025952.1887696-1-xionghuluo@tencent.com>
Hi!
On Fri, Feb 10, 2023 at 10:59:52AM +0800, Xionghu Luo via Gcc-patches wrote:
> The native RTL expression for vec_mrghw should be same for BE and LE as
> they are register and endian-independent.
This isn't so obvious at all. All elements of these constructs are
very much not endian-independent, because of very unfortunate choices
in the meaning of some RTL constructs. It is possible all things in
this negate all other things, but please show that then.
> So both BE and LE need
> generate exactly same RTL with index [0 4 1 5] when expanding vec_mrghw
> with vec_select and vec_concat.
>
> (set (reg:V4SI 141) (vec_select:V4SI (vec_concat:V8SI
> (subreg:V4SI (reg:V16QI 139) 0)
> (subreg:V4SI (reg:V16QI 140) 0))
> [const_int 0 4 1 5]))
With BE, if the source vecs are ABCD and EFGH, the vec_concat gives
ABCDEFGH, and the vec_select than gives AEBF.
What happens for LE?
Segher
next prev parent reply other threads:[~2023-03-30 19:31 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-10 2:59 Xionghu Luo
2023-02-28 6:43 ` Ping: " Xionghu Luo
2023-03-30 19:30 ` Segher Boessenkool [this message]
2023-03-31 2:47 ` Xionghu Luo
-- strict thread matches above, loose matches on Subject: below --
2022-08-08 3:42 [PATCH] " Xionghu Luo
2022-08-09 3:01 ` Kewen.Lin
2022-08-10 6:39 ` [PATCH v2] " Xionghu Luo
2022-08-10 17:07 ` Segher Boessenkool
2022-08-11 6:15 ` Xionghu Luo
2022-08-16 6:53 ` Kewen.Lin
2022-08-17 6:23 ` [PATCH v4] " Xionghu Luo
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