From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id DC64A3858D20 for ; Fri, 31 Mar 2023 06:58:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DC64A3858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680245913; x=1711781913; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=6HnNsWXb7Np12WJ6FElio9rK6aRpaliGIIA7Dv4nzGc=; b=HtTLR1y4CTtYNHUFyiI9APuVL0SKmWuuo2is7C1qYraan2IWGjiJ4i26 EeNbh7lwOwoH9ZhfWyvEPw5Px2mZYovDxJ08lIlTxA+oBbjPjra31UF2D 6lRZLtxUjZ2nJFuDecrXSUq3X60StBvjbqyxf8rUBeQr5reTlS7WNeJEO 3wR2T29GBgbEe5oGFEACFbh7fkmG47lpddKM6moDdZ/T9f8TuflVmmQgZ OVdYo91l/DgLM9Oh9giNyDeXGbEXr1hkSNGqxnaVVLTcJ9ADswqz7xD3h 3liICXncgj+m3L6EQV9ZmnfvuJbuV5tbIl17z8oKupAOZNJ8Y6e57Encc A==; X-IronPort-AV: E=McAfee;i="6600,9927,10665"; a="321031781" X-IronPort-AV: E=Sophos;i="5.98,307,1673942400"; d="scan'208";a="321031781" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2023 23:58:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10665"; a="796003182" X-IronPort-AV: E=Sophos;i="5.98,307,1673942400"; d="scan'208";a="796003182" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga002.fm.intel.com with ESMTP; 30 Mar 2023 23:58:10 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 1C7D2100519C; Fri, 31 Mar 2023 14:58:10 +0800 (CST) From: liuhongt To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com Subject: [PATCH] Document signbitm2. Date: Fri, 31 Mar 2023 14:58:10 +0800 Message-Id: <20230331065810.4012545-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.39.1.388.g2fc9e9ca3c MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_PASS,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Look through all backends which defined signbitm2. 1. When m is a scalar mode, the dest is SImode. 2. When m is a vector mode, the dest mode is the vector integer mode has the same size and elements number as m. Ok for trunk? gcc/ChangeLog: * doc/md.texi: Document signbitm2. --- gcc/doc/md.texi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 8e3113599fd..edfa51e867a 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -6030,6 +6030,17 @@ floating-point mode. This pattern is not allowed to @code{FAIL}. +@cindex @code{signbit@var{m}2} instruction pattern +@item @samp{signbit@var{m}2} +Store the sign bit of floating-point operand 1 in operand 0. +@var{m} is either a scalar or vector mode. When it is a scalar, +operand 1 has mode @var{m} but operand 0 must have mode @code{SImode}. +When @var{m} is a vector, operand 1 has the mode @var{m}. +operand 0's mode should be an vector integer mode which has +the same number of elements and the same size as mode @var{m}. + +This pattern is not allowed to @code{FAIL}. + @cindex @code{significand@var{m}2} instruction pattern @item @samp{significand@var{m}2} Store the significand of floating-point operand 1 in operand 0. -- 2.39.1.388.g2fc9e9ca3c