From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by sourceware.org (Postfix) with ESMTP id 8273C3858D1E for ; Tue, 4 Apr 2023 07:49:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8273C3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id EwgMCgBX9cRx1itkvIcCAA--.19490S4; Tue, 04 Apr 2023 15:49:05 +0800 (CST) From: Li Xu To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Li Xu Subject: [PATCH] RISC-V: Fix typo Date: Tue, 4 Apr 2023 15:49:03 +0800 Message-Id: <20230404074903.4275-1-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID:EwgMCgBX9cRx1itkvIcCAA--.19490S4 X-Coremail-Antispam: 1UD129KBjvJXoWxAF1Utw13Gr4xtFW8Kr4xCrg_yoW5ArWrpa yYgr4aya4fAFs7uw13K3y8Gay3tasa9w45Gws5Ar15Aay5G398ZF1DG343Ar1UXFn8Xr1a ka4Uuw4aka18J3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfU5WlkUUUUU X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: gcc/ChangeLog: * config/riscv/riscv-vector-builtins.def: Fix typo. * config/riscv/riscv.cc (riscv_dwarf_poly_indeterminate_value): Ditto. * config/riscv/vector-iterators.md: Ditto. --- gcc/config/riscv/riscv-vector-builtins.def | 3 +-- gcc/config/riscv/riscv.cc | 4 ++-- gcc/config/riscv/vector-iterators.md | 4 ++-- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def index 2d527f76f0a..563ad355342 100644 --- a/gcc/config/riscv/riscv-vector-builtins.def +++ b/gcc/config/riscv/riscv-vector-builtins.def @@ -65,8 +65,7 @@ along with GCC; see the file COPYING3. If not see #define DEF_RVV_BASE_TYPE(NAME, TYPE) #endif -/* Use "DEF_RVV_TYPE_INDEX" macro to define RVV function types. - The 'NAME' will be concatenated into intrinsic function name. */ +/* Use "DEF_RVV_TYPE_INDEX" macro to define RVV function types. */ #ifndef DEF_RVV_TYPE_INDEX #define DEF_RVV_TYPE_INDEX(VECTOR, MASK, SIGNED, UNSIGNED, EEW8_INDEX, EEW16_INDEX, \ EEW32_INDEX, EEW64_INDEX, SHIFT, DOUBLE_TRUNC, \ diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 76eee4a55e9..5f542932d13 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7048,8 +7048,8 @@ riscv_dwarf_poly_indeterminate_value (unsigned int i, unsigned int *factor, int *offset) { /* Polynomial invariant 1 == (VLENB / riscv_bytes_per_vector_chunk) - 1. - 1. TARGET_MIN_VLEN == 32, olynomial invariant 1 == (VLENB / 4) - 1. - 2. TARGET_MIN_VLEN > 32, olynomial invariant 1 == (VLENB / 8) - 1. + 1. TARGET_MIN_VLEN == 32, polynomial invariant 1 == (VLENB / 4) - 1. + 2. TARGET_MIN_VLEN > 32, polynomial invariant 1 == (VLENB / 8) - 1. */ gcc_assert (i == 1); *factor = riscv_bytes_per_vector_chunk; diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 34e486e48ca..194e9b8f57f 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -727,7 +727,7 @@ (VNx1QI "vnx4hi") (VNx2QI "vnx4hi") (VNx4QI "vnx4hi") (VNx8QI "vnx4hi") (VNx16QI "vnx4hi") (VNx32QI "vnx4hi") (VNx64QI "vnx4hi") (VNx1HI "vnx2si") (VNx2HI "vnx2si") (VNx4HI "vnx2si") - (VNx8HI "vnx2si") (VNx16HI "vnx2si") (VNx32HI "vnx2SI") + (VNx8HI "vnx2si") (VNx16HI "vnx2si") (VNx32HI "vnx2si") (VNx1SI "vnx2di") (VNx2SI "vnx2di") (VNx4SI "vnx2di") (VNx8SI "vnx2di") (VNx16SI "vnx2di") (VNx1SF "vnx1df") (VNx2SF "vnx1df") @@ -738,7 +738,7 @@ (VNx1QI "vnx2hi") (VNx2QI "vnx2hi") (VNx4QI "vnx2hi") (VNx8QI "vnx2hi") (VNx16QI "vnx2hi") (VNx32QI "vnx2hi") (VNx1HI "vnx1si") (VNx2HI "vnx1si") (VNx4HI "vnx1si") - (VNx8HI "vnx1si") (VNx16HI "vnx1SI") + (VNx8HI "vnx1si") (VNx16HI "vnx1si") ]) (define_mode_attr VDEMOTE [ -- 2.17.1