From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x643.google.com (mail-pl1-x643.google.com [IPv6:2607:f8b0:4864:20::643]) by sourceware.org (Postfix) with ESMTPS id 87281385772E for ; Wed, 5 Apr 2023 21:03:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 87281385772E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x643.google.com with SMTP id le6so35578781plb.12 for ; Wed, 05 Apr 2023 14:03:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1680728581; x=1683320581; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IQmv8crckXDjdIGct/3h/uQFufuCYNr1NhmHrxCwpMg=; b=nBZMmOtNOf/WZOdMjjKl2ihWzCWuCsRB/Icwnzk4EoWvF1h1nYXqZaMsRoY3XkKAwE 9MZbamhQY5bIuB7jaaLU3LRtINJOIq6zU7IpvVKFoiHTU77yJCVn1Q4SMRf0mp0jwLsX 5tTcB9skSo53td+xFxAqsSqgqTqslZGw2aJ1CxUsUEn9FptJCmrFVaVHNHUqB53Wbwz+ dylC3YvMS4ZjVb69veBFkJUKXTu2FA5BPQA2mBPuCEAv9BoPOls83TskGqriMDR38v0/ u46XjyGYtmE5hhhtDUP0ki3ydby0at/IVFY2OepKg0eOLbgd00Hn9W0ruVGFiKW8PhI3 9r3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680728581; x=1683320581; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IQmv8crckXDjdIGct/3h/uQFufuCYNr1NhmHrxCwpMg=; b=0zkO1rYx8tGDydWKkML3U691J1E5zxJAI/XQrzTKwNcwmeDhlTZZxJsTu1SYP6IBUy U89e9ok/cSwSS8/AFGsLo1m4NQWXL75Z3uwE+mfODWfDJpmycZGHEJCg1W8WDUgk623m xvWapo4xGMBIaLi75HMKR5s0GbMmWGvY1vJ9DXbB+ZkQI+OFQGNIYKLFuw03MQNGhC4D IsTDhdbAeIgzu2WtgWvPEpVJeuloMSQguQdMNqy5aTzuCtdMjYE7aTcPZGLqYpYDhex6 w44KvuZvK9gTm50wYPB0+j4Dhlbn19vF06ytiA9m5roNiAso1870vEidPkInceKOg7Qn KKLQ== X-Gm-Message-State: AAQBX9fwu3xulDv3RSIw2BWc6KLVTMFJxmFj52Jp5a9J59ikMbx+a2a9 o+1T+u6fvTHQiYCWHcvhautqOREf77zCq6Y/VEZ2+Hosa7Y= X-Google-Smtp-Source: AKy350bjLO7aG0ySOLdJDU5PDvJbk9OX5CBSj39pUelCFF6Ef4D84H13GT3ac6UDtDiaAm3bTaq54g== X-Received: by 2002:a17:90b:3ec6:b0:234:e0c:caaa with SMTP id rm6-20020a17090b3ec600b002340e0ccaaamr8442223pjb.6.1680728581379; Wed, 05 Apr 2023 14:03:01 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id e6-20020a17090a77c600b002342ccc8280sm1809477pjs.6.2023.04.05.14.03.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 14:03:01 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jeffreyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 2/8] RISCV: Enforce Libatomic LR/SC SEQ_CST Date: Wed, 5 Apr 2023 14:01:12 -0700 Message-Id: <20230405210118.1969283-3-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405210118.1969283-1-patrick@rivosinc.com> References: <20220407182918.294892-1-patrick@rivosinc.com> <20230405210118.1969283-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-05 Patrick O'Neill * atomic.c: Change LR.aq/SC.rl pairs into sequentially consistent LR.aqrl/SC.rl pair. Signed-off-by: Patrick O'Neill --- libgcc/config/riscv/atomic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libgcc/config/riscv/atomic.c b/libgcc/config/riscv/atomic.c index 69f53623509..5f895939b0b 100644 --- a/libgcc/config/riscv/atomic.c +++ b/libgcc/config/riscv/atomic.c @@ -39,7 +39,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see unsigned old, tmp1, tmp2; \ \ asm volatile ("1:\n\t" \ - "lr.w.aq %[old], %[mem]\n\t" \ + "lr.w.aqrl %[old], %[mem]\n\t" \ #insn " %[tmp1], %[old], %[value]\n\t" \ invert \ "and %[tmp1], %[tmp1], %[mask]\n\t" \ @@ -73,7 +73,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see unsigned old, tmp1; \ \ asm volatile ("1:\n\t" \ - "lr.w.aq %[old], %[mem]\n\t" \ + "lr.w.aqrl %[old], %[mem]\n\t" \ "and %[tmp1], %[old], %[mask]\n\t" \ "bne %[tmp1], %[o], 1f\n\t" \ "and %[tmp1], %[old], %[not_mask]\n\t" \ -- 2.25.1