From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1041.google.com (mail-pj1-x1041.google.com [IPv6:2607:f8b0:4864:20::1041]) by sourceware.org (Postfix) with ESMTPS id 6A35F385773C for ; Wed, 5 Apr 2023 21:03:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6A35F385773C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pj1-x1041.google.com with SMTP id f6-20020a17090ac28600b0023b9bf9eb63so38570434pjt.5 for ; Wed, 05 Apr 2023 14:03:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1680728585; x=1683320585; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F2bBVJ77D9HA2dPUKZN1EC2GSdfzAA+eOkhFHj2yXzM=; b=jXH9fennGt0WMl9MXEklbZEatZfIsppql/AoHWSiUUII+kmEYK0S+vypQl7OpnrrNe QJYnHQW9hcfsU7+kjoJx8LecNrxJ8Y+/11wVFcs+h6OhLpQ/zY8xJhsVpvmEcb4W5Z2h TlS0qGx5jGJVJINLkPU983g2I8ulvklZVI/+dVVSJdzOJco3qugcb4Ixc/WPkkKRLFo+ zdAQKGQb84+oD65RnYAUNTTyWNMHSDgKDtf9ZyWxFvIPdxmyBGWGgYyEJlG3ZWwCkgcc YLogRHwjcxobCZ+Bt3U3QZoGECfEHs2GARDoqsJ+EHMElH3ODF0m0CIp+soaHYV1Dl73 a+gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680728585; x=1683320585; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F2bBVJ77D9HA2dPUKZN1EC2GSdfzAA+eOkhFHj2yXzM=; b=ru3b4hnr2t/ddGQHZ5owRmckyqD6/90R/vPFRI9NbWZDgdWWNliiAs7Gh1I2t/+oUy zbgP2npyjGeyYSVV+UoNGBbm8TzOO8oOrpDLaHNVuqB7JijNyJFMGQHARaYlZK19TZUt hliFFLT/a7nqfW38anC3ROjrxP8n/o2ATJJhfrG8sORBLH1P0IZn8h2Gd98D2h24l0l9 R9AakELw00pknilur8mU73+wxip3vw9CWORVJn+YY+weXJ1YfiLqb/mknwhPefNhjTR2 pxkqtLhfqas6gK0QtpQVpWeMjgTLvvTyHuzKP6UIBxTTjJUbMBeJ9cTLLMxFq1ISXeHv MlKw== X-Gm-Message-State: AAQBX9d0uWd+UJRY260KYBPC7ckvBbuV0WqaLX+WqaqLivIKzqzWra2x dtznRc5kohT/XHcIyK/UQ6lCpY2KNyXfxOggedt3+BKFQEM= X-Google-Smtp-Source: AKy350Ys76o/eft7sXtZv9I5KZ/qSVPPM44QiyJ+Hqhx5dcwwTsmHcQpQsPqadqHS6/CpS2a57wq4w== X-Received: by 2002:a17:90b:4f42:b0:234:4187:1acc with SMTP id pj2-20020a17090b4f4200b0023441871accmr3736728pjb.19.1680728584903; Wed, 05 Apr 2023 14:03:04 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id e6-20020a17090a77c600b002342ccc8280sm1809477pjs.6.2023.04.05.14.03.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 14:03:04 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jeffreyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 5/8] RISCV: Eliminate AMO op fences Date: Wed, 5 Apr 2023 14:01:15 -0700 Message-Id: <20230405210118.1969283-6-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405210118.1969283-1-patrick@rivosinc.com> References: <20220407182918.294892-1-patrick@rivosinc.com> <20230405210118.1969283-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Atomic operations with the appropriate bits set already enfore release semantics. Remove unnecessary release fences from atomic ops. This change brings AMO ops in line with table A.6 of the ISA manual. 2023-04-05 Patrick O'Neill * riscv.cc (riscv_memmodel_needs_amo_acquire): Change function name. * riscv.cc (riscv_print_operand): Remove unneeded %F case. * sync.md: Remove unneeded fences. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 16 +++++----------- gcc/config/riscv/sync.md | 16 ++++++++-------- 2 files changed, 13 insertions(+), 19 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8ffee494fbe..6576e9ae524 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4301,11 +4301,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) } } -/* Return true if a FENCE should be emitted to before a memory access to - implement the release portion of memory model MODEL. */ +/* Return true if the .RL suffix should be added to an AMO to implement the + release portion of memory model MODEL. */ static bool -riscv_memmodel_needs_release_fence (enum memmodel model) +riscv_memmodel_needs_amo_release (enum memmodel model) { switch (model) { @@ -4331,7 +4331,6 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. - 'F' Print a FENCE if the memory model requires a release. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -4493,19 +4492,14 @@ riscv_print_operand (FILE *file, rtx op, int letter) case 'A': if (riscv_memmodel_needs_amo_acquire (model) && - riscv_memmodel_needs_release_fence (model)) + riscv_memmodel_needs_amo_release (model)) fputs (".aqrl", file); else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); - else if (riscv_memmodel_needs_release_fence (model)) + else if (riscv_memmodel_needs_amo_release (model)) fputs (".rl", file); break; - case 'F': - if (riscv_memmodel_needs_release_fence (model)) - fputs ("fence iorw,ow; ", file); - break; - case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index de42245981b..1aa9ac81cee 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -61,9 +61,9 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "TARGET_ATOMIC" - "%F2amoswap.%A2 zero,%z1,%0" + "amoswap.%A2 zero,%z1,%0" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") @@ -73,9 +73,9 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F2amo.%A2 zero,%z1,%0" + "amo.%A2 zero,%z1,%0" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -87,9 +87,9 @@ (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F3amo.%A3 %0,%z2,%1" + "amo.%A3 %0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -100,9 +100,9 @@ (set (match_dup 1) (match_operand:GPR 2 "register_operand" "0"))] "TARGET_ATOMIC" - "%F3amoswap.%A3 %0,%z2,%1" + "amoswap.%A3 %0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_cas_value_strong" [(set (match_operand:GPR 0 "register_operand" "=&r") -- 2.25.1