From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by sourceware.org (Postfix) with ESMTPS id B03C13857005 for ; Wed, 5 Apr 2023 21:03:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B03C13857005 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x644.google.com with SMTP id kq3so35573826plb.13 for ; Wed, 05 Apr 2023 14:03:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1680728589; x=1683320589; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pcNYn56UjLOYIUhjeLtRwQBit+o1zbjbdDRd9Ok0HAE=; b=mRU7bHdbkN/ywjIDM6oGKkQAiXAw9nHW4Lai6j72fS3NiKpophaLHv5sMY10sH5NvS J4vBY1pZk1neXTRPedwX34udocsSViR7VmcuWh8OEWq7AB7wsER9vuZpg4e2gZrKAzA8 eCIXaK6sv/M44Q4fieAp7/Ykr1SBbSL5AdJdrh32wo0Poedd1ZuLjZkcD/T0yJBb0b3B bxWd502U/nNF7IUTFDkwBaIP9vrK4VzNs5cHwvgemcQJ96lki8qcapFRlJyDnnRt7AiX fkORjZi3Q9DXSAzzsA0k78hhSqFNJn2Lr7JmsYdwDdJ0Dvchx2DZ2Xe/71Y3QdUfHMm2 v71g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680728589; x=1683320589; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pcNYn56UjLOYIUhjeLtRwQBit+o1zbjbdDRd9Ok0HAE=; b=rZZCnJq2KeXiER+F0YPluqiYYTzRnuhyHcKzTcLnEF76eBpRxWGrDCQIGvkWAqO11q R/8GKK92HRrpN0Asp03xxWQHCAuEtxbPKP5QTPfTldjE+HbvajuqVK2dGCXGF+iv0msH c72a1k8SgiGnAUVFN7Rs4a/Gl5e78EyBswtx+5M23WfWMi4f+Qh+KY3ACxIIdAATqD4L l4bk2WePac0VsDJGF+qg2530baxb5Mupa3nHU5hIWQkMe3yIi7l+9aOmrWRy9LsJVntw PjyAyhXbb6XyZH8TP2z2DSKbULYIpLnHDNYubga0b1P3TJSuhPJvnvuYF5VcKRMD+h/l 9GlQ== X-Gm-Message-State: AAQBX9divau+7dbftHHd1yg9Mm7Ox4gIGzyelw0hSss+VRs2HzTM2pxG lQu5W8O3p4z12WxaUHl/+nFgVhQuhuQ2Pmkbo8u7pSMmMiM= X-Google-Smtp-Source: AKy350Y05e4SOENRF41vmQ/ShdOuODxEQlvs7z10sEOZPtgX6HJ69kj8nFcaS2VjK7eFGmpD1z/6dQ== X-Received: by 2002:a17:90b:4c92:b0:23f:635e:51e9 with SMTP id my18-20020a17090b4c9200b0023f635e51e9mr8432006pjb.8.1680728589402; Wed, 05 Apr 2023 14:03:09 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id e6-20020a17090a77c600b002342ccc8280sm1809477pjs.6.2023.04.05.14.03.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 14:03:08 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jeffreyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 8/8] RISCV: Weaken mem_thread_fence Date: Wed, 5 Apr 2023 14:01:18 -0700 Message-Id: <20230405210118.1969283-9-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405210118.1969283-1-patrick@rivosinc.com> References: <20220407182918.294892-1-patrick@rivosinc.com> <20230405210118.1969283-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This change brings atomic fences in line with table A.6 of the ISA manual. Relax mem_thread_fence according to the memmodel given. 2023-04-05 Patrick O'Neill * riscv.cc: Expose helper functions to sync.md. * riscv-protos.h: Likewise. * sync.md (mem_thread_fence_1): Change fence depending on aquire/release requirements. * amo-thread-fence-1: New test. * amo-thread-fence-2: Likewise. * amo-thread-fence-3: Likewise. * amo-thread-fence-4: Likewise. * amo-thread-fence-5: Likewise. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv-protos.h | 2 ++ gcc/config/riscv/riscv.cc | 4 ++-- gcc/config/riscv/sync.md | 17 ++++++++++++++--- .../gcc.target/riscv/amo-thread-fence-1.c | 6 ++++++ .../gcc.target/riscv/amo-thread-fence-2.c | 6 ++++++ .../gcc.target/riscv/amo-thread-fence-3.c | 6 ++++++ .../gcc.target/riscv/amo-thread-fence-4.c | 6 ++++++ .../gcc.target/riscv/amo-thread-fence-5.c | 6 ++++++ 8 files changed, 48 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index b03edc3e8a5..233b8070047 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -81,6 +81,8 @@ extern void riscv_reinit (void); extern poly_uint64 riscv_regmode_natural_size (machine_mode); extern bool riscv_v_ext_vector_mode_p (machine_mode); extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); +extern bool riscv_memmodel_needs_amo_acquire (enum memmodel); +extern bool riscv_memmodel_needs_amo_release (enum memmodel); extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); /* Routines implemented in riscv-c.cc. */ diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 061d2cf42b4..27d876ac44c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4311,7 +4311,7 @@ riscv_union_memmodels (enum memmodel model1, enum memmodel model2) /* Return true if the .AQ suffix should be added to an AMO to implement the acquire portion of memory model MODEL. */ -static bool +bool riscv_memmodel_needs_amo_acquire (enum memmodel model) { switch (model) @@ -4334,7 +4334,7 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) /* Return true if the .RL suffix should be added to an AMO to implement the release portion of memory model MODEL. */ -static bool +bool riscv_memmodel_needs_amo_release (enum memmodel model) { switch (model) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index cdd227721e1..4204c956bd6 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -42,14 +42,25 @@ DONE; }) -;; Until the RISC-V memory model (hence its mapping from C++) is finalized, -;; conservatively emit a full FENCE. (define_insn "mem_thread_fence_1" [(set (match_operand:BLK 0 "" "") (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (match_operand:SI 1 "const_int_operand" "")] ;; model "" - "fence\tiorw,iorw") + { + enum memmodel model = (enum memmodel) INTVAL (operands[1]); + model = memmodel_base (model); + if (model == MEMMODEL_ACQ_REL) + return "fence.tso"; + else if (riscv_memmodel_needs_amo_acquire (model) && + riscv_memmodel_needs_amo_release (model)) + return "fence\trw,rw"; + else if (riscv_memmodel_needs_amo_acquire (model)) + return "fence\tr,rw"; + else if (riscv_memmodel_needs_amo_release (model)) + return "fence\trw,w"; + } + [(set (attr "length") (const_int 4))]) ;; Atomic memory operations. diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c new file mode 100644 index 00000000000..833629bf2f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-final { scan-assembler-not "fence\t" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c new file mode 100644 index 00000000000..3395ee41dbb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-final { scan-assembler "fence\tr,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c new file mode 100644 index 00000000000..59cc4e5d394 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-final { scan-assembler "fence\trw,w" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c new file mode 100644 index 00000000000..2afed9a9e38 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-final { scan-assembler "fence.tso" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c new file mode 100644 index 00000000000..b8d56c0f066 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-final { scan-assembler "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_SEQ_CST); +} -- 2.25.1