public inbox for gcc-patches@gcc.gnu.org
 help / color / mirror / Atom feed
From: juzhe.zhong@rivai.ai
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com,
	richard.sandiford@arm.com, rguenther@suse.de,
	jeffreyalaw@gmail.com, Juzhe-Zhong <juzhe.zhong@rivai.ai>
Subject: [PATCH 0/3] RISC-V:Enable basic auto-vectorization for RVV
Date: Thu,  6 Apr 2023 22:42:19 +0800	[thread overview]
Message-ID: <20230406144222.316395-1-juzhe.zhong@rivai.ai> (raw)

From: Juzhe-Zhong <juzhe.zhong@rivai.ai>

PATCH 1: Add WHILE_LEN pattern in Loop Vectorizer to support decrement IV for RVV.
PATCH 2: Enable basic auto-vectorization for RVV in RISC-V port.
PATCH 3: Add testcases for basic RVV auto-vectorization of WHILE_LEN pattern 
         includeing single rgroup test and multiple rgroup test of SLP.

*** BLURB HERE ***

Juzhe-Zhong (3):
  VECT: Add WHILE_LEN pattern to support decrement IV manipulation for
    loop vectorizer.
  RISC-V: Enable basic RVV auto-vectorization and support
    WHILE_LEN/LEN_LOAD/LEN_STORE pattern
  RISC-V: Add testcase for basic RVV auto-vectorization

 gcc/config/riscv/autovec.md                   |  63 ++
 gcc/config/riscv/riscv-opts.h                 |  16 +
 gcc/config/riscv/riscv-protos.h               |   3 +-
 gcc/config/riscv/riscv-v.cc                   |  61 +-
 gcc/config/riscv/riscv-vector-switch.def      |  47 +-
 gcc/config/riscv/riscv-vsetvl.cc              | 210 ++++-
 gcc/config/riscv/riscv-vsetvl.h               |   1 +
 gcc/config/riscv/riscv.cc                     |  34 +-
 gcc/config/riscv/riscv.opt                    |  40 +
 gcc/config/riscv/vector.md                    |   6 +-
 gcc/doc/md.texi                               |  14 +
 gcc/internal-fn.cc                            |  29 +
 gcc/internal-fn.def                           |   1 +
 gcc/optabs.def                                |   1 +
 gcc/testsuite/gcc.target/riscv/rvv/api/vadc.c | 361 ++++++++
 gcc/testsuite/gcc.target/riscv/rvv/api/vadd.c | 713 ++++++++++++++++
 gcc/testsuite/gcc.target/riscv/rvv/api/vand.c | 713 ++++++++++++++++
 .../gcc.target/riscv/rvv/api/vcpop.c          |  65 ++
 gcc/testsuite/gcc.target/riscv/rvv/api/vdiv.c | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vdivu.c          | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vfirst.c         |  65 ++
 gcc/testsuite/gcc.target/riscv/rvv/api/vid.c  | 185 +++++
 .../gcc.target/riscv/rvv/api/viota.c          | 185 +++++
 .../gcc.target/riscv/rvv/api/vle16.c          | 105 +++
 .../gcc.target/riscv/rvv/api/vle32.c          | 129 +++
 .../gcc.target/riscv/rvv/api/vle64.c          |  73 ++
 gcc/testsuite/gcc.target/riscv/rvv/api/vle8.c | 121 +++
 gcc/testsuite/gcc.target/riscv/rvv/api/vlm.c  |  37 +
 .../gcc.target/riscv/rvv/api/vloxei16.c       | 385 +++++++++
 .../gcc.target/riscv/rvv/api/vloxei32.c       | 353 ++++++++
 .../gcc.target/riscv/rvv/api/vloxei64.c       | 297 +++++++
 .../gcc.target/riscv/rvv/api/vloxei8.c        | 401 +++++++++
 .../gcc.target/riscv/rvv/api/vlse16.c         | 105 +++
 .../gcc.target/riscv/rvv/api/vlse32.c         | 129 +++
 .../gcc.target/riscv/rvv/api/vlse64.c         |  73 ++
 .../gcc.target/riscv/rvv/api/vlse8.c          | 121 +++
 .../gcc.target/riscv/rvv/api/vluxei16.c       | 385 +++++++++
 .../gcc.target/riscv/rvv/api/vluxei32.c       | 353 ++++++++
 .../gcc.target/riscv/rvv/api/vluxei64.c       | 297 +++++++
 .../gcc.target/riscv/rvv/api/vluxei8.c        | 401 +++++++++
 .../gcc.target/riscv/rvv/api/vmacc.c          | 713 ++++++++++++++++
 .../gcc.target/riscv/rvv/api/vmadc.c          | 713 ++++++++++++++++
 .../gcc.target/riscv/rvv/api/vmadd.c          | 713 ++++++++++++++++
 .../gcc.target/riscv/rvv/api/vmand.c          |  37 +
 .../gcc.target/riscv/rvv/api/vmandn.c         |  37 +
 gcc/testsuite/gcc.target/riscv/rvv/api/vmax.c | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vmaxu.c          | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vmclr.c          |  37 +
 .../gcc.target/riscv/rvv/api/vmerge.c         | 361 ++++++++
 gcc/testsuite/gcc.target/riscv/rvv/api/vmin.c | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vminu.c          | 361 ++++++++
 gcc/testsuite/gcc.target/riscv/rvv/api/vmmv.c |  37 +
 .../gcc.target/riscv/rvv/api/vmnand.c         |  37 +
 .../gcc.target/riscv/rvv/api/vmnor.c          |  37 +
 .../gcc.target/riscv/rvv/api/vmnot.c          |  37 +
 gcc/testsuite/gcc.target/riscv/rvv/api/vmor.c |  37 +
 .../gcc.target/riscv/rvv/api/vmorn.c          |  37 +
 .../gcc.target/riscv/rvv/api/vmsbc.c          | 713 ++++++++++++++++
 .../gcc.target/riscv/rvv/api/vmsbf.c          |  65 ++
 .../gcc.target/riscv/rvv/api/vmseq.c          | 713 ++++++++++++++++
 .../gcc.target/riscv/rvv/api/vmset.c          |  37 +
 .../gcc.target/riscv/rvv/api/vmsge.c          | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vmsgeu.c         | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vmsgt.c          | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vmsgtu.c         | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vmsif.c          |  65 ++
 .../gcc.target/riscv/rvv/api/vmsle.c          | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vmsleu.c         | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vmslt.c          | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vmsltu.c         | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vmsne.c          | 713 ++++++++++++++++
 .../gcc.target/riscv/rvv/api/vmsof.c          |  65 ++
 gcc/testsuite/gcc.target/riscv/rvv/api/vmul.c | 713 ++++++++++++++++
 .../gcc.target/riscv/rvv/api/vmulh.c          | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vmulhsu.c        | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vmulhu.c         | 361 ++++++++
 gcc/testsuite/gcc.target/riscv/rvv/api/vmv.c  | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vmxnor.c         |  37 +
 .../gcc.target/riscv/rvv/api/vmxor.c          |  37 +
 gcc/testsuite/gcc.target/riscv/rvv/api/vneg.c | 185 +++++
 .../gcc.target/riscv/rvv/api/vnmsac.c         | 713 ++++++++++++++++
 .../gcc.target/riscv/rvv/api/vnmsub.c         | 713 ++++++++++++++++
 gcc/testsuite/gcc.target/riscv/rvv/api/vnot.c | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vnsra.c          | 249 ++++++
 .../gcc.target/riscv/rvv/api/vnsrl.c          | 249 ++++++
 gcc/testsuite/gcc.target/riscv/rvv/api/vor.c  | 713 ++++++++++++++++
 gcc/testsuite/gcc.target/riscv/rvv/api/vrem.c | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vremu.c          | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vrsub.c          | 361 ++++++++
 gcc/testsuite/gcc.target/riscv/rvv/api/vsbc.c | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vse16.c          | 105 +++
 .../gcc.target/riscv/rvv/api/vse32.c          | 129 +++
 .../gcc.target/riscv/rvv/api/vse64.c          |  73 ++
 gcc/testsuite/gcc.target/riscv/rvv/api/vse8.c | 121 +++
 .../gcc.target/riscv/rvv/api/vsetvl.c         |  97 +++
 .../gcc.target/riscv/rvv/api/vsetvlmax.c      |  97 +++
 .../gcc.target/riscv/rvv/api/vsext_vf2.c      | 129 +++
 .../gcc.target/riscv/rvv/api/vsext_vf4.c      |  81 ++
 .../gcc.target/riscv/rvv/api/vsext_vf8.c      |  41 +
 gcc/testsuite/gcc.target/riscv/rvv/api/vsll.c | 713 ++++++++++++++++
 gcc/testsuite/gcc.target/riscv/rvv/api/vsm.c  |  37 +
 .../gcc.target/riscv/rvv/api/vsoxei16.c       | 385 +++++++++
 .../gcc.target/riscv/rvv/api/vsoxei32.c       | 353 ++++++++
 .../gcc.target/riscv/rvv/api/vsoxei64.c       | 297 +++++++
 .../gcc.target/riscv/rvv/api/vsoxei8.c        | 401 +++++++++
 gcc/testsuite/gcc.target/riscv/rvv/api/vsra.c | 361 ++++++++
 gcc/testsuite/gcc.target/riscv/rvv/api/vsrl.c | 361 ++++++++
 .../gcc.target/riscv/rvv/api/vsse16.c         | 105 +++
 .../gcc.target/riscv/rvv/api/vsse32.c         | 129 +++
 .../gcc.target/riscv/rvv/api/vsse64.c         |  73 ++
 .../gcc.target/riscv/rvv/api/vsse8.c          | 121 +++
 gcc/testsuite/gcc.target/riscv/rvv/api/vsub.c | 713 ++++++++++++++++
 .../gcc.target/riscv/rvv/api/vsuxei16.c       | 385 +++++++++
 .../gcc.target/riscv/rvv/api/vsuxei32.c       | 353 ++++++++
 .../gcc.target/riscv/rvv/api/vsuxei64.c       | 297 +++++++
 .../gcc.target/riscv/rvv/api/vsuxei8.c        | 401 +++++++++
 .../gcc.target/riscv/rvv/api/vwadd.c          | 489 +++++++++++
 .../gcc.target/riscv/rvv/api/vwaddu.c         | 489 +++++++++++
 .../gcc.target/riscv/rvv/api/vwmacc.c         | 249 ++++++
 .../gcc.target/riscv/rvv/api/vwmaccsu.c       | 249 ++++++
 .../gcc.target/riscv/rvv/api/vwmaccu.c        | 249 ++++++
 .../gcc.target/riscv/rvv/api/vwmaccus.c       | 129 +++
 .../gcc.target/riscv/rvv/api/vwmul.c          | 249 ++++++
 .../gcc.target/riscv/rvv/api/vwmulsu.c        | 249 ++++++
 .../gcc.target/riscv/rvv/api/vwmulu.c         | 249 ++++++
 .../gcc.target/riscv/rvv/api/vwsub.c          | 489 +++++++++++
 .../gcc.target/riscv/rvv/api/vwsubu.c         | 489 +++++++++++
 gcc/testsuite/gcc.target/riscv/rvv/api/vxor.c | 713 ++++++++++++++++
 .../gcc.target/riscv/rvv/api/vzext_vf2.c      | 129 +++
 .../gcc.target/riscv/rvv/api/vzext_vf4.c      |  81 ++
 .../gcc.target/riscv/rvv/api/vzext_vf8.c      |  41 +
 .../rvv/autovec/partial/multiple_rgroup-1.c   |   6 +
 .../rvv/autovec/partial/multiple_rgroup-1.h   | 304 +++++++
 .../rvv/autovec/partial/multiple_rgroup-2.c   |   6 +
 .../rvv/autovec/partial/multiple_rgroup-2.h   | 546 ++++++++++++
 .../rvv/autovec/partial/multiple_rgroup-2.s   | 774 ++++++++++++++++++
 .../autovec/partial/multiple_rgroup_run-1.c   |  19 +
 .../autovec/partial/multiple_rgroup_run-2.c   |  19 +
 .../rvv/autovec/partial/single_rgroup-1.c     |   8 +
 .../rvv/autovec/partial/single_rgroup-1.h     | 106 +++
 .../rvv/autovec/partial/single_rgroup_run-1.c |  19 +
 .../gcc.target/riscv/rvv/autovec/template-1.h |  68 ++
 .../gcc.target/riscv/rvv/autovec/v-1.c        |   4 +
 .../gcc.target/riscv/rvv/autovec/v-2.c        |   6 +
 .../gcc.target/riscv/rvv/autovec/zve32f-1.c   |   4 +
 .../gcc.target/riscv/rvv/autovec/zve32f-2.c   |   5 +
 .../riscv/rvv/autovec/zve32f_zvl128b-1.c      |   4 +
 .../riscv/rvv/autovec/zve32f_zvl128b-2.c      |   6 +
 .../gcc.target/riscv/rvv/autovec/zve32x-1.c   |   4 +
 .../gcc.target/riscv/rvv/autovec/zve32x-2.c   |   6 +
 .../riscv/rvv/autovec/zve32x_zvl128b-1.c      |   5 +
 .../riscv/rvv/autovec/zve32x_zvl128b-2.c      |   6 +
 .../gcc.target/riscv/rvv/autovec/zve64d-1.c   |   4 +
 .../gcc.target/riscv/rvv/autovec/zve64d-2.c   |   4 +
 .../riscv/rvv/autovec/zve64d_zvl128b-1.c      |   4 +
 .../riscv/rvv/autovec/zve64d_zvl128b-2.c      |   6 +
 .../gcc.target/riscv/rvv/autovec/zve64f-1.c   |   4 +
 .../gcc.target/riscv/rvv/autovec/zve64f-2.c   |   4 +
 .../riscv/rvv/autovec/zve64f_zvl128b-1.c      |   4 +
 .../riscv/rvv/autovec/zve64f_zvl128b-2.c      |   6 +
 .../gcc.target/riscv/rvv/autovec/zve64x-1.c   |   4 +
 .../gcc.target/riscv/rvv/autovec/zve64x-2.c   |   4 +
 .../riscv/rvv/autovec/zve64x_zvl128b-1.c      |   4 +
 .../riscv/rvv/autovec/zve64x_zvl128b-2.c      |   6 +
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp    |  16 +
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-17.c   |   2 +-
 gcc/tree-ssa-loop-manip.cc                    |   4 +-
 gcc/tree-ssa-loop-manip.h                     |   2 +-
 gcc/tree-vect-loop-manip.cc                   | 186 ++++-
 gcc/tree-vect-loop.cc                         |  35 +-
 gcc/tree-vect-stmts.cc                        |   9 +-
 gcc/tree-vectorizer.h                         |   4 +-
 172 files changed, 36786 insertions(+), 46 deletions(-)
 create mode 100644 gcc/config/riscv/autovec.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vadc.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vadd.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vand.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vcpop.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vdiv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vdivu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vfirst.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vid.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/viota.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vle16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vle32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vle64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vle8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vlm.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vloxei16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vloxei32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vloxei64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vloxei8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vlse16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vlse32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vlse64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vlse8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vluxei16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vluxei32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vluxei64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vluxei8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmacc.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmadc.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmadd.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmand.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmandn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmax.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmaxu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmclr.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmerge.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmin.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vminu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmmv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmnand.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmnor.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmnot.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmor.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmorn.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmsbc.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmsbf.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmseq.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmset.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmsge.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmsgeu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmsgt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmsgtu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmsif.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmsle.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmsleu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmslt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmsltu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmsne.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmsof.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmul.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmulh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmulhsu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmulhu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmv.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmxnor.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vmxor.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vneg.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vnmsac.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vnmsub.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vnot.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vnsra.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vnsrl.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vor.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vrem.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vremu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vrsub.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsbc.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vse16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vse32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vse64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vse8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsetvl.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsetvlmax.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsext_vf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsext_vf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsext_vf8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsll.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsm.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsoxei16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsoxei32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsoxei64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsoxei8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsra.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsrl.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsse16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsse32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsse64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsse8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsub.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsuxei16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsuxei32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsuxei64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vsuxei8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vwadd.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vwaddu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vwmacc.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vwmaccsu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vwmaccu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vwmaccus.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vwmul.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vwmulsu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vwmulu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vwsub.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vwsubu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vxor.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vzext_vf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vzext_vf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/api/vzext_vf8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-1.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.s
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/template-1.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c

-- 
2.36.3


             reply	other threads:[~2023-04-06 14:42 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-06 14:42 juzhe.zhong [this message]
2023-04-06 14:42 ` [PATCH 1/3] VECT: Add WHILE_LEN pattern to support decrement IV manipulation for loop vectorizer juzhe.zhong
2023-04-06 14:42 ` [PATCH 2/3] RISC-V: Enable basic RVV auto-vectorization and support WHILE_LEN/LEN_LOAD/LEN_STORE pattern juzhe.zhong
2023-04-06 16:04   ` Kito Cheng
2023-04-07  1:40     ` juzhe.zhong
2023-04-06 14:42 ` [PATCH] RISC-V: Add RVV auto-vectorization testcase juzhe.zhong
2023-04-06 15:36   ` Kito Cheng

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230406144222.316395-1-juzhe.zhong@rivai.ai \
    --to=juzhe.zhong@rivai.ai \
    --cc=gcc-patches@gcc.gnu.org \
    --cc=jeffreyalaw@gmail.com \
    --cc=kito.cheng@gmail.com \
    --cc=palmer@dabbelt.com \
    --cc=rguenther@suse.de \
    --cc=richard.sandiford@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).