From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) by sourceware.org (Postfix) with ESMTPS id A0F903858C52 for ; Mon, 10 Apr 2023 18:26:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A0F903858C52 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x641.google.com with SMTP id la3so5211777plb.11 for ; Mon, 10 Apr 2023 11:26:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1681151209; x=1683743209; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MBTrnOr4+Zh6gREbG3fG9zaaGf0S8XaU8Hkqx25mYGA=; b=x2fOWCZuXpEdxXtJ40KFUZ5spj7lBf3Ib2BY89S0YlFS9cQ8gDV5YBhsBop8MvjpzY GytoxDeqUAlWgi1WJrzFEr1FUMyi4RRljrEpGraC+IKjRIsxJH18IQ9CFe/V4wVvVG5M UbIc7gQUNXAig6VVfH1HCi48cbwhVIc3z56mB2zvMKUHr0Up9scJJir0dyEygkzmcOI3 FT6BFN50WK1TFGu4AwXJDdVpvdpiSpE7uI2FQIbNA/PmXB6yMJNnrN/BvbyqtRTihZMz 38Py1k2wOBXKG9c9YrJw30qSBW/cYSsOsijH9nqXUohrRT41CCeslSix6NE7fsULfDBG bYIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681151209; x=1683743209; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MBTrnOr4+Zh6gREbG3fG9zaaGf0S8XaU8Hkqx25mYGA=; b=gAdEI2vgDjarcx6ZD/vdbZeeOIro5FuVGP5f/qFobL14GmFYe0rSVPVzBs8RmNTfF/ +EMhyHB2DY+HuEktXGpiu6JhEQmU2yvCxAN6wWFDKyJ6xmJp0tl9vHq8UOdnV2nERF8G qICGRuf96VSZNpqwKHtIhg7lQrD8CNqqJI2YfLzbjK3tKQG4TfefKBQVYmW2U06hzJqQ JNpcI+9jjvDYUTU+FNzsKKxsiTDQ+hDPCiNuVwWO+gE5gTYh9n86B9Dh+DjQadbRPyGo FwQEevxsbHbqXkCKFVhwW8vrmvhjzlJRCgPAIbpc6bML+9ogYe4y34KLJUHc5Rjr1QbW RJXw== X-Gm-Message-State: AAQBX9d4QEMOTco8bPw9KYZXH2J1mPQB8u/ZiEGorx08ZpSALy2c4QWc JQFIf9Dy1NMV1Lsgs+pXbTP4iIzZteTQJYkGqi81sChCE9Q= X-Google-Smtp-Source: AKy350a/Ty6WohnEjVlYyQJH5DG7f3Pu93OWJnkLfqR9eWVsSfYy3au7kWte5hF81LNQphEugm1jOg== X-Received: by 2002:a05:6a20:6525:b0:da:c40:8d8 with SMTP id n37-20020a056a20652500b000da0c4008d8mr12048884pzg.4.1681151209374; Mon, 10 Apr 2023 11:26:49 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id d2-20020aa78e42000000b00627f054a3cdsm4478977pfr.31.2023.04.10.11.26.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 11:26:49 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jefferyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill Subject: [PATCH v3 00/10] RISCV: Implement ISA Manual Table A.6 Mappings Date: Mon, 10 Apr 2023 11:23:38 -0700 Message-Id: <20230410182348.2168356-1-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405210118.1969283-1-patrick@rivosinc.com> References: <20230405210118.1969283-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patchset aims to make the RISCV atomics implementation stronger than the recommended mapping present in table A.6 of the ISA manual. https://github.com/riscv/riscv-isa-manual/blob/c7cf84547b3aefacab5463add1734c1602b67a49/src/memory.tex#L1083-L1157 The current mapping in GCC is not internally consistent. Andrea Parri pointed this out here along with a litmus test: https://inbox.sourceware.org/gcc-patches/Y1GbJuhcBFpPGJQ0@andrea/ As a result, we have an opportunity to jump straight to the A.6 implementation (meaning we will be compatible with LLVM's mappings which are A.6). In light of a proposal by Hans Boehm and to avoid an ABI break in the future, the mapping implemented is strictly stronger than the one in table A.6 in order to be compatible with Table A.7. https://lists.riscv.org/g/tech-unprivileged/topic/risc_v_memory_model_topics/92916241 If Hans' proposal is accepted, it makes sense to migrate to the mapping recommended by table A.7. Since the stronger mapping in this patchset (provided by Hans Boehm) appears to be compatible with both A.6 and A.7, this transition should not result in an ABI break for GCC. Patch 1 simplifies the memmodel to ignore MEMMODEL_SYNC_* cases (legacy cases that aren't handled differently for RISC-V). Patches 2-5 make the mappings strictly stronger. Patches 5-9 weaken the mappings to be in line with table A.6 of the ISA manual. Patch 10 adds some basic conformance tests to ensure the implemented mapping matches table A.6 with stronger SEQ_CST stores. Christoph Muellner also submitted a similar patchset here: https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595712.html I used my previous patchset as a starting point since it was easier for me. LLVM mapping notes: * LLVM emits corresponding fences for atomic_signal_fence instructions. This seems to be an oversight since AFAIK atomic_signal_fence acts as a compiler directive. GCC does not emit any fences for atomic_signal_fence instructions. Patchset v1: https://gcc.gnu.org/pipermail/gcc-patches/2022-April/592950.html Patchset v2: https://gcc.gnu.org/pipermail/gcc-patches/2023-April/615264.html Changes for v2: * Use memmodel_base rather than a custom simplify_memmodel function (Inspired by Christoph Muellner's patch 1/9) * Move instruction styling change from [v1 5/7] to [v2 3/8] to reduce [v2 6/8]'s complexity * Eliminated %K flag for atomic store introduced in v1 in favor of if/else * Rebase/test Changes for v3: * Use a trailing fence for atomic stores to be compatible with Table A.7 * Emit an optimized fence r,rw following a SEQ_CST load * Consolidate tests in [PATCH v3 10/10] * Add tests for basic A.6 conformance Patrick O'Neill (10): RISCV: Eliminate SYNC memory models RISCV: Enforce Libatomic LR/SC SEQ_CST RISCV: Enforce atomic compare_exchange SEQ_CST RISCV: Add AMO release bits RISCV: Strengthen atomic stores RISCV: Eliminate AMO op fences RISCV: Weaken compare_exchange LR/SC pairs RISCV: Weaken mem_thread_fence RISCV: Weaken atomic loads RISCV: Table A.6 conformance tests gcc/config/riscv/riscv-protos.h | 3 + gcc/config/riscv/riscv.cc | 66 +++++++++++--- gcc/config/riscv/sync.md | 89 ++++++++++++++++--- .../riscv/amo-table-a-6-amo-add-1.c | 8 ++ .../riscv/amo-table-a-6-amo-add-2.c | 8 ++ .../riscv/amo-table-a-6-amo-add-3.c | 8 ++ .../riscv/amo-table-a-6-amo-add-4.c | 8 ++ .../riscv/amo-table-a-6-amo-add-5.c | 8 ++ .../riscv/amo-table-a-6-compare-exchange-1.c | 12 +++ .../riscv/amo-table-a-6-compare-exchange-2.c | 12 +++ .../riscv/amo-table-a-6-compare-exchange-3.c | 12 +++ .../riscv/amo-table-a-6-compare-exchange-4.c | 12 +++ .../riscv/amo-table-a-6-compare-exchange-5.c | 12 +++ .../gcc.target/riscv/amo-table-a-6-fence-1.c | 9 ++ .../gcc.target/riscv/amo-table-a-6-fence-2.c | 7 ++ .../gcc.target/riscv/amo-table-a-6-fence-3.c | 7 ++ .../gcc.target/riscv/amo-table-a-6-fence-4.c | 7 ++ .../gcc.target/riscv/amo-table-a-6-fence-5.c | 7 ++ .../gcc.target/riscv/amo-table-a-6-load-1.c | 9 ++ .../gcc.target/riscv/amo-table-a-6-load-2.c | 10 +++ .../gcc.target/riscv/amo-table-a-6-load-3.c | 10 +++ .../gcc.target/riscv/amo-table-a-6-store-1.c | 9 ++ .../gcc.target/riscv/amo-table-a-6-store-2.c | 10 +++ .../riscv/amo-table-a-6-store-compat-3.c | 10 +++ gcc/testsuite/gcc.target/riscv/pr89835.c | 9 ++ libgcc/config/riscv/atomic.c | 4 +- 26 files changed, 336 insertions(+), 30 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c -- 2.25.1