From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1044.google.com (mail-pj1-x1044.google.com [IPv6:2607:f8b0:4864:20::1044]) by sourceware.org (Postfix) with ESMTPS id B57853857709 for ; Mon, 10 Apr 2023 18:27:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B57853857709 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pj1-x1044.google.com with SMTP id y11-20020a17090a600b00b0024693e96b58so4148883pji.1 for ; Mon, 10 Apr 2023 11:27:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1681151220; x=1683743220; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hICO/UALe547y+spMLv5qw3uDM955E0hX92rb0QQAK4=; b=keOIHquggn/UAOlSUAwXxmne/AHfY0a9LMO7Uw5zWduCJyAHAVPFbxbvUDInqW+TRL GASLYMW5xLRXciKyMPJhOwXQHKVLyyEW+AdLknLJdKUlYwYgnxy2hbOqVFnGiGERyonP AsIHGhwzm0og3yLsF9oSrWo+FDEN7Ly08afwwEDlh7ANxjl5vhcL7oXq7AK2hQRZm774 FaD4HpVS4KSWao6SXRC1dDZ9yxNpntSndr362qVfTOGjECffkRnR8eMbPnDOEYP6Q+A4 2lqkk8eSbSwM6f8BOIokNzi7c+9nCb8ZMLxOJZNvMk9uExMtpndnf1TLIz1Qb8AId9cF jyYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681151220; x=1683743220; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hICO/UALe547y+spMLv5qw3uDM955E0hX92rb0QQAK4=; b=vmOQp7Ip4IlNe10W+N6+1lM1/fZFpireBFzLRxoR8rHJZvhkAsLjss0bUIpSRF+lrS Qg5h/eBS69jxTWb3Y8q7xVJeRJs3/N0sPUd1B8oL5GZ1kkTeaMb+5MLTs8ueHBQjNVRN mIM7dMvgBdjpM6t84p4BBwZT0GCek+lrASMz/tg/5gSR0blN5Lv06OG601xIlcANb99c 8bmPAMesnxfq3W+u7AI96aNzLq5sZKu1UM2nVe7maMwH9BGgspBQeKXoFVhzMy7z3PsV n1EiR6CrHGd7sVX92It8qb7hqQ7k22dxYou9HNfPrvRhlnXATfofGM6v/z+lID0nJott LC9w== X-Gm-Message-State: AAQBX9f01Er+LRHuFdjWLqqfrLWiq++qUCGnnQq2MeMr0OKBg4VdjCay tnWnso+2fGfbYodZkw26M5mvrFT9Npo3dnip1j0tDj8bDZs= X-Google-Smtp-Source: AKy350YpO7a3x9NpReXKAewMgMEcQxqorEj/38qoZEZ5/7T4Ats/xRsYu6CZNHKv0/d+kNT/JrTghA== X-Received: by 2002:a05:6a20:6055:b0:dd:ff4f:b856 with SMTP id s21-20020a056a20605500b000ddff4fb856mr14016086pza.26.1681151220651; Mon, 10 Apr 2023 11:27:00 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id d2-20020aa78e42000000b00627f054a3cdsm4478977pfr.31.2023.04.10.11.26.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 11:27:00 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jefferyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill Subject: [PATCH v3 09/10] RISCV: Weaken atomic loads Date: Mon, 10 Apr 2023 11:23:47 -0700 Message-Id: <20230410182348.2168356-10-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230410182348.2168356-1-patrick@rivosinc.com> References: <20230405210118.1969283-1-patrick@rivosinc.com> <20230410182348.2168356-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This change brings atomic loads in line with table A.6 of the ISA manual. 2023-04-10 Patrick O'Neill * sync.md (atomic_load): Implement atomic load mapping. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Add this patch --- gcc/config/riscv/sync.md | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index e91fa29da51..9e3685f5b1c 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -23,6 +23,7 @@ UNSPEC_COMPARE_AND_SWAP UNSPEC_SYNC_OLD_OP UNSPEC_SYNC_EXCHANGE + UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER ]) @@ -63,7 +64,31 @@ ;; Atomic memory operations. -;; Implement atomic stores with conservative fences. Fall back to fences for atomic loads. +(define_insn "atomic_load" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "TARGET_ATOMIC" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw\;" + "l\t%0,%1\;" + "fence\tr,rw"; + if (model == MEMMODEL_ACQUIRE) + return "l\t%0,%1\;" + "fence\tr,rw"; + else + return "l\t%0,%1"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 12))]) + +;; Implement atomic stores with conservative fences. ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. (define_insn "atomic_store" [(set (match_operand:GPR 0 "memory_operand" "=A") -- 2.25.1