From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by sourceware.org (Postfix) with ESMTPS id 2025B3858C1F for ; Mon, 10 Apr 2023 18:26:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2025B3858C1F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x644.google.com with SMTP id ke16so5314368plb.6 for ; Mon, 10 Apr 2023 11:26:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1681151212; x=1683743212; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mpiz+IroUbuQUn0qqwRGeBpz9rfAJCoFpiN82cMSkOM=; b=V82Redk8Gb2ZIKXTpKZSIWz7RqaiA+PdJdAdG+7sw1b5Fs++iXV7wdokMtQL/G0d/U X1ubT2+illeKc7MWaV/In60NdVhxTMfXOQ2LqN0Z0G4gn+aJgXhSKQMhyTMnADrORjQC VGhn5D9KvRNznpEzHL0zI8xYnZ1KSJWBm6hwnY5qqA1RB8t7WQe09x6WroO/tNWVE0XN JyKpIGJGKp0h6o7KIfczjC7Ioy02xSQhxhgVmuMSIpXY6Z72ohw9wf8hOSO+Gy+NhjhZ 9mS+dgPGLzf/sBJccUF8MV/1GL8lkcffBp0DvY48AKJjTKSEcFQCrZxvlPljsekCpJrL rHGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681151212; x=1683743212; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mpiz+IroUbuQUn0qqwRGeBpz9rfAJCoFpiN82cMSkOM=; b=j0TjN/HsJ1DCBZKF58IDsJ4FsntStbTtLSJ2XmK7c4hLjydxJ8XoKbyculf8pPklJe 3CjC4doL+/toKnrRWDOlwRp8SMrmu/24rLapcQYfaT1vaKKFcHZddf+nKtf4wduuBaIW 6OlOr6ETBR3IOvoI1WotRrA5eAKWEXcJ1XOvsUD3O8F8MXs6m+Ts3CBZ16pShgfLgDmN OG9PsYbvLrjVkzEoljNjPXdC9LeVyUPpnhdNizHqu5w+oC6+DXqMmrzGQFUEHkZ/BKox ICfbj9SnUktdnmGhJIrZmMjcQMZ8XLYR8iCShhAYPvJcDuhj46mtZar+shTXnLheA8Ad ZvwQ== X-Gm-Message-State: AAQBX9fLbZPd9bcec5P/44yXrJLqScH4ueCTmVIf1MvIBRzvvXUVHS9P uyvRwKYkohEbnc7qFqomseIDyndYXkUT/iYBb9R2Bh22dmk= X-Google-Smtp-Source: AKy350ZvTdXeFbIB9xqsbwg4j+n4TNfDqZSLHtpBzPbaK763OEX81GdUCpPdKDuap9hrtt2f3Iw+4Q== X-Received: by 2002:a05:6a20:a91f:b0:d5:9216:9182 with SMTP id cd31-20020a056a20a91f00b000d592169182mr8363476pzb.9.1681151212023; Mon, 10 Apr 2023 11:26:52 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id d2-20020aa78e42000000b00627f054a3cdsm4478977pfr.31.2023.04.10.11.26.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 11:26:51 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jefferyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill Subject: [PATCH v3 02/10] RISCV: Enforce Libatomic LR/SC SEQ_CST Date: Mon, 10 Apr 2023 11:23:40 -0700 Message-Id: <20230410182348.2168356-3-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230410182348.2168356-1-patrick@rivosinc.com> References: <20230405210118.1969283-1-patrick@rivosinc.com> <20230410182348.2168356-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs recommended by table A.6 of the ISA manual. 2023-04-10 Patrick O'Neill * atomic.c: Change LR.aq/SC.rl pairs into sequentially consistent LR.aqrl/SC.rl pair. Signed-off-by: Patrick O'Neill --- libgcc/config/riscv/atomic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libgcc/config/riscv/atomic.c b/libgcc/config/riscv/atomic.c index 69f53623509..5f895939b0b 100644 --- a/libgcc/config/riscv/atomic.c +++ b/libgcc/config/riscv/atomic.c @@ -39,7 +39,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see unsigned old, tmp1, tmp2; \ \ asm volatile ("1:\n\t" \ - "lr.w.aq %[old], %[mem]\n\t" \ + "lr.w.aqrl %[old], %[mem]\n\t" \ #insn " %[tmp1], %[old], %[value]\n\t" \ invert \ "and %[tmp1], %[tmp1], %[mask]\n\t" \ @@ -73,7 +73,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see unsigned old, tmp1; \ \ asm volatile ("1:\n\t" \ - "lr.w.aq %[old], %[mem]\n\t" \ + "lr.w.aqrl %[old], %[mem]\n\t" \ "and %[tmp1], %[old], %[mask]\n\t" \ "bne %[tmp1], %[o], 1f\n\t" \ "and %[tmp1], %[old], %[not_mask]\n\t" \ -- 2.25.1