From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by sourceware.org (Postfix) with ESMTPS id 0B0713858C36 for ; Mon, 10 Apr 2023 18:26:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0B0713858C36 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x644.google.com with SMTP id n14so30495412plc.8 for ; Mon, 10 Apr 2023 11:26:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1681151216; x=1683743216; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lQxELVkbvgDoM2334WlZF1piQ+RAUxqqTmxO3BmB9WQ=; b=F9pi8+TXLrdQY3rL72g3D1Fkvk8KiJ/wJNa6f5Nb48DuIdB/y0ZRbXIihE2jCnJSi/ SYMVKU9bWcL4elhIEwNgKfTBkQ+21Ut823YA9fy37NG9u5jWT7k+krI/VlDaeoi5/tZG dg5dM/tjMnykv+EKizvjtPJRXhiqDAshcgkK6qTvvLaxsyogiFVYzBgx8JMZR20auDmL 4U6EC9ddwgV98N/F959HMofWgMzcY3lcdoT9oLVM+ZPX3c9m9hDpAJm9HqMWjTcoyso2 jd/gQNcDWitkjnseSaetDycdcFkJmhOEhQ2MgXncucgrokB1aV6+PHRJ5HwfGYW5QBUX JrfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681151216; x=1683743216; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lQxELVkbvgDoM2334WlZF1piQ+RAUxqqTmxO3BmB9WQ=; b=XdoG7sQWc0s0AL5XjzIZtHqq38Po6fTKT7qv2abhsTmOs0GPjpEZvGwjrFK+TpNuGv wANocWE77WBsHyM/0+p+v4mugyw5078FxG9kYyBVA6n1OjHLgFpmddV7sIHb6tromvmY lv5lzxOCeDOg9SLa7HEcg/wrr9bBm/Ve8AMqX0SU+0wj3drk9NJFGltY6OsWN4svP0k5 BpuKVsS3n9jSxsFEuMpcllszzM8ZfOngV5RGL6eHmQDVJMX5RQ5Bq0SgAdW6+Sa3PN5l oPGkEQZfx626/VxuHLL3KBDYzk++rW2dTMJ2z55lhRg350C7N2ESDZ/9yROMtvgs31qK AAxw== X-Gm-Message-State: AAQBX9flM00GJtA3uuFoT3D4LWdb8HE4Wf21jaTbxlpsmgVSgCdXvdM4 U7wvy4tijFiA4dhLJTDoqX7QqkqsiARejBpQuGOM5BheKnA= X-Google-Smtp-Source: AKy350Zj7Ve05/lHxU7jPzz6IAquh3Tpd5sqFLfCnqW51NhFsr13p6L1lLVmBxQ7SXUckbTeR8mI+A== X-Received: by 2002:a05:6a20:8b29:b0:db:81b:94be with SMTP id l41-20020a056a208b2900b000db081b94bemr11882432pzh.49.1681151215961; Mon, 10 Apr 2023 11:26:55 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id d2-20020aa78e42000000b00627f054a3cdsm4478977pfr.31.2023.04.10.11.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 11:26:55 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jefferyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill Subject: [PATCH v3 05/10] RISCV: Strengthen atomic stores Date: Mon, 10 Apr 2023 11:23:43 -0700 Message-Id: <20230410182348.2168356-6-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230410182348.2168356-1-patrick@rivosinc.com> References: <20230405210118.1969283-1-patrick@rivosinc.com> <20230410182348.2168356-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This change makes atomic stores strictly stronger than table A.6 of the ISA manual. This mapping makes the overall patchset compatible with table A.7 as well. 2023-04-10 Patrick O'Neill PR target/89835 * sync.md (atomic_store): Use simple store instruction in combination with a fence. * pr89835.c: New test. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Use a trailing fence for atomic stores to be compatible with Table A.7 --- gcc/config/riscv/sync.md | 20 +++++++++++++++++--- gcc/testsuite/gcc.target/riscv/pr89835.c | 9 +++++++++ 2 files changed, 26 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index de42245981b..eef083b06e8 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -53,7 +53,8 @@ ;; Atomic memory operations. -;; Implement atomic stores with amoswap. Fall back to fences for atomic loads. +;; Implement atomic stores with conservative fences. Fall back to fences for atomic loads. +;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. (define_insn "atomic_store" [(set (match_operand:GPR 0 "memory_operand" "=A") (unspec_volatile:GPR @@ -61,9 +62,22 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "TARGET_ATOMIC" - "%F2amoswap.%A2 zero,%z1,%0" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,w\;" + "s\t%z1,%0\;" + "fence\trw,rw"; + if (model == MEMMODEL_RELEASE) + return "fence\trw,w\;" + "s\t%z1,%0"; + else + return "s\t%z1,%0"; + } [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 12))]) (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/pr89835.c new file mode 100644 index 00000000000..ab190e11b60 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr89835.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that relaxed atomic stores use simple store instuctions. */ +/* { dg-final { scan-assembler-not "amoswap" } } */ + +void +foo(int bar, int baz) +{ + __atomic_store_n(&bar, baz, __ATOMIC_RELAXED); +} -- 2.25.1