From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1044.google.com (mail-pj1-x1044.google.com [IPv6:2607:f8b0:4864:20::1044]) by sourceware.org (Postfix) with ESMTPS id 522CF385773E for ; Mon, 10 Apr 2023 18:26:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 522CF385773E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pj1-x1044.google.com with SMTP id 98e67ed59e1d1-246bc3d38cdso164032a91.1 for ; Mon, 10 Apr 2023 11:26:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1681151217; x=1683743217; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lVP8IbDjca+kcx7I3tMp6v3BEP4D8BcaOb2FvUjEaeU=; b=ZqLaW+YOFz/8m0ahdaLhLKTmI4nXrtjC8cf2TkuO7/vLqVVKBIgDfzzDZdnHtrnSbW wr9EFNCnW7dwrltO3I1KPrE/b2rrDv0VGuNf1YQfyc773wQsnJ4QkZsucWj0532sylQD VpTTUY+KYN6d/YlWE69O7zqIkbW6pwjT/SHnOb96Q1FPnZiW3wjbFaCSe4C/ZG4B3C4F JM3s5xDBbQ4soimDhGaOK10Z6HYlWmivi3nA37DD7ahx3eIOd96Sr4QlUy4YJ9NfcwwJ uATyijaSiDlUik/4Za/x3/pmrmXF3AkEJnZe2uXlpRaKjAo8XBSmzsqJ+NO4qPiKCzzu L6cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681151217; x=1683743217; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lVP8IbDjca+kcx7I3tMp6v3BEP4D8BcaOb2FvUjEaeU=; b=A33LKJz8eJq+EfI59QiJfBnhlrvyPEUtuzomJv/lHCE3styi9mO6HEpFalonnL9OsY qVWUGX+JLv2vNcOyjQjcf8Sf9zcwy860nJKAm1Yg4kLPvTfpqawhTahrnmZiXp9q9Fw1 S+4Hp7RBT2Gjyk+NxClnLxIoxc0ZFvMnX75oLPasFFfKC/x7f+G8jD7yW3wwRV2asmch kiX6VNx+APonXkpnXXsZHdRf91eibH72mm5d+kWNnN/IgpGU1yZLRVueIjzuU1ny+fMR j0fAFwdh8RM2u3dx4KGyJ8L9RuO2DuOQyXJCzkTR2rWXEp+tUFOpqa3rgLyojkDUFz+z yJAA== X-Gm-Message-State: AAQBX9eqizKfd6rZDrfuPUcoE/UMdd0QZBKfwVxqhsCT8kf0XesFbkuU LEEAbkqmbvDIZpYnJpaXU29uVjwSyDgCm0lz+ldeCHrWj3w= X-Google-Smtp-Source: AKy350br/h+8J1sCkQUbA1M95CJJSJFJegBpKqGnY7UuJpu/IVf+Fpt2OBsj83Js4LAakt1KIuWk2Q== X-Received: by 2002:aa7:8bc4:0:b0:62d:b210:8c9d with SMTP id s4-20020aa78bc4000000b0062db2108c9dmr13524524pfd.32.1681151217132; Mon, 10 Apr 2023 11:26:57 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id d2-20020aa78e42000000b00627f054a3cdsm4478977pfr.31.2023.04.10.11.26.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 11:26:56 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, jefferyalaw@gmail.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, Patrick O'Neill Subject: [PATCH v3 06/10] RISCV: Eliminate AMO op fences Date: Mon, 10 Apr 2023 11:23:44 -0700 Message-Id: <20230410182348.2168356-7-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230410182348.2168356-1-patrick@rivosinc.com> References: <20230405210118.1969283-1-patrick@rivosinc.com> <20230410182348.2168356-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Atomic operations with the appropriate bits set already enfore release semantics. Remove unnecessary release fences from atomic ops. This change brings AMO ops in line with table A.6 of the ISA manual. 2023-04-10 Patrick O'Neill * riscv.cc (riscv_memmodel_needs_amo_acquire): Change function name. * riscv.cc (riscv_print_operand): Remove unneeded %F case. * sync.md: Remove unneeded fences. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 16 +++++----------- gcc/config/riscv/sync.md | 12 ++++++------ 2 files changed, 11 insertions(+), 17 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8ffee494fbe..6576e9ae524 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4301,11 +4301,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) } } -/* Return true if a FENCE should be emitted to before a memory access to - implement the release portion of memory model MODEL. */ +/* Return true if the .RL suffix should be added to an AMO to implement the + release portion of memory model MODEL. */ static bool -riscv_memmodel_needs_release_fence (enum memmodel model) +riscv_memmodel_needs_amo_release (enum memmodel model) { switch (model) { @@ -4331,7 +4331,6 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. - 'F' Print a FENCE if the memory model requires a release. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -4493,19 +4492,14 @@ riscv_print_operand (FILE *file, rtx op, int letter) case 'A': if (riscv_memmodel_needs_amo_acquire (model) && - riscv_memmodel_needs_release_fence (model)) + riscv_memmodel_needs_amo_release (model)) fputs (".aqrl", file); else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); - else if (riscv_memmodel_needs_release_fence (model)) + else if (riscv_memmodel_needs_amo_release (model)) fputs (".rl", file); break; - case 'F': - if (riscv_memmodel_needs_release_fence (model)) - fputs ("fence iorw,ow; ", file); - break; - case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index eef083b06e8..fdfc56d64a1 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -87,9 +87,9 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F2amo.%A2 zero,%z1,%0" + "amo.%A2\tzero,%z1,%0" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -101,9 +101,9 @@ (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F3amo.%A3 %0,%z2,%1" + "amo.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -114,9 +114,9 @@ (set (match_dup 1) (match_operand:GPR 2 "register_operand" "0"))] "TARGET_ATOMIC" - "%F3amoswap.%A3 %0,%z2,%1" + "amoswap.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_cas_value_strong" [(set (match_operand:GPR 0 "register_operand" "=&r") -- 2.25.1