From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 75F773858D33 for ; Fri, 14 Apr 2023 02:45:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 75F773858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681440355; x=1712976355; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2eXrbijpfAq2+S2xXdsnCwSWsfGTZ9RtOwNcDyFHqxk=; b=mfr4c/S+5JHP+4idS5G/HGlyJyHhwT1BaNrU4lAGBkMYc0o55ctvdl9y a8S72P2vpwmIELZtnu9YmrihhR6JIsztutUUhYUmaTIY2MOjowRHCgRRn ZO0F2864T8o6j8JOzHh13PDHEN4GNd2qhz0QuH/9XEM/QPFymtErTAuTn bI8vvm1Zx/n0ScUPc7dVT48hLFcstxC9g617y9siBviopfGMzXvFUGjQD 07CUzntxEmCkUiJ0dByN8Nr/pgEGzn6/DA8mFt5XtPIdoYZNsSskLTdxG l0AMv+NE0q1DhFswZ/wI9TyT547zQ9IOQJGYuiQIteHb9nBPPh9hf9dTY A==; X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="430661665" X-IronPort-AV: E=Sophos;i="5.99,195,1677571200"; d="scan'208";a="430661665" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2023 19:45:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10679"; a="935847785" X-IronPort-AV: E=Sophos;i="5.99,195,1677571200"; d="scan'208";a="935847785" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga006.fm.intel.com with ESMTP; 13 Apr 2023 19:45:32 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.46.88]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 8C3651007EBE; Fri, 14 Apr 2023 10:45:31 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, yanzhang.wang@intel.com, pan2.li@intel.com Subject: [PATCH v2] RISC-V: Add test cases for the RVV mask insn shortcut. Date: Fri, 14 Apr 2023 10:45:29 +0800 Message-Id: <20230414024529.2930664-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230414023238.2921142-1-pan2.li@intel.com> References: <20230414023238.2921142-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li There are sorts of shortcut codegen for the RVV mask insn. For example. vmxor vd, va, va => vmclr vd. We would like to add more optimization like this but first of all we must add the tests for the existing shortcut optimization, to ensure we don't break existing optimization from underlying shortcut optimization. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/mask_insn_shortcut.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/base/mask_insn_shortcut.c | 239 ++++++++++++++++++ 1 file changed, 239 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c new file mode 100644 index 00000000000..efc3af39fc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c @@ -0,0 +1,239 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ + +#include "riscv_vector.h" + +vbool1_t test_shortcut_for_riscv_vmand_case_0(vbool1_t v1, size_t vl) { + return __riscv_vmand_mm_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmand_case_1(vbool2_t v1, size_t vl) { + return __riscv_vmand_mm_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmand_case_2(vbool4_t v1, size_t vl) { + return __riscv_vmand_mm_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmand_case_3(vbool8_t v1, size_t vl) { + return __riscv_vmand_mm_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmand_case_4(vbool16_t v1, size_t vl) { + return __riscv_vmand_mm_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmand_case_5(vbool32_t v1, size_t vl) { + return __riscv_vmand_mm_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmand_case_6(vbool64_t v1, size_t vl) { + return __riscv_vmand_mm_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmnand_case_0(vbool1_t v1, size_t vl) { + return __riscv_vmnand_mm_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmnand_case_1(vbool2_t v1, size_t vl) { + return __riscv_vmnand_mm_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmnand_case_2(vbool4_t v1, size_t vl) { + return __riscv_vmnand_mm_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmnand_case_3(vbool8_t v1, size_t vl) { + return __riscv_vmnand_mm_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmnand_case_4(vbool16_t v1, size_t vl) { + return __riscv_vmnand_mm_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmnand_case_5(vbool32_t v1, size_t vl) { + return __riscv_vmnand_mm_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmnand_case_6(vbool64_t v1, size_t vl) { + return __riscv_vmnand_mm_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmandn_case_0(vbool1_t v1, size_t vl) { + return __riscv_vmandn_mm_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmandn_case_1(vbool2_t v1, size_t vl) { + return __riscv_vmandn_mm_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmandn_case_2(vbool4_t v1, size_t vl) { + return __riscv_vmandn_mm_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmandn_case_3(vbool8_t v1, size_t vl) { + return __riscv_vmandn_mm_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmandn_case_4(vbool16_t v1, size_t vl) { + return __riscv_vmandn_mm_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmandn_case_5(vbool32_t v1, size_t vl) { + return __riscv_vmandn_mm_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmandn_case_6(vbool64_t v1, size_t vl) { + return __riscv_vmandn_mm_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmxor_case_0(vbool1_t v1, size_t vl) { + return __riscv_vmxor_mm_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmxor_case_1(vbool2_t v1, size_t vl) { + return __riscv_vmxor_mm_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmxor_case_2(vbool4_t v1, size_t vl) { + return __riscv_vmxor_mm_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmxor_case_3(vbool8_t v1, size_t vl) { + return __riscv_vmxor_mm_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmxor_case_4(vbool16_t v1, size_t vl) { + return __riscv_vmxor_mm_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmxor_case_5(vbool32_t v1, size_t vl) { + return __riscv_vmxor_mm_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmxor_case_6(vbool64_t v1, size_t vl) { + return __riscv_vmxor_mm_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmor_case_0(vbool1_t v1, size_t vl) { + return __riscv_vmor_mm_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmor_case_1(vbool2_t v1, size_t vl) { + return __riscv_vmor_mm_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmor_case_2(vbool4_t v1, size_t vl) { + return __riscv_vmor_mm_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmor_case_3(vbool8_t v1, size_t vl) { + return __riscv_vmor_mm_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmor_case_4(vbool16_t v1, size_t vl) { + return __riscv_vmor_mm_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmor_case_5(vbool32_t v1, size_t vl) { + return __riscv_vmor_mm_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmor_case_6(vbool64_t v1, size_t vl) { + return __riscv_vmor_mm_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmnor_case_0(vbool1_t v1, size_t vl) { + return __riscv_vmnor_mm_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmnor_case_1(vbool2_t v1, size_t vl) { + return __riscv_vmnor_mm_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmnor_case_2(vbool4_t v1, size_t vl) { + return __riscv_vmnor_mm_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmnor_case_3(vbool8_t v1, size_t vl) { + return __riscv_vmnor_mm_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmnor_case_4(vbool16_t v1, size_t vl) { + return __riscv_vmnor_mm_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmnor_case_5(vbool32_t v1, size_t vl) { + return __riscv_vmnor_mm_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmnor_case_6(vbool64_t v1, size_t vl) { + return __riscv_vmnor_mm_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmorn_case_0(vbool1_t v1, size_t vl) { + return __riscv_vmorn_mm_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmorn_case_1(vbool2_t v1, size_t vl) { + return __riscv_vmorn_mm_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmorn_case_2(vbool4_t v1, size_t vl) { + return __riscv_vmorn_mm_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmorn_case_3(vbool8_t v1, size_t vl) { + return __riscv_vmorn_mm_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmorn_case_4(vbool16_t v1, size_t vl) { + return __riscv_vmorn_mm_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t vl) { + return __riscv_vmorn_mm_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmorn_case_6(vbool64_t v1, size_t vl) { + return __riscv_vmorn_mm_b64(v1, v1, vl); +} + +vbool1_t test_shortcut_for_riscv_vmxnor_case_0(vbool1_t v1, size_t vl) { + return __riscv_vmxnor_mm_b1(v1, v1, vl); +} + +vbool2_t test_shortcut_for_riscv_vmxnor_case_1(vbool2_t v1, size_t vl) { + return __riscv_vmxnor_mm_b2(v1, v1, vl); +} + +vbool4_t test_shortcut_for_riscv_vmxnor_case_2(vbool4_t v1, size_t vl) { + return __riscv_vmxnor_mm_b4(v1, v1, vl); +} + +vbool8_t test_shortcut_for_riscv_vmxnor_case_3(vbool8_t v1, size_t vl) { + return __riscv_vmxnor_mm_b8(v1, v1, vl); +} + +vbool16_t test_shortcut_for_riscv_vmxnor_case_4(vbool16_t v1, size_t vl) { + return __riscv_vmxnor_mm_b16(v1, v1, vl); +} + +vbool32_t test_shortcut_for_riscv_vmxnor_case_5(vbool32_t v1, size_t vl) { + return __riscv_vmxnor_mm_b32(v1, v1, vl); +} + +vbool64_t test_shortcut_for_riscv_vmxnor_case_6(vbool64_t v1, size_t vl) { + return __riscv_vmxnor_mm_b64(v1, v1, vl); +} + +/* { dg-final { scan-assembler-not {vmand\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ +/* { dg-final { scan-assembler-not {vmnand\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ +/* { dg-final { scan-assembler-not {vmnandn\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ +/* { dg-final { scan-assembler-not {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ +/* { dg-final { scan-assembler-not {vmor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ +/* { dg-final { scan-assembler-not {vmnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ +/* { dg-final { scan-assembler-times {vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */ +/* { dg-final { scan-assembler-not {vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ +/* { dg-final { scan-assembler-times {vmclr\.m\s+v[0-9]+} 14 } } */ +/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 7 } } */ -- 2.34.1