From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) by sourceware.org (Postfix) with ESMTPS id 683E23857725 for ; Fri, 14 Apr 2023 17:10:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 683E23857725 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pf1-x444.google.com with SMTP id d2e1a72fcca58-63b509fe13eso394180b3a.1 for ; Fri, 14 Apr 2023 10:10:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681492259; x=1684084259; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BzJUGSPwlCIgt2aYZP1O/yLAc0Yej9dL5/alw4ulUDI=; b=HHcCqJygyYkA0onjiYNIpxX9W3zd2lHmfrverk8Iv624f+J2/+If9PJmn+WFNHgsm0 NMPE/F8X6kBfE4Snoh9Wntaq0VPRB3dJ0eu4/uVrHo/vJWDleeUSSHNVCykVuq4emAFk NBF9WxEijkqcoP/qGYLI2p4Rldp0NWuNPlmvajvAlg9WcK/R+cYLMeTsRjVIB9BwfEvD wOWWudDJQetGc6tdQMJzUHRgJIt6FyMoeabsKaVF1ruwkOKh3fgj9dfm++xIuYTlZ0jg 8a0h+c17bgjv2VypFkLUNX0X2YaWwJzGONePC92OaFC8JP3GSE4sSNVHNklm9Q+BMBE2 9GAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681492259; x=1684084259; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BzJUGSPwlCIgt2aYZP1O/yLAc0Yej9dL5/alw4ulUDI=; b=WzqnE08/3vfWRWRZOTAqF5+3GSE+HKHrT7053lOdI0kSnJPTpGT6cgCi8fnrmAUN+a erD9eL5yHu3EAEHC9SUKObyvuOJ2Et5q2nd+k1lVq0GHNmOlMbpZCID0QzHxxDxzcOmc /C62tt0sccgMyxhv0mEolM/daROVw4VeykF3lPeg7YQeLJPfwVDKLPZ9voiKDi5xsLRt AMDnMKW+R6Gz0zn3qijs0wWb6gusPZaV0gGur4YuqHovUgg/w/b/D/vX/nMf8is9umOI Is65sG1VmrghbNUnNIOBBgaZ2GcKZjiQ6p75iB0aWalVv8LGAwEF0qUFxaIc/WXIT+Oo rhOw== X-Gm-Message-State: AAQBX9fSmnVKIwe/+PMemUYGMCM32EmvnMOQ0phnHuJk3VND7a0g0d7n O6ABZBArF1Ygqn31pfG2ivd/aJPzd7mLP/V3zaMvfYA1Fuo= X-Google-Smtp-Source: AKy350ZQn4MGSXz1TivcCBSU+kZV/SjwQvaYq260WcL8/7TdhDCSvczaLrPPPyPVUcLMHptt6UMJqg== X-Received: by 2002:a05:6a00:88e:b0:626:2ae6:31f6 with SMTP id q14-20020a056a00088e00b006262ae631f6mr9972846pfj.7.1681492258901; Fri, 14 Apr 2023 10:10:58 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id 12-20020aa7924c000000b006258dd63a3fsm3271902pfp.56.2023.04.14.10.10.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 10:10:57 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v4 09/10] RISCV: Weaken atomic loads Date: Fri, 14 Apr 2023 10:09:41 -0700 Message-Id: <20230414170942.1695672-10-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414170942.1695672-1-patrick@rivosinc.com> References: <20230410182348.2168356-1-patrick@rivosinc.com> <20230414170942.1695672-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This change brings atomic loads in line with table A.6 of the ISA manual. 2023-04-14 Patrick O'Neill * sync.md (atomic_load): Implement atomic load mapping. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Add this patch --- gcc/config/riscv/sync.md | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index e91fa29da51..9e3685f5b1c 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -23,6 +23,7 @@ UNSPEC_COMPARE_AND_SWAP UNSPEC_SYNC_OLD_OP UNSPEC_SYNC_EXCHANGE + UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER ]) @@ -63,7 +64,31 @@ ;; Atomic memory operations. -;; Implement atomic stores with conservative fences. Fall back to fences for atomic loads. +(define_insn "atomic_load" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "TARGET_ATOMIC" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw\;" + "l\t%0,%1\;" + "fence\tr,rw"; + if (model == MEMMODEL_ACQUIRE) + return "l\t%0,%1\;" + "fence\tr,rw"; + else + return "l\t%0,%1"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 12))]) + +;; Implement atomic stores with conservative fences. ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. (define_insn "atomic_store" [(set (match_operand:GPR 0 "memory_operand" "=A") -- 2.25.1