From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x543.google.com (mail-pg1-x543.google.com [IPv6:2607:f8b0:4864:20::543]) by sourceware.org (Postfix) with ESMTPS id F34F0385734C for ; Fri, 14 Apr 2023 17:11:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F34F0385734C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pg1-x543.google.com with SMTP id 41be03b00d2f7-51b0f9d7d70so1182336a12.1 for ; Fri, 14 Apr 2023 10:11:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681492262; x=1684084262; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n3LzP7XpzoD4Lg+4GYg/HvBpgnedaRrZEWNS7IaNLvA=; b=y2A1FFq2Upntzzj2eGqVcaazVgUi4V2OfgoEc4sE5lrsbwXFeEIvEII8ZSsedjzwmD 1dpOLYkXf6U8DUDwFd+cQTBgFYTUiCsdumbabXQSAsC3N8S8kPoihUmF3RUeXhNaFZFT itrXJUi8nX+uniDvfJxww09wXlrw69n6B95B4I+ILk4/RRuXC31lzJddlH1BHTlc2gNn IduDKZ5gczxD/l9PZgqtEiQGIxSHx9WKvr/M/rAI+D0VKKDXL3phP185gSb/qwYPdz35 W6n/7i7blapGZKfTmciCsz2KU2ndRpNxOB3jLIC/kRA3JXMNfNa42hyzFHnBKLELYQ5t PpUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681492262; x=1684084262; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n3LzP7XpzoD4Lg+4GYg/HvBpgnedaRrZEWNS7IaNLvA=; b=I1Sm5otFHH8nuTFFgMiZNp5rY4siulbqQ3anfTnKRiQqDKH+vIUyKTqscwBjQPB+H7 xrmfDKGc21FDB5pIVT7Ek79I0up98h11Pi2ZuivpU4aHCakiysu0h5HwI+Pu5ausEbbi iY5tu2DLaViM+Uw6OrMDlHOvAWrmCpFow7J3NecthUJehgdtC7lOHS+zfRP43TGwnD5d y1Il+fK83Nir3Sx2UsXhNJuwoydg0zM5qI0klHysuNKl3STApvGiaOlDJox/cxSnmA0p wfeiCGl57QYk29WuCJ/AKrSu9SLCoa3j67pFUbz5DP94P+vPks7DtsMyijH06iYiTzfr rN4g== X-Gm-Message-State: AAQBX9fZ3dKVyiGPhbeopRVZPo7LbaA+IheU1sT7cN2utOO0VPUDBa52 YT8tTTb6Fwuq0uqDK2hFMIkSSwkq+8z63oFS4h/RMbsucpE= X-Google-Smtp-Source: AKy350Zi4WufulTVdKX1HuwCjiOs8TUWH5IBqb5ney/DYgv+zSf28KzHE9vbiQDlb+BSZLi9HAFDlQ== X-Received: by 2002:a05:6a00:1a43:b0:5a8:b2bf:26ac with SMTP id h3-20020a056a001a4300b005a8b2bf26acmr9346857pfv.20.1681492261185; Fri, 14 Apr 2023 10:11:01 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id 12-20020aa7924c000000b006258dd63a3fsm3271902pfp.56.2023.04.14.10.10.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 10:10:59 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v4 10/10] RISCV: Table A.6 conformance tests Date: Fri, 14 Apr 2023 10:09:42 -0700 Message-Id: <20230414170942.1695672-11-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414170942.1695672-1-patrick@rivosinc.com> References: <20230410182348.2168356-1-patrick@rivosinc.com> <20230414170942.1695672-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: These tests cover basic cases to ensure the atomic mappings follow the strengthened Table A.6 mappings that are compatible with Table A.7. 2023-04-14 Patrick O'Neill * amo-table-a-6-amo-add-1.c: New test. * amo-table-a-6-amo-add-2.c: Likewise. * amo-table-a-6-amo-add-3.c: Likewise. * amo-table-a-6-amo-add-4.c: Likewise. * amo-table-a-6-amo-add-5.c: Likewise. * amo-table-a-6-compare-exchange-1.c: Likewise. * amo-table-a-6-compare-exchange-2.c: Likewise. * amo-table-a-6-compare-exchange-3.c: Likewise. * amo-table-a-6-compare-exchange-4.c: Likewise. * amo-table-a-6-compare-exchange-5.c: Likewise. * amo-table-a-6-compare-exchange-6.c: Likewise. * amo-table-a-6-compare-exchange-7.c: Likewise. * amo-table-a-6-fence-1.c: Likewise. * amo-table-a-6-fence-2.c: Likewise. * amo-table-a-6-fence-3.c: Likewise. * amo-table-a-6-fence-4.c: Likewise. * amo-table-a-6-fence-5.c: Likewise. * amo-table-a-6-load-1.c: Likewise. * amo-table-a-6-load-2.c: Likewise. * amo-table-a-6-load-3.c: Likewise. * amo-table-a-6-store-1.c: Likewise. * amo-table-a-6-store-2.c: Likewise. * amo-table-a-6-store-compat-3.c: Likewise. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Consolidate existing tests in this patch * Add new tests for store/load/amoadd --- v4 Changelog: * Add additional compare-exchange testcases * Update assertions to use scan-assembler-times for fences --- .../gcc.target/riscv/amo-table-a-6-amo-add-1.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-2.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-3.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-4.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-5.c | 8 ++++++++ .../riscv/amo-table-a-6-compare-exchange-1.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-2.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-3.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-4.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-5.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-6.c | 11 +++++++++++ .../riscv/amo-table-a-6-compare-exchange-7.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-1.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-fence-2.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-3.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-4.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-5.c | 10 ++++++++++ gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c | 9 +++++++++ gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c | 11 +++++++++++ .../gcc.target/riscv/amo-table-a-6-store-1.c | 9 +++++++++ .../gcc.target/riscv/amo-table-a-6-store-2.c | 11 +++++++++++ .../gcc.target/riscv/amo-table-a-6-store-compat-3.c | 11 +++++++++++ 23 files changed, 221 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c new file mode 100644 index 00000000000..ae7e407befc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c new file mode 100644 index 00000000000..60d84f32481 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aq\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c new file mode 100644 index 00000000000..a97231e4e73 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.rl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c new file mode 100644 index 00000000000..3c843afdd5f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c new file mode 100644 index 00000000000..3434229f5e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c new file mode 100644 index 00000000000..a9141cde48f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c new file mode 100644 index 00000000000..b1ebb20e2f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_CONSUME, __ATOMIC_CONSUME); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c new file mode 100644 index 00000000000..47d8d02f7e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c new file mode 100644 index 00000000000..af6e1d69c75 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c new file mode 100644 index 00000000000..ceb5660b6af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c new file mode 100644 index 00000000000..7b012fb1288 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* Mixed mappings need to be unioned. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c new file mode 100644 index 00000000000..5adec6f7a19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c new file mode 100644 index 00000000000..b8c28013ef3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c new file mode 100644 index 00000000000..117f9036e39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c new file mode 100644 index 00000000000..4b6dd7a9aa7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c new file mode 100644 index 00000000000..d40d3bc37db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence.tso" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c new file mode 100644 index 00000000000..71f76c27789 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c new file mode 100644 index 00000000000..8278198072e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that load mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c new file mode 100644 index 00000000000..84b6cc542ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that load mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c new file mode 100644 index 00000000000..3f15041d117 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that load mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */ +/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c new file mode 100644 index 00000000000..c200bd1d11d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that store mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c new file mode 100644 index 00000000000..1cf366b5986 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that store mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c new file mode 100644 index 00000000000..288e1493156 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that store mapping are compatible with Table A.6 & A.7. */ +/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */ +/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_SEQ_CST); +} -- 2.25.1