From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) by sourceware.org (Postfix) with ESMTPS id 7A8CC3857714 for ; Fri, 14 Apr 2023 17:10:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7A8CC3857714 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pf1-x444.google.com with SMTP id d2e1a72fcca58-63b509fe13eso394155b3a.1 for ; Fri, 14 Apr 2023 10:10:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681492251; x=1684084251; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P9Da4sGTXFtl1RlbfN0nZAdSV4+gLUU/Cs6PMOmhG0U=; b=ESyUr4qRhrasq7sZM94NoaRcciMo8ezfN9PVUBbWWWkPgvjm7U21R6en4ROIupCmDx dMKxVG8YuRfXjJKQnrfqms6kvcu25BebVONO4phHHpsL8VWVNDjAyPsXlx5XMYcf8uG5 v1HZvqfkJUDszIZ/L9/z7kDTa15YZL+xDQZu+2iCwO0IR8ZnLSgfwvqid/gjx/BwtxzQ J2NDcIPiUV77fHkIEbGdqZ7/K2SnFxkScyfRzI6a6XTrSRSvmiTbeI4QYzAcfGu5D8Ac ACme02Br013VqzbLjZJ9WTgEl8BQ21aHMMREsJhIF1jbXZXpHoD7ryarrmCNs2PnoxZM fvPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681492251; x=1684084251; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P9Da4sGTXFtl1RlbfN0nZAdSV4+gLUU/Cs6PMOmhG0U=; b=PVgugEL/E8hg5JzYqbURFoFy4hpocWI+bWYolZ08k4M3lgmZis2bFFLn5l6ksfbQ4K KPpo9vQ0vikviWn1vKXoOPC9tueTlSwIJJQe/rhO8dBn2dGdFHv0VtzITrAPhPOzk/FQ 1Ye36ta/xkii6ZeMTcQ6u7YtmVrl14Vuya/Aobvwa5qMY8QY0lfss7oja5VpRQsN1C7X gLHG1E06/ZFRwlWYngEcWn6zUZAu3+dKDSMdAGbM/X9QSkN9i6s2slz04M0jdF7MpOvM RigFUtjRUbNwe3kfTkdc8IsdW9KjOm/Mlo7otSzUKjvpi09alhMl2YrTXI2/rxSLG8M+ BjvQ== X-Gm-Message-State: AAQBX9cEkYRJ6jQyz0LvFHupkO0R5VVtuJj90/L6O/JkSg/kCm9yML5E jspMKKRbElHu69DsW63jAW3aQRWbZdoWnU1+uqx3yvWFYvY= X-Google-Smtp-Source: AKy350bxRZjd3Tq8JOra1ClC2DM3Jk7jjpjI5jxZ8mLtTIg85IXId5WiEoCV0NRrlm9M72zAdFG40Q== X-Received: by 2002:a05:6a00:1a12:b0:63b:5c82:e21a with SMTP id g18-20020a056a001a1200b0063b5c82e21amr6403399pfv.1.1681492251324; Fri, 14 Apr 2023 10:10:51 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id 12-20020aa7924c000000b006258dd63a3fsm3271902pfp.56.2023.04.14.10.10.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 10:10:50 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v4 06/10] RISCV: Eliminate AMO op fences Date: Fri, 14 Apr 2023 10:09:38 -0700 Message-Id: <20230414170942.1695672-7-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414170942.1695672-1-patrick@rivosinc.com> References: <20230410182348.2168356-1-patrick@rivosinc.com> <20230414170942.1695672-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Atomic operations with the appropriate bits set already enfore release semantics. Remove unnecessary release fences from atomic ops. This change brings AMO ops in line with table A.6 of the ISA manual. 2023-04-14 Patrick O'Neill * riscv.cc (riscv_memmodel_needs_amo_acquire): Change function name. * riscv.cc (riscv_print_operand): Remove unneeded %F case. * sync.md: Remove unneeded fences. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 16 +++++----------- gcc/config/riscv/sync.md | 12 ++++++------ 2 files changed, 11 insertions(+), 17 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 088b8d25773..70031b83391 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4301,11 +4301,11 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model) } } -/* Return true if a FENCE should be emitted to before a memory access to - implement the release portion of memory model MODEL. */ +/* Return true if the .RL suffix should be added to an AMO to implement the + release portion of memory model MODEL. */ static bool -riscv_memmodel_needs_release_fence (enum memmodel model) +riscv_memmodel_needs_amo_release (enum memmodel model) { switch (model) { @@ -4331,7 +4331,6 @@ riscv_memmodel_needs_release_fence (enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. - 'F' Print a FENCE if the memory model requires a release. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -4493,19 +4492,14 @@ riscv_print_operand (FILE *file, rtx op, int letter) case 'A': if (riscv_memmodel_needs_amo_acquire (model) && - riscv_memmodel_needs_release_fence (model)) + riscv_memmodel_needs_amo_release (model)) fputs (".aqrl", file); else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); - else if (riscv_memmodel_needs_release_fence (model)) + else if (riscv_memmodel_needs_amo_release (model)) fputs (".rl", file); break; - case 'F': - if (riscv_memmodel_needs_release_fence (model)) - fputs ("fence iorw,ow; ", file); - break; - case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index eef083b06e8..fdfc56d64a1 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -87,9 +87,9 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F2amo.%A2 zero,%z1,%0" + "amo.%A2\tzero,%z1,%0" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -101,9 +101,9 @@ (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F3amo.%A3 %0,%z2,%1" + "amo.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -114,9 +114,9 @@ (set (match_dup 1) (match_operand:GPR 2 "register_operand" "0"))] "TARGET_ATOMIC" - "%F3amoswap.%A3 %0,%z2,%1" + "amoswap.%A3\t%0,%z2,%1" [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 4))]) (define_insn "atomic_cas_value_strong" [(set (match_operand:GPR 0 "register_operand" "=&r") -- 2.25.1