From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) by sourceware.org (Postfix) with ESMTPS id 4326A3857350 for ; Fri, 14 Apr 2023 17:10:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4326A3857350 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pg1-x542.google.com with SMTP id 41be03b00d2f7-517bb01bac9so737849a12.0 for ; Fri, 14 Apr 2023 10:10:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681492256; x=1684084256; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VQ7bZtpi2cp1uLeZu12OoYkmqoLLJkZVj1Ye9cT2adU=; b=L4V1ZdyD79VT8Aixtu24KMduJ3RGVRWkvQT/e368vCYOrNv8BvWM4GfJ7R1yeYel9h lFFR8BmX+Z86MtLw7hsnxJobpefDLdbzIS7AouCmcUQgjFHBO0cNJPDTxbEWBg1xw9af AFIciXwcpbYc1yseRYzafte6ff43wAiMOpXLNqaXBYrNwn1ZQ8fgYeEXnb1weSVhga0i YTmlITNRDHwShu56VsiR5HLPkpkQaK4TlMjV1fssEBg7wW0fdO4RzBqMSt0+/1CyKsWy T3qnPqXzVHIiLmy2ArzOO7Dc/UqpMkPjLVhW635mU0CnQKxmgiuZ6rkpBtKDf7hOWOLk tC+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681492256; x=1684084256; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VQ7bZtpi2cp1uLeZu12OoYkmqoLLJkZVj1Ye9cT2adU=; b=AbmiLoGoC0zioCE+9dqK2PMkhiPo1/6kskd9Nhg4qVv1CKp/rP/vBKJrWbGpr6HMoI IZhfGWexwkI/iTVw0EVEfOVs8WVm5lQC1oKWQkp9QYFGdCMN0h3q+n7z3LP2I09PTnqu 10T89wfXPNdp9r3DMwEuJbDjmdUIp6WD8xsqUow7Lq6MX2mWY5y1K4/rlxGNnlc4E2Nm M761mx3D06x0VgqHY8ph/wvp5Hd3/EJOY2WE1A8BA+/9QT3g5pE399zTZ1m5Pq1nUAYN LiDGAKwmmwQj7ooR6GH0FWgE2LuTIyDUSzk4yxjb5VIIMwXu4QXX/InB3mwGmzZUAFbK 2HgA== X-Gm-Message-State: AAQBX9c1Asb2IIYZ28SqBE8ABY+ZDdJJbuY5CQkoJQteVCLWQWApa2ce ylp6APVpSNGKVfPBv67wlNSKR96zNw1bk+tebRNcTDNNCY8= X-Google-Smtp-Source: AKy350bQehNTkx71kKyTxP9PQm9ZNXCCNFe5czUp/HjVyq9oH0Kwfi3YCyvwBeeOnlrjmBNSGTjoDQ== X-Received: by 2002:a05:6a00:1250:b0:627:e342:7f0e with SMTP id u16-20020a056a00125000b00627e3427f0emr8908457pfi.30.1681492256039; Fri, 14 Apr 2023 10:10:56 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id 12-20020aa7924c000000b006258dd63a3fsm3271902pfp.56.2023.04.14.10.10.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 10:10:54 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v4 08/10] RISCV: Weaken mem_thread_fence Date: Fri, 14 Apr 2023 10:09:40 -0700 Message-Id: <20230414170942.1695672-9-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414170942.1695672-1-patrick@rivosinc.com> References: <20230410182348.2168356-1-patrick@rivosinc.com> <20230414170942.1695672-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This change brings atomic fences in line with table A.6 of the ISA manual. Relax mem_thread_fence according to the memmodel given. 2023-04-14 Patrick O'Neill * sync.md (mem_thread_fence_1): Change fence depending on the given memory model. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Consolidate tests in [PATCH v3 10/10] * Remove helper functions --- gcc/config/riscv/sync.md | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index a31b8c4f28a..e91fa29da51 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -42,14 +42,24 @@ DONE; }) -;; Until the RISC-V memory model (hence its mapping from C++) is finalized, -;; conservatively emit a full FENCE. (define_insn "mem_thread_fence_1" [(set (match_operand:BLK 0 "" "") (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (match_operand:SI 1 "const_int_operand" "")] ;; model "" - "fence\tiorw,iorw") + { + enum memmodel model = (enum memmodel) INTVAL (operands[1]); + model = memmodel_base (model); + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw"; + else if (model == MEMMODEL_ACQ_REL) + return "fence.tso"; + else if (model == MEMMODEL_ACQUIRE) + return "fence\tr,rw"; + else if (model == MEMMODEL_RELEASE) + return "fence\trw,w"; + } + [(set (attr "length") (const_int 4))]) ;; Atomic memory operations. -- 2.25.1