From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id 51A413858CDB for ; Mon, 17 Apr 2023 06:18:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 51A413858CDB Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp75t1681712277tfuhmgrx Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 17 Apr 2023 14:17:56 +0800 (CST) X-QQ-SSF: 01400000000000F0P000000A0000000 X-QQ-FEAT: +ujAKkuGAaWW37Y83RQ2tGYxgcUFCzp6WaqwY+NDl0bf+gmASfIv7v0YM3tck AYru8TatV7NFnxIzoPtbQeXLtSYBJG6kjDF268WjxWft/GFCA4ixIiyGbwoqkVkUw+S+mWM M/l92O114s8F982ELD/0IIjUUsG2tij+kgbHO7K7m//I61s/p3BbY2AmxR5IyZL7GWvkSI8 CeS5F+5jL9zRGtiZB3Cb5YFKgy1j45zWaAc55twqVCAt/Eha62fOCLh6TarwgEj3LEx+pVv pJa8t/SDHG2WWRcKKQMp6kaUjwbqcu6A1dxsoBLmwFK+juUCopgIHSC8a3gU4AT3bS1NQ2G BQGiLDXD4gcjVzomEWYhvWeGjlmsS0L4PA5UpZJ68BHPMRxjUTZ8rcW6nVUdA== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 10857695677759116191 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Add tuple type builtins for segment intrinsics Date: Mon, 17 Apr 2023 14:17:54 +0800 Message-Id: <20230417061754.1879-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Juzhe-Zhong Add tuple types for segment intrinsics: https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/198 gcc/ChangeLog: * config/riscv/riscv-modes.def (RVV_TUPLE_MODES): New macro define. (RVV_TUPLE_PARTIAL_MODES): Ditto. * config/riscv/riscv-protos.h (riscv_v_ext_tuple_mode_p): New function. (get_nf): Ditto. (get_subpart_mode): Ditto. (get_tuple_mode): Ditto. * config/riscv/riscv-v.cc (ENTRY): Add tuple modes. (TUPLE_ENTRY): Ditto. (get_nf): Ditto. (get_subpart_mode): Ditto. (get_tuple_mode): Ditto. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_TUPLE_TYPE): New macro define. (register_tuple_type): Ditto. * config/riscv/riscv-vector-builtins.def (DEF_RVV_TUPLE_TYPE): Ditto. (vint8mf8x2_t): Ditto. (vuint8mf8x2_t): Ditto. (vint8mf8x3_t): Ditto. (vuint8mf8x3_t): Ditto. (vint8mf8x4_t): Ditto. (vuint8mf8x4_t): Ditto. (vint8mf8x5_t): Ditto. (vuint8mf8x5_t): Ditto. (vint8mf8x6_t): Ditto. (vuint8mf8x6_t): Ditto. (vint8mf8x7_t): Ditto. (vuint8mf8x7_t): Ditto. (vint8mf8x8_t): Ditto. (vuint8mf8x8_t): Ditto. (vint8mf4x2_t): Ditto. (vuint8mf4x2_t): Ditto. (vint8mf4x3_t): Ditto. (vuint8mf4x3_t): Ditto. (vint8mf4x4_t): Ditto. (vuint8mf4x4_t): Ditto. (vint8mf4x5_t): Ditto. (vuint8mf4x5_t): Ditto. (vint8mf4x6_t): Ditto. (vuint8mf4x6_t): Ditto. (vint8mf4x7_t): Ditto. (vuint8mf4x7_t): Ditto. (vint8mf4x8_t): Ditto. (vuint8mf4x8_t): Ditto. (vint8mf2x2_t): Ditto. (vuint8mf2x2_t): Ditto. (vint8mf2x3_t): Ditto. (vuint8mf2x3_t): Ditto. (vint8mf2x4_t): Ditto. (vuint8mf2x4_t): Ditto. (vint8mf2x5_t): Ditto. (vuint8mf2x5_t): Ditto. (vint8mf2x6_t): Ditto. (vuint8mf2x6_t): Ditto. (vint8mf2x7_t): Ditto. (vuint8mf2x7_t): Ditto. (vint8mf2x8_t): Ditto. (vuint8mf2x8_t): Ditto. (vint8m1x2_t): Ditto. (vuint8m1x2_t): Ditto. (vint8m1x3_t): Ditto. (vuint8m1x3_t): Ditto. (vint8m1x4_t): Ditto. (vuint8m1x4_t): Ditto. (vint8m1x5_t): Ditto. (vuint8m1x5_t): Ditto. (vint8m1x6_t): Ditto. (vuint8m1x6_t): Ditto. (vint8m1x7_t): Ditto. (vuint8m1x7_t): Ditto. (vint8m1x8_t): Ditto. (vuint8m1x8_t): Ditto. (vint8m2x2_t): Ditto. (vuint8m2x2_t): Ditto. (vint8m2x3_t): Ditto. (vuint8m2x3_t): Ditto. (vint8m2x4_t): Ditto. (vuint8m2x4_t): Ditto. (vint8m4x2_t): Ditto. (vuint8m4x2_t): Ditto. (vint16mf4x2_t): Ditto. (vuint16mf4x2_t): Ditto. (vint16mf4x3_t): Ditto. (vuint16mf4x3_t): Ditto. (vint16mf4x4_t): Ditto. (vuint16mf4x4_t): Ditto. (vint16mf4x5_t): Ditto. (vuint16mf4x5_t): Ditto. (vint16mf4x6_t): Ditto. (vuint16mf4x6_t): Ditto. (vint16mf4x7_t): Ditto. (vuint16mf4x7_t): Ditto. (vint16mf4x8_t): Ditto. (vuint16mf4x8_t): Ditto. (vint16mf2x2_t): Ditto. (vuint16mf2x2_t): Ditto. (vint16mf2x3_t): Ditto. (vuint16mf2x3_t): Ditto. (vint16mf2x4_t): Ditto. (vuint16mf2x4_t): Ditto. (vint16mf2x5_t): Ditto. (vuint16mf2x5_t): Ditto. (vint16mf2x6_t): Ditto. (vuint16mf2x6_t): Ditto. (vint16mf2x7_t): Ditto. (vuint16mf2x7_t): Ditto. (vint16mf2x8_t): Ditto. (vuint16mf2x8_t): Ditto. (vint16m1x2_t): Ditto. (vuint16m1x2_t): Ditto. (vint16m1x3_t): Ditto. (vuint16m1x3_t): Ditto. (vint16m1x4_t): Ditto. (vuint16m1x4_t): Ditto. (vint16m1x5_t): Ditto. (vuint16m1x5_t): Ditto. (vint16m1x6_t): Ditto. (vuint16m1x6_t): Ditto. (vint16m1x7_t): Ditto. (vuint16m1x7_t): Ditto. (vint16m1x8_t): Ditto. (vuint16m1x8_t): Ditto. (vint16m2x2_t): Ditto. (vuint16m2x2_t): Ditto. (vint16m2x3_t): Ditto. (vuint16m2x3_t): Ditto. (vint16m2x4_t): Ditto. (vuint16m2x4_t): Ditto. (vint16m4x2_t): Ditto. (vuint16m4x2_t): Ditto. (vint32mf2x2_t): Ditto. (vuint32mf2x2_t): Ditto. (vint32mf2x3_t): Ditto. (vuint32mf2x3_t): Ditto. (vint32mf2x4_t): Ditto. (vuint32mf2x4_t): Ditto. (vint32mf2x5_t): Ditto. (vuint32mf2x5_t): Ditto. (vint32mf2x6_t): Ditto. (vuint32mf2x6_t): Ditto. (vint32mf2x7_t): Ditto. (vuint32mf2x7_t): Ditto. (vint32mf2x8_t): Ditto. (vuint32mf2x8_t): Ditto. (vint32m1x2_t): Ditto. (vuint32m1x2_t): Ditto. (vint32m1x3_t): Ditto. (vuint32m1x3_t): Ditto. (vint32m1x4_t): Ditto. (vuint32m1x4_t): Ditto. (vint32m1x5_t): Ditto. (vuint32m1x5_t): Ditto. (vint32m1x6_t): Ditto. (vuint32m1x6_t): Ditto. (vint32m1x7_t): Ditto. (vuint32m1x7_t): Ditto. (vint32m1x8_t): Ditto. (vuint32m1x8_t): Ditto. (vint32m2x2_t): Ditto. (vuint32m2x2_t): Ditto. (vint32m2x3_t): Ditto. (vuint32m2x3_t): Ditto. (vint32m2x4_t): Ditto. (vuint32m2x4_t): Ditto. (vint32m4x2_t): Ditto. (vuint32m4x2_t): Ditto. (vint64m1x2_t): Ditto. (vuint64m1x2_t): Ditto. (vint64m1x3_t): Ditto. (vuint64m1x3_t): Ditto. (vint64m1x4_t): Ditto. (vuint64m1x4_t): Ditto. (vint64m1x5_t): Ditto. (vuint64m1x5_t): Ditto. (vint64m1x6_t): Ditto. (vuint64m1x6_t): Ditto. (vint64m1x7_t): Ditto. (vuint64m1x7_t): Ditto. (vint64m1x8_t): Ditto. (vuint64m1x8_t): Ditto. (vint64m2x2_t): Ditto. (vuint64m2x2_t): Ditto. (vint64m2x3_t): Ditto. (vuint64m2x3_t): Ditto. (vint64m2x4_t): Ditto. (vuint64m2x4_t): Ditto. (vint64m4x2_t): Ditto. (vuint64m4x2_t): Ditto. (vfloat32mf2x2_t): Ditto. (vfloat32mf2x3_t): Ditto. (vfloat32mf2x4_t): Ditto. (vfloat32mf2x5_t): Ditto. (vfloat32mf2x6_t): Ditto. (vfloat32mf2x7_t): Ditto. (vfloat32mf2x8_t): Ditto. (vfloat32m1x2_t): Ditto. (vfloat32m1x3_t): Ditto. (vfloat32m1x4_t): Ditto. (vfloat32m1x5_t): Ditto. (vfloat32m1x6_t): Ditto. (vfloat32m1x7_t): Ditto. (vfloat32m1x8_t): Ditto. (vfloat32m2x2_t): Ditto. (vfloat32m2x3_t): Ditto. (vfloat32m2x4_t): Ditto. (vfloat32m4x2_t): Ditto. (vfloat64m1x2_t): Ditto. (vfloat64m1x3_t): Ditto. (vfloat64m1x4_t): Ditto. (vfloat64m1x5_t): Ditto. (vfloat64m1x6_t): Ditto. (vfloat64m1x7_t): Ditto. (vfloat64m1x8_t): Ditto. (vfloat64m2x2_t): Ditto. (vfloat64m2x3_t): Ditto. (vfloat64m2x4_t): Ditto. (vfloat64m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.h (DEF_RVV_TUPLE_TYPE): New macro define. * config/riscv/riscv-vector-switch.def (TUPLE_ENTRY): Ditto. * config/riscv/riscv.cc (riscv_v_ext_tuple_mode_p): New function. (TUPLE_ENTRY): New macro define. (riscv_v_ext_mode_p): New function. (riscv_v_adjust_nunits): Add tuple types. (riscv_classify_address): Ditto. (riscv_binary_cost): Ditto. (riscv_rtx_costs): Ditto. (riscv_secondary_memory_needed): Ditto. (riscv_hard_regno_nregs): Ditto. (riscv_hard_regno_mode_ok): Ditto. (riscv_vector_mode_supported_p): Ditto. (riscv_array_mode): Ditto. (TARGET_ARRAY_MODE): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/abi-10.c: New test. * gcc.target/riscv/rvv/base/abi-11.c: New test. * gcc.target/riscv/rvv/base/abi-12.c: New test. * gcc.target/riscv/rvv/base/abi-13.c: New test. * gcc.target/riscv/rvv/base/abi-14.c: New test. * gcc.target/riscv/rvv/base/abi-15.c: New test. * gcc.target/riscv/rvv/base/abi-16.c: New test. * gcc.target/riscv/rvv/base/abi-8.c: New test. * gcc.target/riscv/rvv/base/abi-9.c: New test. * gcc.target/riscv/rvv/base/user-10.c: New test. * gcc.target/riscv/rvv/base/user-11.c: New test. * gcc.target/riscv/rvv/base/user-12.c: New test. * gcc.target/riscv/rvv/base/user-13.c: New test. * gcc.target/riscv/rvv/base/user-14.c: New test. * gcc.target/riscv/rvv/base/user-15.c: New test. * gcc.target/riscv/rvv/base/user-7.c: New test. * gcc.target/riscv/rvv/base/user-8.c: New test. * gcc.target/riscv/rvv/base/user-9.c: New test. --- gcc/config/riscv/riscv-modes.def | 133 ++++++++++ gcc/config/riscv/riscv-protos.h | 4 + gcc/config/riscv/riscv-v.cc | 58 ++++- gcc/config/riscv/riscv-vector-builtins.cc | 78 ++++++ gcc/config/riscv/riscv-vector-builtins.def | 237 ++++++++++++++++++ gcc/config/riscv/riscv-vector-builtins.h | 1 + gcc/config/riscv/riscv-vector-switch.def | 176 +++++++++++++ gcc/config/riscv/riscv.cc | 88 ++++++- .../gcc.target/riscv/rvv/base/abi-10.c | 204 +++++++++++++++ .../gcc.target/riscv/rvv/base/abi-11.c | 204 +++++++++++++++ .../gcc.target/riscv/rvv/base/abi-12.c | 204 +++++++++++++++ .../gcc.target/riscv/rvv/base/abi-13.c | 204 +++++++++++++++ .../gcc.target/riscv/rvv/base/abi-14.c | 204 +++++++++++++++ .../gcc.target/riscv/rvv/base/abi-15.c | 204 +++++++++++++++ .../gcc.target/riscv/rvv/base/abi-16.c | 204 +++++++++++++++ .../gcc.target/riscv/rvv/base/abi-8.c | 205 +++++++++++++++ .../gcc.target/riscv/rvv/base/abi-9.c | 204 +++++++++++++++ .../gcc.target/riscv/rvv/base/user-10.c | 206 +++++++++++++++ .../gcc.target/riscv/rvv/base/user-11.c | 206 +++++++++++++++ .../gcc.target/riscv/rvv/base/user-12.c | 206 +++++++++++++++ .../gcc.target/riscv/rvv/base/user-13.c | 206 +++++++++++++++ .../gcc.target/riscv/rvv/base/user-14.c | 206 +++++++++++++++ .../gcc.target/riscv/rvv/base/user-15.c | 206 +++++++++++++++ .../gcc.target/riscv/rvv/base/user-7.c | 204 +++++++++++++++ .../gcc.target/riscv/rvv/base/user-8.c | 206 +++++++++++++++ .../gcc.target/riscv/rvv/base/user-9.c | 206 +++++++++++++++ 26 files changed, 4448 insertions(+), 16 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/abi-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/user-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/user-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/user-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/user-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/user-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/user-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/user-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/user-9.c diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def index b1669609eec..19a4f9fb3db 100644 --- a/gcc/config/riscv/riscv-modes.def +++ b/gcc/config/riscv/riscv-modes.def @@ -185,6 +185,139 @@ VECTOR_MODE_WITH_PREFIX (VNx, INT, QI, 1, 0); ADJUST_NUNITS (VNx1QI, riscv_v_adjust_nunits (VNx1QImode, 1)); ADJUST_ALIGNMENT (VNx1QI, 1); +/* Tuple modes for segment loads/stores according to NF, NF value can be 2 ~ 8. */ + +/* + | Mode | MIN_VLEN=32 | MIN_VLEN=32 | MIN_VLEN=64 | MIN_VLEN=64 | MIN_VLEN=128 | MIN_VLEN=128 | + | | LMUL | SEW/LMUL | LMUL | SEW/LMUL | LMUL | SEW/LMUL | + | VNxNFx1QI | MF4 | 32 | MF8 | 64 | N/A | N/A | + | VNxNFx2QI | MF2 | 16 | MF4 | 32 | MF8 | 64 | + | VNxNFx4QI | M1 | 8 | MF2 | 16 | MF4 | 32 | + | VNxNFx8QI | M2 | 4 | M1 | 8 | MF2 | 16 | + | VNxNFx16QI | M4 | 2 | M2 | 4 | M1 | 8 | + | VNxNFx32QI | M8 | 1 | M4 | 2 | M2 | 4 | + | VNxNFx64QI | N/A | N/A | M8 | 1 | M4 | 2 | + | VNxNFx128QI | N/A | N/A | N/A | N/A | M8 | 1 | + | VNxNFx1(HI|HF) | MF2 | 32 | MF4 | 64 | N/A | N/A | + | VNxNFx2(HI|HF) | M1 | 16 | MF2 | 32 | MF4 | 64 | + | VNxNFx4(HI|HF) | M2 | 8 | M1 | 16 | MF2 | 32 | + | VNxNFx8(HI|HF) | M4 | 4 | M2 | 8 | M1 | 16 | + | VNxNFx16(HI|HF)| M8 | 2 | M4 | 4 | M2 | 8 | + | VNxNFx32(HI|HF)| N/A | N/A | M8 | 2 | M4 | 4 | + | VNxNFx64(HI|HF)| N/A | N/A | N/A | N/A | M8 | 2 | + | VNxNFx1(SI|SF) | M1 | 32 | MF2 | 64 | MF2 | 64 | + | VNxNFx2(SI|SF) | M2 | 16 | M1 | 32 | M1 | 32 | + | VNxNFx4(SI|SF) | M4 | 8 | M2 | 16 | M2 | 16 | + | VNxNFx8(SI|SF) | M8 | 4 | M4 | 8 | M4 | 8 | + | VNxNFx16(SI|SF)| N/A | N/A | M8 | 4 | M8 | 4 | + | VNxNFx1(DI|DF) | N/A | N/A | M1 | 64 | N/A | N/A | + | VNxNFx2(DI|DF) | N/A | N/A | M2 | 32 | M1 | 64 | + | VNxNFx4(DI|DF) | N/A | N/A | M4 | 16 | M2 | 32 | + | VNxNFx8(DI|DF) | N/A | N/A | M8 | 8 | M4 | 16 | + | VNxNFx16(DI|DF)| N/A | N/A | N/A | N/A | M8 | 8 | +*/ + +#define RVV_TUPLE_MODES(NBYTES, NSUBPARTS, VB, VH, VS, VD) \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, NBYTES, 1); \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, HI, NBYTES / 2, 1); \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, SI, NBYTES / 4, 1); \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, SF, NBYTES / 4, 1); \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, DI, NBYTES / 8, 1); \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, DF, NBYTES / 8, 1); \ + ADJUST_NUNITS (VNx##NSUBPARTS##x##VB##QI, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VB##QI##mode, \ + VB * NSUBPARTS)); \ + ADJUST_NUNITS (VNx##NSUBPARTS##x##VH##HI, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VH##HI##mode, \ + VH * NSUBPARTS)); \ + ADJUST_NUNITS (VNx##NSUBPARTS##x##VS##SI, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VS##SI##mode, \ + VS * NSUBPARTS)); \ + ADJUST_NUNITS (VNx##NSUBPARTS##x##VD##DI, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VD##DI##mode, \ + VD * NSUBPARTS)); \ + ADJUST_NUNITS (VNx##NSUBPARTS##x##VS##SF, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VS##SF##mode, \ + VS * NSUBPARTS)); \ + ADJUST_NUNITS (VNx##NSUBPARTS##x##VD##DF, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x##VD##DF##mode, \ + VD * NSUBPARTS)); \ + \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VB##QI, 1); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VH##HI, 2); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VS##SI, 4); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VD##DI, 8); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VS##SF, 4); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x##VD##DF, 8); + +RVV_TUPLE_MODES (8, 2, 8, 4, 2, 1) +RVV_TUPLE_MODES (8, 3, 8, 4, 2, 1) +RVV_TUPLE_MODES (8, 4, 8, 4, 2, 1) +RVV_TUPLE_MODES (8, 5, 8, 4, 2, 1) +RVV_TUPLE_MODES (8, 6, 8, 4, 2, 1) +RVV_TUPLE_MODES (8, 7, 8, 4, 2, 1) +RVV_TUPLE_MODES (8, 8, 8, 4, 2, 1) + +RVV_TUPLE_MODES (16, 2, 16, 8, 4, 2) +RVV_TUPLE_MODES (16, 3, 16, 8, 4, 2) +RVV_TUPLE_MODES (16, 4, 16, 8, 4, 2) +RVV_TUPLE_MODES (16, 5, 16, 8, 4, 2) +RVV_TUPLE_MODES (16, 6, 16, 8, 4, 2) +RVV_TUPLE_MODES (16, 7, 16, 8, 4, 2) +RVV_TUPLE_MODES (16, 8, 16, 8, 4, 2) + +RVV_TUPLE_MODES (32, 2, 32, 16, 8, 4) +RVV_TUPLE_MODES (32, 3, 32, 16, 8, 4) +RVV_TUPLE_MODES (32, 4, 32, 16, 8, 4) + +RVV_TUPLE_MODES (64, 2, 64, 32, 16, 8) + +#define RVV_TUPLE_PARTIAL_MODES(NSUBPARTS) \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, 1, 1); \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, HI, 1, 1); \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, SI, 1, 1); \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, FLOAT, SF, 1, 1); \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, 2, 1); \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, HI, 2, 1); \ + VECTOR_MODE_WITH_PREFIX (VNx##NSUBPARTS##x, INT, QI, 4, 1); \ + \ + ADJUST_NUNITS (VNx##NSUBPARTS##x1QI, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x1QI##mode, \ + NSUBPARTS)); \ + ADJUST_NUNITS (VNx##NSUBPARTS##x1HI, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x1HI##mode, \ + NSUBPARTS)); \ + ADJUST_NUNITS (VNx##NSUBPARTS##x1SI, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x1SI##mode, \ + NSUBPARTS)); \ + ADJUST_NUNITS (VNx##NSUBPARTS##x1SF, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x1SF##mode, \ + NSUBPARTS)); \ + ADJUST_NUNITS (VNx##NSUBPARTS##x2QI, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x2QI##mode, \ + 2 * NSUBPARTS)); \ + ADJUST_NUNITS (VNx##NSUBPARTS##x2HI, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x2HI##mode, \ + 2 * NSUBPARTS)); \ + ADJUST_NUNITS (VNx##NSUBPARTS##x4QI, \ + riscv_v_adjust_nunits (VNx##NSUBPARTS##x4QI##mode, \ + 4 * NSUBPARTS)); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1QI, 1); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1HI, 2); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1SI, 4); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x1SF, 4); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x2QI, 1); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x2HI, 2); \ + ADJUST_ALIGNMENT (VNx##NSUBPARTS##x4QI, 1); + +RVV_TUPLE_PARTIAL_MODES (2) +RVV_TUPLE_PARTIAL_MODES (3) +RVV_TUPLE_PARTIAL_MODES (4) +RVV_TUPLE_PARTIAL_MODES (5) +RVV_TUPLE_PARTIAL_MODES (6) +RVV_TUPLE_PARTIAL_MODES (7) +RVV_TUPLE_PARTIAL_MODES (8) + /* TODO: According to RISC-V 'V' ISA spec, the maximun vector length can be 65536 for a single vector register which means the vector mode in GCC can be maximum = 65536 * 8 bits (LMUL=8). diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 5244e8dcbf0..becd6f84628 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -78,6 +78,7 @@ extern bool riscv_gpr_save_operation_p (rtx); extern void riscv_reinit (void); extern poly_uint64 riscv_regmode_natural_size (machine_mode); extern bool riscv_v_ext_vector_mode_p (machine_mode); +extern bool riscv_v_ext_tuple_mode_p (machine_mode); extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); /* Routines implemented in riscv-c.cc. */ @@ -165,6 +166,8 @@ void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode); void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode); enum vlmul_type get_vlmul (machine_mode); unsigned int get_ratio (machine_mode); +unsigned int get_nf (machine_mode); +machine_mode get_subpart_mode (machine_mode); int get_ta (rtx); int get_ma (rtx); int get_avl_type (rtx); @@ -186,6 +189,7 @@ enum tail_policy get_prefer_tail_policy (); enum mask_policy get_prefer_mask_policy (); rtx get_avl_type_rtx (enum avl_type); opt_machine_mode get_vector_mode (scalar_mode, poly_uint64); +opt_machine_mode get_tuple_mode (machine_mode, unsigned int); bool simm5_p (rtx); bool neg_simm5_p (rtx); #ifdef RTX_CODE diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 99c414cc910..97b7ebee157 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -342,17 +342,32 @@ struct mode_vtype_group uint8_t ratio_for_min_vlen64[NUM_MACHINE_MODES]; enum vlmul_type vlmul_for_for_vlen128[NUM_MACHINE_MODES]; uint8_t ratio_for_for_vlen128[NUM_MACHINE_MODES]; + machine_mode subpart_mode[NUM_MACHINE_MODES]; + uint8_t nf[NUM_MACHINE_MODES]; mode_vtype_group () { #define ENTRY(MODE, REQUIREMENT, VLMUL_FOR_MIN_VLEN32, RATIO_FOR_MIN_VLEN32, \ VLMUL_FOR_MIN_VLEN64, RATIO_FOR_MIN_VLEN64, \ - VLMUL_FOR_FOR_VLEN128, RATIO_FOR_FOR_VLEN128) \ + VLMUL_FOR_MIN_VLEN128, RATIO_FOR_MIN_VLEN128) \ vlmul_for_min_vlen32[MODE##mode] = VLMUL_FOR_MIN_VLEN32; \ ratio_for_min_vlen32[MODE##mode] = RATIO_FOR_MIN_VLEN32; \ vlmul_for_min_vlen64[MODE##mode] = VLMUL_FOR_MIN_VLEN64; \ ratio_for_min_vlen64[MODE##mode] = RATIO_FOR_MIN_VLEN64; \ - vlmul_for_for_vlen128[MODE##mode] = VLMUL_FOR_FOR_VLEN128; \ - ratio_for_for_vlen128[MODE##mode] = RATIO_FOR_FOR_VLEN128; + vlmul_for_for_vlen128[MODE##mode] = VLMUL_FOR_MIN_VLEN128; \ + ratio_for_for_vlen128[MODE##mode] = RATIO_FOR_MIN_VLEN128; +#include "riscv-vector-switch.def" +#define TUPLE_ENTRY(MODE, REQUIREMENT, SUBPART_MODE, NF, VLMUL_FOR_MIN_VLEN32, \ + RATIO_FOR_MIN_VLEN32, VLMUL_FOR_MIN_VLEN64, \ + RATIO_FOR_MIN_VLEN64, VLMUL_FOR_MIN_VLEN128, \ + RATIO_FOR_MIN_VLEN128) \ + subpart_mode[MODE##mode] = SUBPART_MODE##mode; \ + nf[MODE##mode] = NF; \ + vlmul_for_min_vlen32[MODE##mode] = VLMUL_FOR_MIN_VLEN32; \ + ratio_for_min_vlen32[MODE##mode] = RATIO_FOR_MIN_VLEN32; \ + vlmul_for_min_vlen64[MODE##mode] = VLMUL_FOR_MIN_VLEN64; \ + ratio_for_min_vlen64[MODE##mode] = RATIO_FOR_MIN_VLEN64; \ + vlmul_for_for_vlen128[MODE##mode] = VLMUL_FOR_MIN_VLEN128; \ + ratio_for_for_vlen128[MODE##mode] = RATIO_FOR_MIN_VLEN128; #include "riscv-vector-switch.def" } }; @@ -371,6 +386,26 @@ get_vlmul (machine_mode mode) return mode_vtype_infos.vlmul_for_min_vlen64[mode]; } +/* Return the NF value of the corresponding mode. */ +unsigned int +get_nf (machine_mode mode) +{ + /* We don't allow non-tuple modes go through this function. */ + gcc_assert (riscv_v_ext_tuple_mode_p (mode)); + return mode_vtype_infos.nf[mode]; +} + +/* Return the subpart mode of the tuple mode. For VNx2x1SImode, + the subpart mode is VNx1SImode. This will help to build + array/struct type in builtins. */ +machine_mode +get_subpart_mode (machine_mode mode) +{ + /* We don't allow non-tuple modes go through this function. */ + gcc_assert (riscv_v_ext_tuple_mode_p (mode)); + return mode_vtype_infos.subpart_mode[mode]; +} + /* Get ratio according to machine mode. */ unsigned int get_ratio (machine_mode mode) @@ -452,6 +487,23 @@ get_vector_mode (scalar_mode inner_mode, poly_uint64 nunits) return opt_machine_mode (); } +/* Return the RVV tuple mode if we can find the legal tuple mode for the + corresponding subpart mode and NF. */ +opt_machine_mode +get_tuple_mode (machine_mode subpart_mode, unsigned int nf) +{ + poly_uint64 nunits = GET_MODE_NUNITS (subpart_mode) * nf; + scalar_mode inner_mode = GET_MODE_INNER (subpart_mode); + enum mode_class mclass = GET_MODE_CLASS (subpart_mode); + machine_mode mode; + FOR_EACH_MODE_IN_CLASS (mode, mclass) + if (inner_mode == GET_MODE_INNER (mode) + && known_eq (nunits, GET_MODE_NUNITS (mode)) + && riscv_v_ext_tuple_mode_p (mode)) + return mode; + return opt_machine_mode (); +} + bool simm5_p (rtx x) { diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 434bd8e157b..3cfa9c90181 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -95,6 +95,8 @@ struct registered_function_hasher : nofree_ptr_hash static CONSTEXPR const vector_type_info vector_types[] = { #define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, ARGS...) \ {#NAME, #ABI_NAME, "u" #NCHARS #ABI_NAME}, +#define DEF_RVV_TUPLE_TYPE(NAME, NCHARS, ABI_NAME, ARGS...) \ + {#NAME, #ABI_NAME, "u" #NCHARS #ABI_NAME}, #include "riscv-vector-builtins.def" }; @@ -112,6 +114,9 @@ const rvv_builtin_suffixes type_suffixes[NUM_VECTOR_TYPES + 1] = { VECTOR_MODE_MIN_VLEN_32, VECTOR_SUFFIX, SCALAR_SUFFIX, \ VSETVL_SUFFIX) \ {#VECTOR_SUFFIX, #SCALAR_SUFFIX, #VSETVL_SUFFIX}, +#define DEF_RVV_TUPLE_TYPE(NAME, NCHARS, ABI_NAME, SUBPART_TYPE, SCALAR_TYPE, \ + NF, VECTOR_SUFFIX) \ + {#VECTOR_SUFFIX, "", ""}, #include "riscv-vector-builtins.def" }; @@ -2336,6 +2341,75 @@ register_builtin_type (vector_type_index type, tree eltype, machine_mode mode) lang_hooks.types.register_builtin_type (vectype, vector_types[type].abi_name); } +/* Register the tuple type that contains NUM_VECTORS vectors of type TYPE. */ +static void +register_tuple_type (vector_type_index type, vector_type_index subpart_type, + tree eltype, unsigned int nf) +{ + /* TODO: We currently just skip the register of the illegal RVV type. + Ideally, we should report error message more friendly instead of + reporting "unknown" type. Support more friendly error message in + the future. */ + if (!abi_vector_types[subpart_type]) + return; + tree tuple_type = lang_hooks.types.make_type (RECORD_TYPE); + + /* The contents of the type are opaque, so we can define them in any + way that maps to the correct ABI type. + + Here we choose to use the same layout as for riscv_vector.h, with + "__val": + + struct vfooxN_t { vfoo_t __val[N]; }; + + (It wouldn't be possible to write that directly in C or C++ for + sizeless types, but that's not a problem for this function.) + + Using arrays simplifies the handling of vget and vset for variable + arguments. */ + tree array_type = build_array_type_nelts (abi_vector_types[subpart_type], nf); + gcc_assert (array_type); + gcc_assert (VECTOR_MODE_P (TYPE_MODE (array_type)) + && TYPE_MODE_RAW (array_type) == TYPE_MODE (array_type)); + + tree field = build_decl (input_location, FIELD_DECL, get_identifier ("__val"), + array_type); + DECL_FIELD_CONTEXT (field) = tuple_type; + TYPE_FIELDS (tuple_type) = field; + add_vector_type_attribute (tuple_type, vector_types[type].mangled_name); + make_type_sizeless (tuple_type); + layout_type (tuple_type); + gcc_assert (VECTOR_MODE_P (TYPE_MODE (tuple_type)) + && TYPE_MODE_RAW (tuple_type) == TYPE_MODE (tuple_type)); + + tree decl + = build_decl (input_location, TYPE_DECL, + get_identifier (vector_types[type].abi_name), tuple_type); + TYPE_NAME (tuple_type) = decl; + TYPE_STUB_DECL (tuple_type) = decl; + lang_hooks.decls.pushdecl (decl); + /* ??? Undo the effect of set_underlying_type for C. The C frontend + doesn't recognize DECL as a built-in because (as intended) the decl has + a real location instead of BUILTINS_LOCATION. The frontend therefore + treats the decl like a normal C "typedef struct foo foo;", expecting + the type for tag "struct foo" to have a dummy unnamed TYPE_DECL instead + of the named one we attached above. It then sets DECL_ORIGINAL_TYPE + on the supposedly unnamed decl, creating a circularity that upsets + dwarf2out. + + We don't want to follow the normal C model and create "struct foo" + tags for tuple types since (a) the types are supposed to be opaque + and (b) they couldn't be defined as a real struct anyway. Treating + the TYPE_DECLs as "typedef struct foo foo;" without creating + "struct foo" would lead to confusing error messages. */ + DECL_ORIGINAL_TYPE (decl) = NULL_TREE; + + builtin_types[type].scalar = eltype; + builtin_types[type].scalar_ptr = build_pointer_type (eltype); + builtin_types[type].scalar_const_ptr = build_const_pointer (eltype); + abi_vector_types[type] = tuple_type; +} + /* Register the built-in RVV ABI types, such as __rvv_int32m1_t. */ static void register_builtin_types () @@ -2358,6 +2432,10 @@ register_builtin_types () : TARGET_MIN_VLEN >= 64 ? VECTOR_MODE_MIN_VLEN_64##mode \ : VECTOR_MODE_MIN_VLEN_32##mode; \ register_builtin_type (VECTOR_TYPE_##NAME, SCALAR_TYPE##_type_node, mode); +#define DEF_RVV_TUPLE_TYPE(NAME, NCHARS, ABI_NAME, SUBPART_TYPE, SCALAR_TYPE, \ + NF, VECTOR_SUFFIX) \ + register_tuple_type (VECTOR_TYPE_##NAME, VECTOR_TYPE_##SUBPART_TYPE, \ + SCALAR_TYPE##_type_node, NF); #include "riscv-vector-builtins.def" } diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def index 64c09b5d8cb..b0d6edda1b6 100644 --- a/gcc/config/riscv/riscv-vector-builtins.def +++ b/gcc/config/riscv/riscv-vector-builtins.def @@ -48,6 +48,11 @@ along with GCC; see the file COPYING3. If not see VSETVL_SUFFIX) #endif +#ifndef DEF_RVV_TUPLE_TYPE +#define DEF_RVV_TUPLE_TYPE(NAME, NCHARS, ABI_NAME, SUBPART_TYPE, SCALAR_TYPE, \ + NF, VECTOR_SUFFIX) +#endif + /* Use "DEF_RVV_OP_TYPE" macro to define RVV operand types. The 'NAME' will be concatenated into intrinsic function name. */ #ifndef DEF_RVV_OP_TYPE @@ -323,6 +328,237 @@ DEF_RVV_TYPE (vfloat64m4_t, 17, __rvv_float64m4_t, double, VNx8DF, VNx4DF, VOID, DEF_RVV_TYPE (vfloat64m8_t, 17, __rvv_float64m8_t, double, VNx16DF, VNx8DF, VOID, _f64m8, _f64, _e64m8) +/* Define tuple type for segment loads/stores, each tuple type should always satisfy + naming with vintx_t. Note that it's always LMUL * NF <= 8. */ +/* Define tuple types for SEW = 8, LMUL = MF8. */ +DEF_RVV_TUPLE_TYPE (vint8mf8x2_t, 17, __rvv_int8mf8x2_t, vint8mf8_t, int8, 2, _i8mf8x2) +DEF_RVV_TUPLE_TYPE (vuint8mf8x2_t, 18, __rvv_uint8mf8x2_t, vuint8mf8_t, uint8, 2, _u8mf8x2) +DEF_RVV_TUPLE_TYPE (vint8mf8x3_t, 17, __rvv_int8mf8x3_t, vint8mf8_t, int8, 3, _i8mf8x3) +DEF_RVV_TUPLE_TYPE (vuint8mf8x3_t, 18, __rvv_uint8mf8x3_t, vuint8mf8_t, uint8, 3, _u8mf8x3) +DEF_RVV_TUPLE_TYPE (vint8mf8x4_t, 17, __rvv_int8mf8x4_t, vint8mf8_t, int8, 4, _i8mf8x4) +DEF_RVV_TUPLE_TYPE (vuint8mf8x4_t, 18, __rvv_uint8mf8x4_t, vuint8mf8_t, uint8, 4, _u8mf8x4) +DEF_RVV_TUPLE_TYPE (vint8mf8x5_t, 17, __rvv_int8mf8x5_t, vint8mf8_t, int8, 5, _i8mf8x5) +DEF_RVV_TUPLE_TYPE (vuint8mf8x5_t, 18, __rvv_uint8mf8x5_t, vuint8mf8_t, uint8, 5, _u8mf8x5) +DEF_RVV_TUPLE_TYPE (vint8mf8x6_t, 17, __rvv_int8mf8x6_t, vint8mf8_t, int8, 6, _i8mf8x6) +DEF_RVV_TUPLE_TYPE (vuint8mf8x6_t, 18, __rvv_uint8mf8x6_t, vuint8mf8_t, uint8, 6, _u8mf8x6) +DEF_RVV_TUPLE_TYPE (vint8mf8x7_t, 17, __rvv_int8mf8x7_t, vint8mf8_t, int8, 7, _i8mf8x7) +DEF_RVV_TUPLE_TYPE (vuint8mf8x7_t, 18, __rvv_uint8mf8x7_t, vuint8mf8_t, uint8, 7, _u8mf8x7) +DEF_RVV_TUPLE_TYPE (vint8mf8x8_t, 17, __rvv_int8mf8x8_t, vint8mf8_t, int8, 8, _i8mf8x8) +DEF_RVV_TUPLE_TYPE (vuint8mf8x8_t, 18, __rvv_uint8mf8x8_t, vuint8mf8_t, uint8, 8, _u8mf8x8) +/* Define tuple types for SEW = 8, LMUL = MF4. */ +DEF_RVV_TUPLE_TYPE (vint8mf4x2_t, 17, __rvv_int8mf4x2_t, vint8mf4_t, int8, 2, _i8mf4x2) +DEF_RVV_TUPLE_TYPE (vuint8mf4x2_t, 18, __rvv_uint8mf4x2_t, vuint8mf4_t, uint8, 2, _u8mf4x2) +DEF_RVV_TUPLE_TYPE (vint8mf4x3_t, 17, __rvv_int8mf4x3_t, vint8mf4_t, int8, 3, _i8mf4x3) +DEF_RVV_TUPLE_TYPE (vuint8mf4x3_t, 18, __rvv_uint8mf4x3_t, vuint8mf4_t, uint8, 3, _u8mf4x3) +DEF_RVV_TUPLE_TYPE (vint8mf4x4_t, 17, __rvv_int8mf4x4_t, vint8mf4_t, int8, 4, _i8mf4x4) +DEF_RVV_TUPLE_TYPE (vuint8mf4x4_t, 18, __rvv_uint8mf4x4_t, vuint8mf4_t, uint8, 4, _u8mf4x4) +DEF_RVV_TUPLE_TYPE (vint8mf4x5_t, 17, __rvv_int8mf4x5_t, vint8mf4_t, int8, 5, _i8mf4x5) +DEF_RVV_TUPLE_TYPE (vuint8mf4x5_t, 18, __rvv_uint8mf4x5_t, vuint8mf4_t, uint8, 5, _u8mf4x5) +DEF_RVV_TUPLE_TYPE (vint8mf4x6_t, 17, __rvv_int8mf4x6_t, vint8mf4_t, int8, 6, _i8mf4x6) +DEF_RVV_TUPLE_TYPE (vuint8mf4x6_t, 18, __rvv_uint8mf4x6_t, vuint8mf4_t, uint8, 6, _u8mf4x6) +DEF_RVV_TUPLE_TYPE (vint8mf4x7_t, 17, __rvv_int8mf4x7_t, vint8mf4_t, int8, 7, _i8mf4x7) +DEF_RVV_TUPLE_TYPE (vuint8mf4x7_t, 18, __rvv_uint8mf4x7_t, vuint8mf4_t, uint8, 7, _u8mf4x7) +DEF_RVV_TUPLE_TYPE (vint8mf4x8_t, 17, __rvv_int8mf4x8_t, vint8mf4_t, int8, 8, _i8mf4x8) +DEF_RVV_TUPLE_TYPE (vuint8mf4x8_t, 18, __rvv_uint8mf4x8_t, vuint8mf4_t, uint8, 8, _u8mf4x8) +/* Define tuple types for SEW = 8, LMUL = MF2. */ +DEF_RVV_TUPLE_TYPE (vint8mf2x2_t, 17, __rvv_int8mf2x2_t, vint8mf2_t, int8, 2, _i8mf2x2) +DEF_RVV_TUPLE_TYPE (vuint8mf2x2_t, 18, __rvv_uint8mf2x2_t, vuint8mf2_t, uint8, 2, _u8mf2x2) +DEF_RVV_TUPLE_TYPE (vint8mf2x3_t, 17, __rvv_int8mf2x3_t, vint8mf2_t, int8, 3, _i8mf2x3) +DEF_RVV_TUPLE_TYPE (vuint8mf2x3_t, 18, __rvv_uint8mf2x3_t, vuint8mf2_t, uint8, 3, _u8mf2x3) +DEF_RVV_TUPLE_TYPE (vint8mf2x4_t, 17, __rvv_int8mf2x4_t, vint8mf2_t, int8, 4, _i8mf2x4) +DEF_RVV_TUPLE_TYPE (vuint8mf2x4_t, 18, __rvv_uint8mf2x4_t, vuint8mf2_t, uint8, 4, _u8mf2x4) +DEF_RVV_TUPLE_TYPE (vint8mf2x5_t, 17, __rvv_int8mf2x5_t, vint8mf2_t, int8, 5, _i8mf2x5) +DEF_RVV_TUPLE_TYPE (vuint8mf2x5_t, 18, __rvv_uint8mf2x5_t, vuint8mf2_t, uint8, 5, _u8mf2x5) +DEF_RVV_TUPLE_TYPE (vint8mf2x6_t, 17, __rvv_int8mf2x6_t, vint8mf2_t, int8, 6, _i8mf2x6) +DEF_RVV_TUPLE_TYPE (vuint8mf2x6_t, 18, __rvv_uint8mf2x6_t, vuint8mf2_t, uint8, 6, _u8mf2x6) +DEF_RVV_TUPLE_TYPE (vint8mf2x7_t, 17, __rvv_int8mf2x7_t, vint8mf2_t, int8, 7, _i8mf2x7) +DEF_RVV_TUPLE_TYPE (vuint8mf2x7_t, 18, __rvv_uint8mf2x7_t, vuint8mf2_t, uint8, 7, _u8mf2x7) +DEF_RVV_TUPLE_TYPE (vint8mf2x8_t, 17, __rvv_int8mf2x8_t, vint8mf2_t, int8, 8, _i8mf2x8) +DEF_RVV_TUPLE_TYPE (vuint8mf2x8_t, 18, __rvv_uint8mf2x8_t, vuint8mf2_t, uint8, 8, _u8mf2x8) +/* Define tuple types for SEW = 8, LMUL = M1. */ +DEF_RVV_TUPLE_TYPE (vint8m1x2_t, 16, __rvv_int8m1x2_t, vint8m1_t, int8, 2, _i8m1x2) +DEF_RVV_TUPLE_TYPE (vuint8m1x2_t, 17, __rvv_uint8m1x2_t, vuint8m1_t, uint8, 2, _u8m1x2) +DEF_RVV_TUPLE_TYPE (vint8m1x3_t, 16, __rvv_int8m1x3_t, vint8m1_t, int8, 3, _i8m1x3) +DEF_RVV_TUPLE_TYPE (vuint8m1x3_t, 17, __rvv_uint8m1x3_t, vuint8m1_t, uint8, 3, _u8m1x3) +DEF_RVV_TUPLE_TYPE (vint8m1x4_t, 16, __rvv_int8m1x4_t, vint8m1_t, int8, 4, _i8m1x4) +DEF_RVV_TUPLE_TYPE (vuint8m1x4_t, 17, __rvv_uint8m1x4_t, vuint8m1_t, uint8, 4, _u8m1x4) +DEF_RVV_TUPLE_TYPE (vint8m1x5_t, 16, __rvv_int8m1x5_t, vint8m1_t, int8, 5, _i8m1x5) +DEF_RVV_TUPLE_TYPE (vuint8m1x5_t, 17, __rvv_uint8m1x5_t, vuint8m1_t, uint8, 5, _u8m1x5) +DEF_RVV_TUPLE_TYPE (vint8m1x6_t, 16, __rvv_int8m1x6_t, vint8m1_t, int8, 6, _i8m1x6) +DEF_RVV_TUPLE_TYPE (vuint8m1x6_t, 17, __rvv_uint8m1x6_t, vuint8m1_t, uint8, 6, _u8m1x6) +DEF_RVV_TUPLE_TYPE (vint8m1x7_t, 16, __rvv_int8m1x7_t, vint8m1_t, int8, 7, _i8m1x7) +DEF_RVV_TUPLE_TYPE (vuint8m1x7_t, 17, __rvv_uint8m1x7_t, vuint8m1_t, uint8, 7, _u8m1x7) +DEF_RVV_TUPLE_TYPE (vint8m1x8_t, 16, __rvv_int8m1x8_t, vint8m1_t, int8, 8, _i8m1x8) +DEF_RVV_TUPLE_TYPE (vuint8m1x8_t, 17, __rvv_uint8m1x8_t, vuint8m1_t, uint8, 8, _u8m1x8) +/* Define tuple types for SEW = 8, LMUL = M2. */ +DEF_RVV_TUPLE_TYPE (vint8m2x2_t, 16, __rvv_int8m2x2_t, vint8m2_t, int8, 2, _i8m2x2) +DEF_RVV_TUPLE_TYPE (vuint8m2x2_t, 17, __rvv_uint8m2x2_t, vuint8m2_t, uint8, 2, _u8m2x2) +DEF_RVV_TUPLE_TYPE (vint8m2x3_t, 16, __rvv_int8m2x3_t, vint8m2_t, int8, 3, _i8m2x3) +DEF_RVV_TUPLE_TYPE (vuint8m2x3_t, 17, __rvv_uint8m2x3_t, vuint8m2_t, uint8, 3, _u8m2x3) +DEF_RVV_TUPLE_TYPE (vint8m2x4_t, 16, __rvv_int8m2x4_t, vint8m2_t, int8, 4, _i8m2x4) +DEF_RVV_TUPLE_TYPE (vuint8m2x4_t, 17, __rvv_uint8m2x4_t, vuint8m2_t, uint8, 4, _u8m2x4) +/* Define tuple types for SEW = 8, LMUL = M4. */ +DEF_RVV_TUPLE_TYPE (vint8m4x2_t, 16, __rvv_int8m4x2_t, vint8m4_t, int8, 2, _i8m4x2) +DEF_RVV_TUPLE_TYPE (vuint8m4x2_t, 17, __rvv_uint8m4x2_t, vuint8m4_t, uint8, 2, _u8m4x2) +/* Define tuple types for SEW = 16, LMUL = MF4. */ +DEF_RVV_TUPLE_TYPE (vint16mf4x2_t, 18, __rvv_int16mf4x2_t, vint16mf4_t, int16, 2, _i16mf4x2) +DEF_RVV_TUPLE_TYPE (vuint16mf4x2_t, 19, __rvv_uint16mf4x2_t, vuint16mf4_t, uint16, 2, _u16mf4x2) +DEF_RVV_TUPLE_TYPE (vint16mf4x3_t, 18, __rvv_int16mf4x3_t, vint16mf4_t, int16, 3, _i16mf4x3) +DEF_RVV_TUPLE_TYPE (vuint16mf4x3_t, 19, __rvv_uint16mf4x3_t, vuint16mf4_t, uint16, 3, _u16mf4x3) +DEF_RVV_TUPLE_TYPE (vint16mf4x4_t, 18, __rvv_int16mf4x4_t, vint16mf4_t, int16, 4, _i16mf4x4) +DEF_RVV_TUPLE_TYPE (vuint16mf4x4_t, 19, __rvv_uint16mf4x4_t, vuint16mf4_t, uint16, 4, _u16mf4x4) +DEF_RVV_TUPLE_TYPE (vint16mf4x5_t, 18, __rvv_int16mf4x5_t, vint16mf4_t, int16, 5, _i16mf4x5) +DEF_RVV_TUPLE_TYPE (vuint16mf4x5_t, 19, __rvv_uint16mf4x5_t, vuint16mf4_t, uint16, 5, _u16mf4x5) +DEF_RVV_TUPLE_TYPE (vint16mf4x6_t, 18, __rvv_int16mf4x6_t, vint16mf4_t, int16, 6, _i16mf4x6) +DEF_RVV_TUPLE_TYPE (vuint16mf4x6_t, 19, __rvv_uint16mf4x6_t, vuint16mf4_t, uint16, 6, _u16mf4x6) +DEF_RVV_TUPLE_TYPE (vint16mf4x7_t, 18, __rvv_int16mf4x7_t, vint16mf4_t, int16, 7, _i16mf4x7) +DEF_RVV_TUPLE_TYPE (vuint16mf4x7_t, 19, __rvv_uint16mf4x7_t, vuint16mf4_t, uint16, 7, _u16mf4x7) +DEF_RVV_TUPLE_TYPE (vint16mf4x8_t, 18, __rvv_int16mf4x8_t, vint16mf4_t, int16, 8, _i16mf4x8) +DEF_RVV_TUPLE_TYPE (vuint16mf4x8_t, 19, __rvv_uint16mf4x8_t, vuint16mf4_t, uint16, 8, _u16mf4x8) +/* Define tuple types for SEW = 16, LMUL = MF2. */ +DEF_RVV_TUPLE_TYPE (vint16mf2x2_t, 18, __rvv_int16mf2x2_t, vint16mf2_t, int16, 2, _i16mf2x2) +DEF_RVV_TUPLE_TYPE (vuint16mf2x2_t, 19, __rvv_uint16mf2x2_t, vuint16mf2_t, uint16, 2, _u16mf2x2) +DEF_RVV_TUPLE_TYPE (vint16mf2x3_t, 18, __rvv_int16mf2x3_t, vint16mf2_t, int16, 3, _i16mf2x3) +DEF_RVV_TUPLE_TYPE (vuint16mf2x3_t, 19, __rvv_uint16mf2x3_t, vuint16mf2_t, uint16, 3, _u16mf2x3) +DEF_RVV_TUPLE_TYPE (vint16mf2x4_t, 18, __rvv_int16mf2x4_t, vint16mf2_t, int16, 4, _i16mf2x4) +DEF_RVV_TUPLE_TYPE (vuint16mf2x4_t, 19, __rvv_uint16mf2x4_t, vuint16mf2_t, uint16, 4, _u16mf2x4) +DEF_RVV_TUPLE_TYPE (vint16mf2x5_t, 18, __rvv_int16mf2x5_t, vint16mf2_t, int16, 5, _i16mf2x5) +DEF_RVV_TUPLE_TYPE (vuint16mf2x5_t, 19, __rvv_uint16mf2x5_t, vuint16mf2_t, uint16, 5, _u16mf2x5) +DEF_RVV_TUPLE_TYPE (vint16mf2x6_t, 18, __rvv_int16mf2x6_t, vint16mf2_t, int16, 6, _i16mf2x6) +DEF_RVV_TUPLE_TYPE (vuint16mf2x6_t, 19, __rvv_uint16mf2x6_t, vuint16mf2_t, uint16, 6, _u16mf2x6) +DEF_RVV_TUPLE_TYPE (vint16mf2x7_t, 18, __rvv_int16mf2x7_t, vint16mf2_t, int16, 7, _i16mf2x7) +DEF_RVV_TUPLE_TYPE (vuint16mf2x7_t, 19, __rvv_uint16mf2x7_t, vuint16mf2_t, uint16, 7, _u16mf2x7) +DEF_RVV_TUPLE_TYPE (vint16mf2x8_t, 18, __rvv_int16mf2x8_t, vint16mf2_t, int16, 8, _i16mf2x8) +DEF_RVV_TUPLE_TYPE (vuint16mf2x8_t, 19, __rvv_uint16mf2x8_t, vuint16mf2_t, uint16, 8, _u16mf2x8) +/* Define tuple types for SEW = 16, LMUL = M1. */ +DEF_RVV_TUPLE_TYPE (vint16m1x2_t, 17, __rvv_int16m1x2_t, vint16m1_t, int16, 2, _i16m1x2) +DEF_RVV_TUPLE_TYPE (vuint16m1x2_t, 18, __rvv_uint16m1x2_t, vuint16m1_t, uint16, 2, _u16m1x2) +DEF_RVV_TUPLE_TYPE (vint16m1x3_t, 17, __rvv_int16m1x3_t, vint16m1_t, int16, 3, _i16m1x3) +DEF_RVV_TUPLE_TYPE (vuint16m1x3_t, 18, __rvv_uint16m1x3_t, vuint16m1_t, uint16, 3, _u16m1x3) +DEF_RVV_TUPLE_TYPE (vint16m1x4_t, 17, __rvv_int16m1x4_t, vint16m1_t, int16, 4, _i16m1x4) +DEF_RVV_TUPLE_TYPE (vuint16m1x4_t, 18, __rvv_uint16m1x4_t, vuint16m1_t, uint16, 4, _u16m1x4) +DEF_RVV_TUPLE_TYPE (vint16m1x5_t, 17, __rvv_int16m1x5_t, vint16m1_t, int16, 5, _i16m1x5) +DEF_RVV_TUPLE_TYPE (vuint16m1x5_t, 18, __rvv_uint16m1x5_t, vuint16m1_t, uint16, 5, _u16m1x5) +DEF_RVV_TUPLE_TYPE (vint16m1x6_t, 17, __rvv_int16m1x6_t, vint16m1_t, int16, 6, _i16m1x6) +DEF_RVV_TUPLE_TYPE (vuint16m1x6_t, 18, __rvv_uint16m1x6_t, vuint16m1_t, uint16, 6, _u16m1x6) +DEF_RVV_TUPLE_TYPE (vint16m1x7_t, 17, __rvv_int16m1x7_t, vint16m1_t, int16, 7, _i16m1x7) +DEF_RVV_TUPLE_TYPE (vuint16m1x7_t, 18, __rvv_uint16m1x7_t, vuint16m1_t, uint16, 7, _u16m1x7) +DEF_RVV_TUPLE_TYPE (vint16m1x8_t, 17, __rvv_int16m1x8_t, vint16m1_t, int16, 8, _i16m1x8) +DEF_RVV_TUPLE_TYPE (vuint16m1x8_t, 18, __rvv_uint16m1x8_t, vuint16m1_t, uint16, 8, _u16m1x8) +/* Define tuple types for SEW = 16, LMUL = M2. */ +DEF_RVV_TUPLE_TYPE (vint16m2x2_t, 17, __rvv_int16m2x2_t, vint16m2_t, int16, 2, _i16m2x2) +DEF_RVV_TUPLE_TYPE (vuint16m2x2_t, 18, __rvv_uint16m2x2_t, vuint16m2_t, uint16, 2, _u16m2x2) +DEF_RVV_TUPLE_TYPE (vint16m2x3_t, 17, __rvv_int16m2x3_t, vint16m2_t, int16, 3, _i16m2x3) +DEF_RVV_TUPLE_TYPE (vuint16m2x3_t, 18, __rvv_uint16m2x3_t, vuint16m2_t, uint16, 3, _u16m2x3) +DEF_RVV_TUPLE_TYPE (vint16m2x4_t, 17, __rvv_int16m2x4_t, vint16m2_t, int16, 4, _i16m2x4) +DEF_RVV_TUPLE_TYPE (vuint16m2x4_t, 18, __rvv_uint16m2x4_t, vuint16m2_t, uint16, 4, _u16m2x4) +/* Define tuple types for SEW = 16, LMUL = M4. */ +DEF_RVV_TUPLE_TYPE (vint16m4x2_t, 17, __rvv_int16m4x2_t, vint16m4_t, int16, 2, _i16m4x2) +DEF_RVV_TUPLE_TYPE (vuint16m4x2_t, 18, __rvv_uint16m4x2_t, vuint16m4_t, uint16, 2, _u16m4x2) +/* Define tuple types for SEW = 32, LMUL = MF2. */ +DEF_RVV_TUPLE_TYPE (vint32mf2x2_t, 18, __rvv_int32mf2x2_t, vint32mf2_t, int32, 2, _i32mf2x2) +DEF_RVV_TUPLE_TYPE (vuint32mf2x2_t, 19, __rvv_uint32mf2x2_t, vuint32mf2_t, uint32, 2, _u32mf2x2) +DEF_RVV_TUPLE_TYPE (vint32mf2x3_t, 18, __rvv_int32mf2x3_t, vint32mf2_t, int32, 3, _i32mf2x3) +DEF_RVV_TUPLE_TYPE (vuint32mf2x3_t, 19, __rvv_uint32mf2x3_t, vuint32mf2_t, uint32, 3, _u32mf2x3) +DEF_RVV_TUPLE_TYPE (vint32mf2x4_t, 18, __rvv_int32mf2x4_t, vint32mf2_t, int32, 4, _i32mf2x4) +DEF_RVV_TUPLE_TYPE (vuint32mf2x4_t, 19, __rvv_uint32mf2x4_t, vuint32mf2_t, uint32, 4, _u32mf2x4) +DEF_RVV_TUPLE_TYPE (vint32mf2x5_t, 18, __rvv_int32mf2x5_t, vint32mf2_t, int32, 5, _i32mf2x5) +DEF_RVV_TUPLE_TYPE (vuint32mf2x5_t, 19, __rvv_uint32mf2x5_t, vuint32mf2_t, uint32, 5, _u32mf2x5) +DEF_RVV_TUPLE_TYPE (vint32mf2x6_t, 18, __rvv_int32mf2x6_t, vint32mf2_t, int32, 6, _i32mf2x6) +DEF_RVV_TUPLE_TYPE (vuint32mf2x6_t, 19, __rvv_uint32mf2x6_t, vuint32mf2_t, uint32, 6, _u32mf2x6) +DEF_RVV_TUPLE_TYPE (vint32mf2x7_t, 18, __rvv_int32mf2x7_t, vint32mf2_t, int32, 7, _i32mf2x7) +DEF_RVV_TUPLE_TYPE (vuint32mf2x7_t, 19, __rvv_uint32mf2x7_t, vuint32mf2_t, uint32, 7, _u32mf2x7) +DEF_RVV_TUPLE_TYPE (vint32mf2x8_t, 18, __rvv_int32mf2x8_t, vint32mf2_t, int32, 8, _i32mf2x8) +DEF_RVV_TUPLE_TYPE (vuint32mf2x8_t, 19, __rvv_uint32mf2x8_t, vuint32mf2_t, uint32, 8, _u32mf2x8) +/* Define tuple types for SEW = 32, LMUL = M1. */ +DEF_RVV_TUPLE_TYPE (vint32m1x2_t, 17, __rvv_int32m1x2_t, vint32m1_t, int32, 2, _i32m1x2) +DEF_RVV_TUPLE_TYPE (vuint32m1x2_t, 18, __rvv_uint32m1x2_t, vuint32m1_t, uint32, 2, _u32m1x2) +DEF_RVV_TUPLE_TYPE (vint32m1x3_t, 17, __rvv_int32m1x3_t, vint32m1_t, int32, 3, _i32m1x3) +DEF_RVV_TUPLE_TYPE (vuint32m1x3_t, 18, __rvv_uint32m1x3_t, vuint32m1_t, uint32, 3, _u32m1x3) +DEF_RVV_TUPLE_TYPE (vint32m1x4_t, 17, __rvv_int32m1x4_t, vint32m1_t, int32, 4, _i32m1x4) +DEF_RVV_TUPLE_TYPE (vuint32m1x4_t, 18, __rvv_uint32m1x4_t, vuint32m1_t, uint32, 4, _u32m1x4) +DEF_RVV_TUPLE_TYPE (vint32m1x5_t, 17, __rvv_int32m1x5_t, vint32m1_t, int32, 5, _i32m1x5) +DEF_RVV_TUPLE_TYPE (vuint32m1x5_t, 18, __rvv_uint32m1x5_t, vuint32m1_t, uint32, 5, _u32m1x5) +DEF_RVV_TUPLE_TYPE (vint32m1x6_t, 17, __rvv_int32m1x6_t, vint32m1_t, int32, 6, _i32m1x6) +DEF_RVV_TUPLE_TYPE (vuint32m1x6_t, 18, __rvv_uint32m1x6_t, vuint32m1_t, uint32, 6, _u32m1x6) +DEF_RVV_TUPLE_TYPE (vint32m1x7_t, 17, __rvv_int32m1x7_t, vint32m1_t, int32, 7, _i32m1x7) +DEF_RVV_TUPLE_TYPE (vuint32m1x7_t, 18, __rvv_uint32m1x7_t, vuint32m1_t, uint32, 7, _u32m1x7) +DEF_RVV_TUPLE_TYPE (vint32m1x8_t, 17, __rvv_int32m1x8_t, vint32m1_t, int32, 8, _i32m1x8) +DEF_RVV_TUPLE_TYPE (vuint32m1x8_t, 18, __rvv_uint32m1x8_t, vuint32m1_t, uint32, 8, _u32m1x8) +/* Define tuple types for SEW = 32, LMUL = M2. */ +DEF_RVV_TUPLE_TYPE (vint32m2x2_t, 17, __rvv_int32m2x2_t, vint32m2_t, int32, 2, _i32m2x2) +DEF_RVV_TUPLE_TYPE (vuint32m2x2_t, 18, __rvv_uint32m2x2_t, vuint32m2_t, uint32, 2, _u32m2x2) +DEF_RVV_TUPLE_TYPE (vint32m2x3_t, 17, __rvv_int32m2x3_t, vint32m2_t, int32, 3, _i32m2x3) +DEF_RVV_TUPLE_TYPE (vuint32m2x3_t, 18, __rvv_uint32m2x3_t, vuint32m2_t, uint32, 3, _u32m2x3) +DEF_RVV_TUPLE_TYPE (vint32m2x4_t, 17, __rvv_int32m2x4_t, vint32m2_t, int32, 4, _i32m2x4) +DEF_RVV_TUPLE_TYPE (vuint32m2x4_t, 18, __rvv_uint32m2x4_t, vuint32m2_t, uint32, 4, _u32m2x4) +/* Define tuple types for SEW = 32, LMUL = M4. */ +DEF_RVV_TUPLE_TYPE (vint32m4x2_t, 17, __rvv_int32m4x2_t, vint32m4_t, int32, 2, _i32m4x2) +DEF_RVV_TUPLE_TYPE (vuint32m4x2_t, 18, __rvv_uint32m4x2_t, vuint32m4_t, uint32, 2, _u32m4x2) +/* Define tuple types for SEW = 64, LMUL = M1. */ +DEF_RVV_TUPLE_TYPE (vint64m1x2_t, 17, __rvv_int64m1x2_t, vint64m1_t, int64, 2, _i64m1x2) +DEF_RVV_TUPLE_TYPE (vuint64m1x2_t, 18, __rvv_uint64m1x2_t, vuint64m1_t, uint64, 2, _u64m1x2) +DEF_RVV_TUPLE_TYPE (vint64m1x3_t, 17, __rvv_int64m1x3_t, vint64m1_t, int64, 3, _i64m1x3) +DEF_RVV_TUPLE_TYPE (vuint64m1x3_t, 18, __rvv_uint64m1x3_t, vuint64m1_t, uint64, 3, _u64m1x3) +DEF_RVV_TUPLE_TYPE (vint64m1x4_t, 17, __rvv_int64m1x4_t, vint64m1_t, int64, 4, _i64m1x4) +DEF_RVV_TUPLE_TYPE (vuint64m1x4_t, 18, __rvv_uint64m1x4_t, vuint64m1_t, uint64, 4, _u64m1x4) +DEF_RVV_TUPLE_TYPE (vint64m1x5_t, 17, __rvv_int64m1x5_t, vint64m1_t, int64, 5, _i64m1x5) +DEF_RVV_TUPLE_TYPE (vuint64m1x5_t, 18, __rvv_uint64m1x5_t, vuint64m1_t, uint64, 5, _u64m1x5) +DEF_RVV_TUPLE_TYPE (vint64m1x6_t, 17, __rvv_int64m1x6_t, vint64m1_t, int64, 6, _i64m1x6) +DEF_RVV_TUPLE_TYPE (vuint64m1x6_t, 18, __rvv_uint64m1x6_t, vuint64m1_t, uint64, 6, _u64m1x6) +DEF_RVV_TUPLE_TYPE (vint64m1x7_t, 17, __rvv_int64m1x7_t, vint64m1_t, int64, 7, _i64m1x7) +DEF_RVV_TUPLE_TYPE (vuint64m1x7_t, 18, __rvv_uint64m1x7_t, vuint64m1_t, uint64, 7, _u64m1x7) +DEF_RVV_TUPLE_TYPE (vint64m1x8_t, 17, __rvv_int64m1x8_t, vint64m1_t, int64, 8, _i64m1x8) +DEF_RVV_TUPLE_TYPE (vuint64m1x8_t, 18, __rvv_uint64m1x8_t, vuint64m1_t, uint64, 8, _u64m1x8) +/* Define tuple types for SEW = 64, LMUL = M2. */ +DEF_RVV_TUPLE_TYPE (vint64m2x2_t, 17, __rvv_int64m2x2_t, vint64m2_t, int64, 2, _i64m2x2) +DEF_RVV_TUPLE_TYPE (vuint64m2x2_t, 18, __rvv_uint64m2x2_t, vuint64m2_t, uint64, 2, _u64m2x2) +DEF_RVV_TUPLE_TYPE (vint64m2x3_t, 17, __rvv_int64m2x3_t, vint64m2_t, int64, 3, _i64m2x3) +DEF_RVV_TUPLE_TYPE (vuint64m2x3_t, 18, __rvv_uint64m2x3_t, vuint64m2_t, uint64, 3, _u64m2x3) +DEF_RVV_TUPLE_TYPE (vint64m2x4_t, 17, __rvv_int64m2x4_t, vint64m2_t, int64, 4, _i64m2x4) +DEF_RVV_TUPLE_TYPE (vuint64m2x4_t, 18, __rvv_uint64m2x4_t, vuint64m2_t, uint64, 4, _u64m2x4) +/* Define tuple types for SEW = 64, LMUL = M4. */ +DEF_RVV_TUPLE_TYPE (vint64m4x2_t, 17, __rvv_int64m4x2_t, vint64m4_t, int64, 2, _i64m4x2) +DEF_RVV_TUPLE_TYPE (vuint64m4x2_t, 18, __rvv_uint64m4x2_t, vuint64m4_t, uint64, 2, _u64m4x2) + +/* Define floating-point tuple types. */ +/* Define tuple types for SEW = 32, LMUL = MF2. */ +DEF_RVV_TUPLE_TYPE (vfloat32mf2x2_t, 20, __rvv_float32mf2x2_t, vfloat32mf2_t, float, 2, _f32mf2x2) +DEF_RVV_TUPLE_TYPE (vfloat32mf2x3_t, 20, __rvv_float32mf2x3_t, vfloat32mf2_t, float, 3, _f32mf2x3) +DEF_RVV_TUPLE_TYPE (vfloat32mf2x4_t, 20, __rvv_float32mf2x4_t, vfloat32mf2_t, float, 4, _f32mf2x4) +DEF_RVV_TUPLE_TYPE (vfloat32mf2x5_t, 20, __rvv_float32mf2x5_t, vfloat32mf2_t, float, 5, _f32mf2x5) +DEF_RVV_TUPLE_TYPE (vfloat32mf2x6_t, 20, __rvv_float32mf2x6_t, vfloat32mf2_t, float, 6, _f32mf2x6) +DEF_RVV_TUPLE_TYPE (vfloat32mf2x7_t, 20, __rvv_float32mf2x7_t, vfloat32mf2_t, float, 7, _f32mf2x7) +DEF_RVV_TUPLE_TYPE (vfloat32mf2x8_t, 20, __rvv_float32mf2x8_t, vfloat32mf2_t, float, 8, _f32mf2x8) +/* Define tuple types for SEW = 32, LMUL = M1. */ +DEF_RVV_TUPLE_TYPE (vfloat32m1x2_t, 19, __rvv_float32m1x2_t, vfloat32m1_t, double, 2, _f32m1x2) +DEF_RVV_TUPLE_TYPE (vfloat32m1x3_t, 19, __rvv_float32m1x3_t, vfloat32m1_t, double, 3, _f32m1x3) +DEF_RVV_TUPLE_TYPE (vfloat32m1x4_t, 19, __rvv_float32m1x4_t, vfloat32m1_t, double, 4, _f32m1x4) +DEF_RVV_TUPLE_TYPE (vfloat32m1x5_t, 19, __rvv_float32m1x5_t, vfloat32m1_t, double, 5, _f32m1x5) +DEF_RVV_TUPLE_TYPE (vfloat32m1x6_t, 19, __rvv_float32m1x6_t, vfloat32m1_t, double, 6, _f32m1x6) +DEF_RVV_TUPLE_TYPE (vfloat32m1x7_t, 19, __rvv_float32m1x7_t, vfloat32m1_t, double, 7, _f32m1x7) +DEF_RVV_TUPLE_TYPE (vfloat32m1x8_t, 19, __rvv_float32m1x8_t, vfloat32m1_t, double, 8, _f32m1x8) +/* Define tuple types for SEW = 32, LMUL = M2. */ +DEF_RVV_TUPLE_TYPE (vfloat32m2x2_t, 19, __rvv_float32m2x2_t, vfloat32m2_t, double, 2, _f32m2x2) +DEF_RVV_TUPLE_TYPE (vfloat32m2x3_t, 19, __rvv_float32m2x3_t, vfloat32m2_t, double, 3, _f32m2x3) +DEF_RVV_TUPLE_TYPE (vfloat32m2x4_t, 19, __rvv_float32m2x4_t, vfloat32m2_t, double, 4, _f32m2x4) +/* Define tuple types for SEW = 32, LMUL = M4. */ +DEF_RVV_TUPLE_TYPE (vfloat32m4x2_t, 19, __rvv_float32m4x2_t, vfloat32m4_t, double, 2, _f32m4x2) +/* Define tuple types for SEW = 64, LMUL = M1. */ +DEF_RVV_TUPLE_TYPE (vfloat64m1x2_t, 19, __rvv_float64m1x2_t, vfloat64m1_t, double, 2, _f64m1x2) +DEF_RVV_TUPLE_TYPE (vfloat64m1x3_t, 19, __rvv_float64m1x3_t, vfloat64m1_t, double, 3, _f64m1x3) +DEF_RVV_TUPLE_TYPE (vfloat64m1x4_t, 19, __rvv_float64m1x4_t, vfloat64m1_t, double, 4, _f64m1x4) +DEF_RVV_TUPLE_TYPE (vfloat64m1x5_t, 19, __rvv_float64m1x5_t, vfloat64m1_t, double, 5, _f64m1x5) +DEF_RVV_TUPLE_TYPE (vfloat64m1x6_t, 19, __rvv_float64m1x6_t, vfloat64m1_t, double, 6, _f64m1x6) +DEF_RVV_TUPLE_TYPE (vfloat64m1x7_t, 19, __rvv_float64m1x7_t, vfloat64m1_t, double, 7, _f64m1x7) +DEF_RVV_TUPLE_TYPE (vfloat64m1x8_t, 19, __rvv_float64m1x8_t, vfloat64m1_t, double, 8, _f64m1x8) +/* Define tuple types for SEW = 64, LMUL = M2. */ +DEF_RVV_TUPLE_TYPE (vfloat64m2x2_t, 19, __rvv_float64m2x2_t, vfloat64m2_t, double, 2, _f64m2x2) +DEF_RVV_TUPLE_TYPE (vfloat64m2x3_t, 19, __rvv_float64m2x3_t, vfloat64m2_t, double, 3, _f64m2x3) +DEF_RVV_TUPLE_TYPE (vfloat64m2x4_t, 19, __rvv_float64m2x4_t, vfloat64m2_t, double, 4, _f64m2x4) +/* Define tuple types for SEW = 64, LMUL = M4. */ +DEF_RVV_TUPLE_TYPE (vfloat64m4x2_t, 19, __rvv_float64m4x2_t, vfloat64m4_t, double, 2, _f64m4x2) + DEF_RVV_OP_TYPE (vv) DEF_RVV_OP_TYPE (vx) DEF_RVV_OP_TYPE (v) @@ -417,5 +653,6 @@ DEF_RVV_BASE_TYPE (size_ptr, build_pointer_type (size_type_node)) #undef DEF_RVV_PRED_TYPE #undef DEF_RVV_OP_TYPE #undef DEF_RVV_TYPE +#undef DEF_RVV_TUPLE_TYPE #undef DEF_RVV_BASE_TYPE #undef DEF_RVV_TYPE_INDEX diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h index 8ffb9d33e33..93261a72134 100644 --- a/gcc/config/riscv/riscv-vector-builtins.h +++ b/gcc/config/riscv/riscv-vector-builtins.h @@ -123,6 +123,7 @@ enum operand_type_index enum vector_type_index { #define DEF_RVV_TYPE(NAME, ABI_NAME, NCHARS, ARGS...) VECTOR_TYPE_##NAME, +#define DEF_RVV_TUPLE_TYPE(NAME, ABI_NAME, NCHARS, ARGS...) VECTOR_TYPE_##NAME, #include "riscv-vector-builtins.def" NUM_VECTOR_TYPES, VECTOR_TYPE_INVALID = NUM_VECTOR_TYPES diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def index 8aae22d3259..4b1c32de0a3 100644 --- a/gcc/config/riscv/riscv-vector-switch.def +++ b/gcc/config/riscv/riscv-vector-switch.def @@ -84,6 +84,12 @@ TODO: FP16 vector needs support of 'zvfh', we don't support it yet. */ VLMUL_FOR_MIN_VLEN64, RATIO_FOR_MIN_VLEN64, \ VLMUL_FOR_MIN_VLEN128, RATIO_FOR_MIN_VLEN128) #endif +#ifndef TUPLE_ENTRY +#define TUPLE_ENTRY(MODE, REQUIREMENT, SUBPART_MODE, NF, VLMUL_FOR_MIN_VLEN32, \ + RATIO_FOR_MIN_VLEN32, VLMUL_FOR_MIN_VLEN64, \ + RATIO_FOR_MIN_VLEN64, VLMUL_FOR_MIN_VLEN128, \ + RATIO_FOR_MIN_VLEN128) +#endif /* Mask modes. Disable VNx64BImode when TARGET_MIN_VLEN == 32. */ ENTRY (VNx128BI, TARGET_MIN_VLEN >= 128, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_8, 1) @@ -157,4 +163,174 @@ ENTRY (VNx4DF, TARGET_VECTOR_ELEN_FP_64, LMUL_RESERVED, 0, LMUL_4, 16, LMUL_2, 3 ENTRY (VNx2DF, TARGET_VECTOR_ELEN_FP_64, LMUL_RESERVED, 0, LMUL_2, 32, LMUL_1, 64) ENTRY (VNx1DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) +/* Enable or disable the tuple type. BASE_MODE is the base vector mode of the + tuple mode. For example, the BASE_MODE of VNx2x1SImode is VNx1SImode. ALL + tuple modes should always satisfy NF * BASE_MODE LMUL <= 8. */ + +/* Tuple modes for EEW = 8. */ +TUPLE_ENTRY (VNx2x64QI, TARGET_MIN_VLEN >= 128, VNx64QI, 2, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_4, 2) +TUPLE_ENTRY (VNx2x32QI, TARGET_MIN_VLEN >= 64, VNx32QI, 2, LMUL_RESERVED, 0, LMUL_4, 2, LMUL_2, 4) +TUPLE_ENTRY (VNx3x32QI, TARGET_MIN_VLEN >= 128, VNx32QI, 3, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 4) +TUPLE_ENTRY (VNx4x32QI, TARGET_MIN_VLEN >= 128, VNx32QI, 4, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 4) +TUPLE_ENTRY (VNx2x16QI, true, VNx16QI, 2, LMUL_4, 2, LMUL_2, 4, LMUL_1, 8) +TUPLE_ENTRY (VNx3x16QI, TARGET_MIN_VLEN >= 64, VNx16QI, 3, LMUL_RESERVED, 0, LMUL_2, 4, LMUL_1, 8) +TUPLE_ENTRY (VNx4x16QI, TARGET_MIN_VLEN >= 64, VNx16QI, 4, LMUL_RESERVED, 0, LMUL_2, 4, LMUL_1, 8) +TUPLE_ENTRY (VNx5x16QI, TARGET_MIN_VLEN >= 128, VNx16QI, 5, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 8) +TUPLE_ENTRY (VNx6x16QI, TARGET_MIN_VLEN >= 128, VNx16QI, 6, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 8) +TUPLE_ENTRY (VNx7x16QI, TARGET_MIN_VLEN >= 128, VNx16QI, 7, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 8) +TUPLE_ENTRY (VNx8x16QI, TARGET_MIN_VLEN >= 128, VNx16QI, 8, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 8) +TUPLE_ENTRY (VNx2x8QI, true, VNx8QI, 2, LMUL_2, 4, LMUL_1, 8, LMUL_F2, 16) +TUPLE_ENTRY (VNx3x8QI, true, VNx8QI, 3, LMUL_2, 4, LMUL_1, 8, LMUL_F2, 16) +TUPLE_ENTRY (VNx4x8QI, true, VNx8QI, 4, LMUL_2, 4, LMUL_1, 8, LMUL_F2, 16) +TUPLE_ENTRY (VNx5x8QI, TARGET_MIN_VLEN >= 64, VNx8QI, 5, LMUL_RESERVED, 0, LMUL_1, 8, LMUL_F2, 16) +TUPLE_ENTRY (VNx6x8QI, TARGET_MIN_VLEN >= 64, VNx8QI, 6, LMUL_RESERVED, 0, LMUL_1, 8, LMUL_F2, 16) +TUPLE_ENTRY (VNx7x8QI, TARGET_MIN_VLEN >= 64, VNx8QI, 7, LMUL_RESERVED, 0, LMUL_1, 8, LMUL_F2, 16) +TUPLE_ENTRY (VNx8x8QI, TARGET_MIN_VLEN >= 64, VNx8QI, 8, LMUL_RESERVED, 0, LMUL_1, 8, LMUL_F2, 16) +TUPLE_ENTRY (VNx2x4QI, true, VNx4QI, 2, LMUL_1, 8, LMUL_F2, 16, LMUL_F4, 32) +TUPLE_ENTRY (VNx3x4QI, true, VNx4QI, 3, LMUL_1, 8, LMUL_F2, 16, LMUL_F4, 32) +TUPLE_ENTRY (VNx4x4QI, true, VNx4QI, 4, LMUL_1, 8, LMUL_F2, 16, LMUL_F4, 32) +TUPLE_ENTRY (VNx5x4QI, true, VNx4QI, 5, LMUL_1, 8, LMUL_F2, 16, LMUL_F4, 32) +TUPLE_ENTRY (VNx6x4QI, true, VNx4QI, 6, LMUL_1, 8, LMUL_F2, 16, LMUL_F4, 32) +TUPLE_ENTRY (VNx7x4QI, true, VNx4QI, 7, LMUL_1, 8, LMUL_F2, 16, LMUL_F4, 32) +TUPLE_ENTRY (VNx8x4QI, true, VNx4QI, 8, LMUL_1, 8, LMUL_F2, 16, LMUL_F4, 32) +TUPLE_ENTRY (VNx2x2QI, true, VNx2QI, 2, LMUL_F2, 16, LMUL_F4, 32, LMUL_F8, 64) +TUPLE_ENTRY (VNx3x2QI, true, VNx2QI, 3, LMUL_F2, 16, LMUL_F4, 32, LMUL_F8, 64) +TUPLE_ENTRY (VNx4x2QI, true, VNx2QI, 4, LMUL_F2, 16, LMUL_F4, 32, LMUL_F8, 64) +TUPLE_ENTRY (VNx5x2QI, true, VNx2QI, 5, LMUL_F2, 16, LMUL_F4, 32, LMUL_F8, 64) +TUPLE_ENTRY (VNx6x2QI, true, VNx2QI, 6, LMUL_F2, 16, LMUL_F4, 32, LMUL_F8, 64) +TUPLE_ENTRY (VNx7x2QI, true, VNx2QI, 7, LMUL_F2, 16, LMUL_F4, 32, LMUL_F8, 64) +TUPLE_ENTRY (VNx8x2QI, true, VNx2QI, 8, LMUL_F2, 16, LMUL_F4, 32, LMUL_F8, 64) +TUPLE_ENTRY (VNx2x1QI, TARGET_MIN_VLEN < 128, VNx1QI, 2, LMUL_F4, 32, LMUL_F8, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx3x1QI, TARGET_MIN_VLEN < 128, VNx1QI, 3, LMUL_F4, 32, LMUL_F8, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx4x1QI, TARGET_MIN_VLEN < 128, VNx1QI, 4, LMUL_F4, 32, LMUL_F8, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx5x1QI, TARGET_MIN_VLEN < 128, VNx1QI, 5, LMUL_F4, 32, LMUL_F8, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx6x1QI, TARGET_MIN_VLEN < 128, VNx1QI, 6, LMUL_F4, 32, LMUL_F8, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx7x1QI, TARGET_MIN_VLEN < 128, VNx1QI, 7, LMUL_F4, 32, LMUL_F8, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx8x1QI, TARGET_MIN_VLEN < 128, VNx1QI, 8, LMUL_F4, 32, LMUL_F8, 64, LMUL_RESERVED, 0) + +/* Tuple modes for EEW = 16. */ +TUPLE_ENTRY (VNx2x32HI, TARGET_MIN_VLEN >= 128, VNx32HI, 2, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_4, 4) +TUPLE_ENTRY (VNx2x16HI, TARGET_MIN_VLEN >= 64, VNx16HI, 2, LMUL_RESERVED, 0, LMUL_4, 4, LMUL_2, 8) +TUPLE_ENTRY (VNx3x16HI, TARGET_MIN_VLEN >= 128, VNx16HI, 3, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 8) +TUPLE_ENTRY (VNx4x16HI, TARGET_MIN_VLEN >= 128, VNx16HI, 4, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 8) +TUPLE_ENTRY (VNx2x8HI, true, VNx8HI, 2, LMUL_4, 4, LMUL_2, 8, LMUL_1, 16) +TUPLE_ENTRY (VNx3x8HI, TARGET_MIN_VLEN >= 64, VNx8HI, 3, LMUL_RESERVED, 0, LMUL_2, 8, LMUL_1, 16) +TUPLE_ENTRY (VNx4x8HI, TARGET_MIN_VLEN >= 64, VNx8HI, 4, LMUL_RESERVED, 0, LMUL_2, 8, LMUL_1, 16) +TUPLE_ENTRY (VNx5x8HI, TARGET_MIN_VLEN >= 128, VNx8HI, 5, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 16) +TUPLE_ENTRY (VNx6x8HI, TARGET_MIN_VLEN >= 128, VNx8HI, 6, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 16) +TUPLE_ENTRY (VNx7x8HI, TARGET_MIN_VLEN >= 128, VNx8HI, 7, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 16) +TUPLE_ENTRY (VNx8x8HI, TARGET_MIN_VLEN >= 128, VNx8HI, 8, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 16) +TUPLE_ENTRY (VNx2x4HI, true, VNx4HI, 2, LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32) +TUPLE_ENTRY (VNx3x4HI, true, VNx4HI, 3, LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32) +TUPLE_ENTRY (VNx4x4HI, true, VNx4HI, 4, LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32) +TUPLE_ENTRY (VNx5x4HI, TARGET_MIN_VLEN >= 64, VNx4HI, 5, LMUL_RESERVED, 0, LMUL_1, 16, LMUL_F2, 32) +TUPLE_ENTRY (VNx6x4HI, TARGET_MIN_VLEN >= 64, VNx4HI, 6, LMUL_RESERVED, 0, LMUL_1, 16, LMUL_F2, 32) +TUPLE_ENTRY (VNx7x4HI, TARGET_MIN_VLEN >= 64, VNx4HI, 7, LMUL_RESERVED, 0, LMUL_1, 16, LMUL_F2, 32) +TUPLE_ENTRY (VNx8x4HI, TARGET_MIN_VLEN >= 64, VNx4HI, 8, LMUL_RESERVED, 0, LMUL_1, 16, LMUL_F2, 32) +TUPLE_ENTRY (VNx2x2HI, true, VNx2HI, 2, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +TUPLE_ENTRY (VNx3x2HI, true, VNx2HI, 3, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +TUPLE_ENTRY (VNx4x2HI, true, VNx2HI, 4, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +TUPLE_ENTRY (VNx5x2HI, true, VNx2HI, 5, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +TUPLE_ENTRY (VNx6x2HI, true, VNx2HI, 6, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +TUPLE_ENTRY (VNx7x2HI, true, VNx2HI, 7, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +TUPLE_ENTRY (VNx8x2HI, true, VNx2HI, 8, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64) +TUPLE_ENTRY (VNx2x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 2, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx3x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 3, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx4x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 4, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx5x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 5, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx6x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 6, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx7x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 7, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx8x1HI, TARGET_MIN_VLEN < 128, VNx1HI, 8, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0) + +/* Tuple modes for EEW = 32. */ +TUPLE_ENTRY (VNx2x16SI, TARGET_MIN_VLEN >= 128, VNx16SI, 2, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_4, 8) +TUPLE_ENTRY (VNx2x8SI, TARGET_MIN_VLEN >= 64, VNx8SI, 2, LMUL_RESERVED, 0, LMUL_4, 8, LMUL_2, 16) +TUPLE_ENTRY (VNx3x8SI, TARGET_MIN_VLEN >= 128, VNx8SI, 3, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 16) +TUPLE_ENTRY (VNx4x8SI, TARGET_MIN_VLEN >= 128, VNx8SI, 4, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 16) +TUPLE_ENTRY (VNx2x4SI, true, VNx4SI, 2, LMUL_4, 8, LMUL_2, 16, LMUL_1, 32) +TUPLE_ENTRY (VNx3x4SI, TARGET_MIN_VLEN >= 64, VNx4SI, 3, LMUL_RESERVED, 0, LMUL_2, 16, LMUL_1, 32) +TUPLE_ENTRY (VNx4x4SI, TARGET_MIN_VLEN >= 64, VNx4SI, 4, LMUL_RESERVED, 0, LMUL_2, 16, LMUL_1, 32) +TUPLE_ENTRY (VNx5x4SI, TARGET_MIN_VLEN >= 128, VNx4SI, 5, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 32) +TUPLE_ENTRY (VNx6x4SI, TARGET_MIN_VLEN >= 128, VNx4SI, 6, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 32) +TUPLE_ENTRY (VNx7x4SI, TARGET_MIN_VLEN >= 128, VNx4SI, 7, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 32) +TUPLE_ENTRY (VNx8x4SI, TARGET_MIN_VLEN >= 128, VNx4SI, 8, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 32) +TUPLE_ENTRY (VNx2x2SI, true, VNx2SI, 2, LMUL_2, 16, LMUL_1, 32, LMUL_F2, 64) +TUPLE_ENTRY (VNx3x2SI, true, VNx2SI, 3, LMUL_2, 16, LMUL_1, 32, LMUL_F2, 64) +TUPLE_ENTRY (VNx4x2SI, true, VNx2SI, 4, LMUL_2, 16, LMUL_1, 32, LMUL_F2, 64) +TUPLE_ENTRY (VNx5x2SI, TARGET_MIN_VLEN >= 64, VNx2SI, 5, LMUL_RESERVED, 0, LMUL_1, 32, LMUL_F2, 64) +TUPLE_ENTRY (VNx6x2SI, TARGET_MIN_VLEN >= 64, VNx2SI, 6, LMUL_RESERVED, 0, LMUL_1, 32, LMUL_F2, 64) +TUPLE_ENTRY (VNx7x2SI, TARGET_MIN_VLEN >= 64, VNx2SI, 7, LMUL_RESERVED, 0, LMUL_1, 32, LMUL_F2, 64) +TUPLE_ENTRY (VNx8x2SI, TARGET_MIN_VLEN >= 64, VNx2SI, 8, LMUL_RESERVED, 0, LMUL_1, 32, LMUL_F2, 64) +TUPLE_ENTRY (VNx2x1SI, TARGET_MIN_VLEN < 128, VNx1SI, 2, LMUL_1, 32, LMUL_F2, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx3x1SI, TARGET_MIN_VLEN < 128, VNx1SI, 3, LMUL_1, 32, LMUL_F2, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx4x1SI, TARGET_MIN_VLEN < 128, VNx1SI, 4, LMUL_1, 32, LMUL_F2, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx5x1SI, TARGET_MIN_VLEN < 128, VNx1SI, 5, LMUL_1, 32, LMUL_F2, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx6x1SI, TARGET_MIN_VLEN < 128, VNx1SI, 6, LMUL_1, 32, LMUL_F2, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx7x1SI, TARGET_MIN_VLEN < 128, VNx1SI, 7, LMUL_1, 32, LMUL_F2, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx8x1SI, TARGET_MIN_VLEN < 128, VNx1SI, 8, LMUL_1, 32, LMUL_F2, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx2x16SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, VNx16SF, 2, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_4, 8) +TUPLE_ENTRY (VNx2x8SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64, VNx8SF, 2, LMUL_RESERVED, 0, LMUL_4, 8, LMUL_2, 16) +TUPLE_ENTRY (VNx3x8SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128, VNx8SF, 3, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 16) +TUPLE_ENTRY (VNx4x8SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128, VNx8SF, 4, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 16) +TUPLE_ENTRY (VNx2x4SF, TARGET_VECTOR_ELEN_FP_32, VNx4SF, 2, LMUL_4, 8, LMUL_2, 16, LMUL_1, 32) +TUPLE_ENTRY (VNx3x4SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64, VNx4SF, 3, LMUL_RESERVED, 0, LMUL_2, 16, LMUL_1, 32) +TUPLE_ENTRY (VNx4x4SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64, VNx4SF, 4, LMUL_RESERVED, 0, LMUL_2, 16, LMUL_1, 32) +TUPLE_ENTRY (VNx5x4SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128, VNx4SF, 5, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 32) +TUPLE_ENTRY (VNx6x4SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128, VNx4SF, 6, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 32) +TUPLE_ENTRY (VNx7x4SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128, VNx4SF, 7, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 32) +TUPLE_ENTRY (VNx8x4SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128, VNx4SF, 8, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 32) +TUPLE_ENTRY (VNx2x2SF, TARGET_VECTOR_ELEN_FP_32, VNx2SF, 2, LMUL_2, 16, LMUL_1, 32, LMUL_F2, 64) +TUPLE_ENTRY (VNx3x2SF, TARGET_VECTOR_ELEN_FP_32, VNx2SF, 3, LMUL_2, 16, LMUL_1, 32, LMUL_F2, 64) +TUPLE_ENTRY (VNx4x2SF, TARGET_VECTOR_ELEN_FP_32, VNx2SF, 4, LMUL_2, 16, LMUL_1, 32, LMUL_F2, 64) +TUPLE_ENTRY (VNx5x2SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64, VNx2SF, 5, LMUL_RESERVED, 0, LMUL_1, 32, LMUL_F2, 64) +TUPLE_ENTRY (VNx6x2SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64, VNx2SF, 6, LMUL_RESERVED, 0, LMUL_1, 32, LMUL_F2, 64) +TUPLE_ENTRY (VNx7x2SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64, VNx2SF, 7, LMUL_RESERVED, 0, LMUL_1, 32, LMUL_F2, 64) +TUPLE_ENTRY (VNx8x2SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64, VNx2SF, 8, LMUL_RESERVED, 0, LMUL_1, 32, LMUL_F2, 64) +TUPLE_ENTRY (VNx2x1SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128, VNx1SF, 2, LMUL_1, 32, LMUL_F2, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx3x1SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128, VNx1SF, 3, LMUL_1, 32, LMUL_F2, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx4x1SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128, VNx1SF, 4, LMUL_1, 32, LMUL_F2, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx5x1SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128, VNx1SF, 5, LMUL_1, 32, LMUL_F2, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx6x1SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128, VNx1SF, 6, LMUL_1, 32, LMUL_F2, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx7x1SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128, VNx1SF, 7, LMUL_1, 32, LMUL_F2, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx8x1SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128, VNx1SF, 8, LMUL_1, 32, LMUL_F2, 64, LMUL_RESERVED, 0) + +/* Tuple modes for EEW = 64. */ +TUPLE_ENTRY (VNx2x8DI, TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128, VNx8DI, 2, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_4, 16) +TUPLE_ENTRY (VNx2x4DI, TARGET_VECTOR_ELEN_64, VNx4DI, 2, LMUL_RESERVED, 0, LMUL_4, 16, LMUL_2, 32) +TUPLE_ENTRY (VNx3x4DI, TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128, VNx4DI, 3, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 32) +TUPLE_ENTRY (VNx4x4DI, TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128, VNx4DI, 4, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 32) +TUPLE_ENTRY (VNx2x2DI, TARGET_VECTOR_ELEN_64, VNx2DI, 2, LMUL_RESERVED, 0, LMUL_2, 32, LMUL_1, 64) +TUPLE_ENTRY (VNx3x2DI, TARGET_VECTOR_ELEN_64, VNx2DI, 3, LMUL_RESERVED, 0, LMUL_2, 32, LMUL_1, 64) +TUPLE_ENTRY (VNx4x2DI, TARGET_VECTOR_ELEN_64, VNx2DI, 4, LMUL_RESERVED, 0, LMUL_2, 32, LMUL_1, 64) +TUPLE_ENTRY (VNx5x2DI, TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128, VNx2DI, 5, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 64) +TUPLE_ENTRY (VNx6x2DI, TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128, VNx2DI, 6, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 64) +TUPLE_ENTRY (VNx7x2DI, TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128, VNx2DI, 7, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 64) +TUPLE_ENTRY (VNx8x2DI, TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128, VNx2DI, 8, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 64) +TUPLE_ENTRY (VNx2x1DI, TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128, VNx1DI, 2, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx3x1DI, TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128, VNx1DI, 3, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx4x1DI, TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128, VNx1DI, 4, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx5x1DI, TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128, VNx1DI, 5, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx6x1DI, TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128, VNx1DI, 6, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx7x1DI, TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128, VNx1DI, 7, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx8x1DI, TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128, VNx1DI, 8, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx2x8DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128, VNx8DF, 2, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_4, 16) +TUPLE_ENTRY (VNx2x4DF, TARGET_VECTOR_ELEN_FP_64, VNx4DF, 2, LMUL_RESERVED, 0, LMUL_4, 16, LMUL_2, 32) +TUPLE_ENTRY (VNx3x4DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128, VNx4DF, 3, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 32) +TUPLE_ENTRY (VNx4x4DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128, VNx4DF, 4, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_2, 32) +TUPLE_ENTRY (VNx2x2DF, TARGET_VECTOR_ELEN_FP_64, VNx2DF, 2, LMUL_RESERVED, 0, LMUL_2, 32, LMUL_1, 64) +TUPLE_ENTRY (VNx3x2DF, TARGET_VECTOR_ELEN_FP_64, VNx2DF, 3, LMUL_RESERVED, 0, LMUL_2, 32, LMUL_1, 64) +TUPLE_ENTRY (VNx4x2DF, TARGET_VECTOR_ELEN_FP_64, VNx2DF, 4, LMUL_RESERVED, 0, LMUL_2, 32, LMUL_1, 64) +TUPLE_ENTRY (VNx5x2DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128, VNx2DF, 5, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 64) +TUPLE_ENTRY (VNx6x2DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128, VNx2DF, 6, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 64) +TUPLE_ENTRY (VNx7x2DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128, VNx2DF, 7, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 64) +TUPLE_ENTRY (VNx8x2DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128, VNx2DF, 8, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_1, 64) +TUPLE_ENTRY (VNx2x1DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128, VNx1DF, 2, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx3x1DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128, VNx1DF, 3, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx4x1DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128, VNx1DF, 4, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx5x1DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128, VNx1DF, 5, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx6x1DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128, VNx1DF, 6, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx7x1DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128, VNx1DF, 7, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) +TUPLE_ENTRY (VNx8x1DF, TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN < 128, VNx1DF, 8, LMUL_RESERVED, 0, LMUL_1, 64, LMUL_RESERVED, 0) + #undef ENTRY +#undef TUPLE_ENTRY diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index a0b32a247b6..92fc1e38065 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -992,13 +992,39 @@ riscv_v_ext_vector_mode_p (machine_mode mode) return false; } +/* Return true if mode is the RVV enabled tuple mode. */ + +bool +riscv_v_ext_tuple_mode_p (machine_mode mode) +{ +#define TUPLE_ENTRY(MODE, REQUIREMENT, ...) \ + case MODE##mode: \ + return REQUIREMENT; + switch (mode) + { +#include "riscv-vector-switch.def" + default: + return false; + } + + return false; +} + +/* Return true if it is either RVV vector mode or RVV tuple mode. */ + +static bool +riscv_v_ext_mode_p (machine_mode mode) +{ + return riscv_v_ext_vector_mode_p (mode) || riscv_v_ext_tuple_mode_p (mode); +} + /* Call from ADJUST_NUNITS in riscv-modes.def. Return the correct NUNITS size for corresponding machine_mode. */ poly_int64 riscv_v_adjust_nunits (machine_mode mode, int scale) { - if (riscv_v_ext_vector_mode_p (mode)) + if (riscv_v_ext_mode_p (mode)) return riscv_vector_chunks * scale; return scale; } @@ -1056,7 +1082,7 @@ riscv_classify_address (struct riscv_address_info *info, rtx x, case PLUS: /* RVV load/store disallow any offset. */ - if (riscv_v_ext_vector_mode_p (mode)) + if (riscv_v_ext_mode_p (mode)) return false; info->type = ADDRESS_REG; @@ -1067,7 +1093,7 @@ riscv_classify_address (struct riscv_address_info *info, rtx x, case LO_SUM: /* RVV load/store disallow LO_SUM. */ - if (riscv_v_ext_vector_mode_p (mode)) + if (riscv_v_ext_mode_p (mode)) return false; info->type = ADDRESS_LO_SUM; @@ -1089,7 +1115,7 @@ riscv_classify_address (struct riscv_address_info *info, rtx x, case CONST_INT: /* RVV load/store disallow CONST_INT. */ - if (riscv_v_ext_vector_mode_p (mode)) + if (riscv_v_ext_mode_p (mode)) return false; /* Small-integer addresses don't occur very often, but they @@ -2221,7 +2247,7 @@ riscv_immediate_operand_p (int code, HOST_WIDE_INT x) static int riscv_binary_cost (rtx x, int single_insns, int double_insns) { - if (!riscv_v_ext_vector_mode_p (GET_MODE (x)) + if (!riscv_v_ext_mode_p (GET_MODE (x)) && GET_MODE_SIZE (GET_MODE (x)).to_constant () == UNITS_PER_WORD * 2) return COSTS_N_INSNS (double_insns); return COSTS_N_INSNS (single_insns); @@ -2271,7 +2297,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN { /* TODO: We set RVV instruction cost as 1 by default. Cost Model need to be well analyzed and supported in the future. */ - if (riscv_v_ext_vector_mode_p (mode)) + if (riscv_v_ext_mode_p (mode)) { *total = COSTS_N_INSNS (1); return true; @@ -5885,7 +5911,7 @@ static bool riscv_secondary_memory_needed (machine_mode mode, reg_class_t class1, reg_class_t class2) { - return (!riscv_v_ext_vector_mode_p (mode) + return (!riscv_v_ext_mode_p (mode) && GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD && (class1 == FP_REGS) != (class2 == FP_REGS) && !TARGET_XTHEADFMV); @@ -5919,6 +5945,22 @@ riscv_hard_regno_nregs (unsigned int regno, machine_mode mode) return exact_div (GET_MODE_SIZE (mode), UNITS_PER_V_REG).to_constant (); } + /* For tuple modes, the number of register = NF * LMUL. */ + if (riscv_v_ext_tuple_mode_p (mode)) + { + unsigned int nf = riscv_vector::get_nf (mode); + machine_mode subpart_mode = riscv_vector::get_subpart_mode (mode); + poly_int64 size = GET_MODE_SIZE (subpart_mode); + gcc_assert (known_eq (size * nf, GET_MODE_SIZE (mode))); + if (maybe_lt (size, UNITS_PER_V_REG)) + return nf; + else + { + unsigned int lmul = exact_div (size, UNITS_PER_V_REG).to_constant (); + return nf * lmul; + } + } + /* mode for VL or VTYPE are just a marker, not holding value, so it always consume one register. */ if (regno == VTYPE_REGNUM || regno == VL_REGNUM) @@ -5944,7 +5986,7 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) if (GP_REG_P (regno)) { - if (riscv_v_ext_vector_mode_p (mode)) + if (riscv_v_ext_mode_p (mode)) return false; if (!GP_REG_P (regno + nregs - 1)) @@ -5952,7 +5994,7 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) } else if (FP_REG_P (regno)) { - if (riscv_v_ext_vector_mode_p (mode)) + if (riscv_v_ext_mode_p (mode)) return false; if (!FP_REG_P (regno + nregs - 1)) @@ -5971,7 +6013,7 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) } else if (V_REG_P (regno)) { - if (!riscv_v_ext_vector_mode_p (mode)) + if (!riscv_v_ext_mode_p (mode)) return false; if (!V_REG_P (regno + nregs - 1)) @@ -5980,8 +6022,12 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) /* 3.3.2. LMUL = 2,4,8, register numbers should be multiple of 2,4,8. but for mask vector register, register numbers can be any number. */ int lmul = 1; - if (known_gt (GET_MODE_SIZE (mode), UNITS_PER_V_REG)) - lmul = exact_div (GET_MODE_SIZE (mode), UNITS_PER_V_REG).to_constant (); + machine_mode rvv_mode = mode; + if (riscv_v_ext_tuple_mode_p (rvv_mode)) + rvv_mode = riscv_vector::get_subpart_mode (rvv_mode); + poly_int64 size = GET_MODE_SIZE (rvv_mode); + if (known_gt (size, UNITS_PER_V_REG)) + lmul = exact_div (size, UNITS_PER_V_REG).to_constant (); if (lmul != 1) return ((regno % lmul) == 0); } @@ -7004,7 +7050,7 @@ static bool riscv_vector_mode_supported_p (machine_mode mode) { if (TARGET_VECTOR) - return riscv_v_ext_vector_mode_p (mode); + return riscv_v_ext_mode_p (mode); return false; } @@ -7147,6 +7193,19 @@ riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) & ~zeroed_hardregs); } +/* Implement target hook TARGET_ARRAY_MODE. */ + +static opt_machine_mode +riscv_array_mode (machine_mode mode, unsigned HOST_WIDE_INT nelems) +{ + machine_mode vmode; + if (TARGET_VECTOR + && riscv_vector::get_tuple_mode (mode, nelems).exists (&vmode)) + return vmode; + + return opt_machine_mode (); +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" @@ -7401,6 +7460,9 @@ riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) #undef TARGET_ZERO_CALL_USED_REGS #define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs +#undef TARGET_ARRAY_MODE +#define TARGET_ARRAY_MODE riscv_array_mode + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-riscv.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-10.c new file mode 100644 index 00000000000..62dd7c8663c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-10.c @@ -0,0 +1,204 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc_zve64x -mabi=ilp32d" } */ + +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} +void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} +void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} +void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} +void f___rvv_uint8mf4x3_t () {__rvv_uint8mf4x3_t t;} +void f___rvv_int8mf4x4_t () {__rvv_int8mf4x4_t t;} +void f___rvv_uint8mf4x4_t () {__rvv_uint8mf4x4_t t;} +void f___rvv_int8mf4x5_t () {__rvv_int8mf4x5_t t;} +void f___rvv_uint8mf4x5_t () {__rvv_uint8mf4x5_t t;} +void f___rvv_int8mf4x6_t () {__rvv_int8mf4x6_t t;} +void f___rvv_uint8mf4x6_t () {__rvv_uint8mf4x6_t t;} +void f___rvv_int8mf4x7_t () {__rvv_int8mf4x7_t t;} +void f___rvv_uint8mf4x7_t () {__rvv_uint8mf4x7_t t;} +void f___rvv_int8mf4x8_t () {__rvv_int8mf4x8_t t;} +void f___rvv_uint8mf4x8_t () {__rvv_uint8mf4x8_t t;} +void f___rvv_int8mf2x2_t () {__rvv_int8mf2x2_t t;} +void f___rvv_uint8mf2x2_t () {__rvv_uint8mf2x2_t t;} +void f___rvv_int8mf2x3_t () {__rvv_int8mf2x3_t t;} +void f___rvv_uint8mf2x3_t () {__rvv_uint8mf2x3_t t;} +void f___rvv_int8mf2x4_t () {__rvv_int8mf2x4_t t;} +void f___rvv_uint8mf2x4_t () {__rvv_uint8mf2x4_t t;} +void f___rvv_int8mf2x5_t () {__rvv_int8mf2x5_t t;} +void f___rvv_uint8mf2x5_t () {__rvv_uint8mf2x5_t t;} +void f___rvv_int8mf2x6_t () {__rvv_int8mf2x6_t t;} +void f___rvv_uint8mf2x6_t () {__rvv_uint8mf2x6_t t;} +void f___rvv_int8mf2x7_t () {__rvv_int8mf2x7_t t;} +void f___rvv_uint8mf2x7_t () {__rvv_uint8mf2x7_t t;} +void f___rvv_int8mf2x8_t () {__rvv_int8mf2x8_t t;} +void f___rvv_uint8mf2x8_t () {__rvv_uint8mf2x8_t t;} +void f___rvv_int8m1x2_t () {__rvv_int8m1x2_t t;} +void f___rvv_uint8m1x2_t () {__rvv_uint8m1x2_t t;} +void f___rvv_int8m1x3_t () {__rvv_int8m1x3_t t;} +void f___rvv_uint8m1x3_t () {__rvv_uint8m1x3_t t;} +void f___rvv_int8m1x4_t () {__rvv_int8m1x4_t t;} +void f___rvv_uint8m1x4_t () {__rvv_uint8m1x4_t t;} +void f___rvv_int8m1x5_t () {__rvv_int8m1x5_t t;} +void f___rvv_uint8m1x5_t () {__rvv_uint8m1x5_t t;} +void f___rvv_int8m1x6_t () {__rvv_int8m1x6_t t;} +void f___rvv_uint8m1x6_t () {__rvv_uint8m1x6_t t;} +void f___rvv_int8m1x7_t () {__rvv_int8m1x7_t t;} +void f___rvv_uint8m1x7_t () {__rvv_uint8m1x7_t t;} +void f___rvv_int8m1x8_t () {__rvv_int8m1x8_t t;} +void f___rvv_uint8m1x8_t () {__rvv_uint8m1x8_t t;} +void f___rvv_int8m2x2_t () {__rvv_int8m2x2_t t;} +void f___rvv_uint8m2x2_t () {__rvv_uint8m2x2_t t;} +void f___rvv_int8m2x3_t () {__rvv_int8m2x3_t t;} +void f___rvv_uint8m2x3_t () {__rvv_uint8m2x3_t t;} +void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} +void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} +void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} +void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} +void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} +void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} +void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} +void f___rvv_uint16mf2x3_t () {__rvv_uint16mf2x3_t t;} +void f___rvv_int16mf2x4_t () {__rvv_int16mf2x4_t t;} +void f___rvv_uint16mf2x4_t () {__rvv_uint16mf2x4_t t;} +void f___rvv_int16mf2x5_t () {__rvv_int16mf2x5_t t;} +void f___rvv_uint16mf2x5_t () {__rvv_uint16mf2x5_t t;} +void f___rvv_int16mf2x6_t () {__rvv_int16mf2x6_t t;} +void f___rvv_uint16mf2x6_t () {__rvv_uint16mf2x6_t t;} +void f___rvv_int16mf2x7_t () {__rvv_int16mf2x7_t t;} +void f___rvv_uint16mf2x7_t () {__rvv_uint16mf2x7_t t;} +void f___rvv_int16mf2x8_t () {__rvv_int16mf2x8_t t;} +void f___rvv_uint16mf2x8_t () {__rvv_uint16mf2x8_t t;} +void f___rvv_int16m1x2_t () {__rvv_int16m1x2_t t;} +void f___rvv_uint16m1x2_t () {__rvv_uint16m1x2_t t;} +void f___rvv_int16m1x3_t () {__rvv_int16m1x3_t t;} +void f___rvv_uint16m1x3_t () {__rvv_uint16m1x3_t t;} +void f___rvv_int16m1x4_t () {__rvv_int16m1x4_t t;} +void f___rvv_uint16m1x4_t () {__rvv_uint16m1x4_t t;} +void f___rvv_int16m1x5_t () {__rvv_int16m1x5_t t;} +void f___rvv_uint16m1x5_t () {__rvv_uint16m1x5_t t;} +void f___rvv_int16m1x6_t () {__rvv_int16m1x6_t t;} +void f___rvv_uint16m1x6_t () {__rvv_uint16m1x6_t t;} +void f___rvv_int16m1x7_t () {__rvv_int16m1x7_t t;} +void f___rvv_uint16m1x7_t () {__rvv_uint16m1x7_t t;} +void f___rvv_int16m1x8_t () {__rvv_int16m1x8_t t;} +void f___rvv_uint16m1x8_t () {__rvv_uint16m1x8_t t;} +void f___rvv_int16m2x2_t () {__rvv_int16m2x2_t t;} +void f___rvv_uint16m2x2_t () {__rvv_uint16m2x2_t t;} +void f___rvv_int16m2x3_t () {__rvv_int16m2x3_t t;} +void f___rvv_uint16m2x3_t () {__rvv_uint16m2x3_t t;} +void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} +void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} +void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} +void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} +void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} +void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} +void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} +void f___rvv_uint32m1x3_t () {__rvv_uint32m1x3_t t;} +void f___rvv_int32m1x4_t () {__rvv_int32m1x4_t t;} +void f___rvv_uint32m1x4_t () {__rvv_uint32m1x4_t t;} +void f___rvv_int32m1x5_t () {__rvv_int32m1x5_t t;} +void f___rvv_uint32m1x5_t () {__rvv_uint32m1x5_t t;} +void f___rvv_int32m1x6_t () {__rvv_int32m1x6_t t;} +void f___rvv_uint32m1x6_t () {__rvv_uint32m1x6_t t;} +void f___rvv_int32m1x7_t () {__rvv_int32m1x7_t t;} +void f___rvv_uint32m1x7_t () {__rvv_uint32m1x7_t t;} +void f___rvv_int32m1x8_t () {__rvv_int32m1x8_t t;} +void f___rvv_uint32m1x8_t () {__rvv_uint32m1x8_t t;} +void f___rvv_int32m2x2_t () {__rvv_int32m2x2_t t;} +void f___rvv_uint32m2x2_t () {__rvv_uint32m2x2_t t;} +void f___rvv_int32m2x3_t () {__rvv_int32m2x3_t t;} +void f___rvv_uint32m2x3_t () {__rvv_uint32m2x3_t t;} +void f___rvv_int32m2x4_t () {__rvv_int32m2x4_t t;} +void f___rvv_uint32m2x4_t () {__rvv_uint32m2x4_t t;} +void f___rvv_int32m4x2_t () {__rvv_int32m4x2_t t;} +void f___rvv_uint32m4x2_t () {__rvv_uint32m4x2_t t;} +void f___rvv_int64m1x2_t () {__rvv_int64m1x2_t t;} +void f___rvv_uint64m1x2_t () {__rvv_uint64m1x2_t t;} +void f___rvv_int64m1x3_t () {__rvv_int64m1x3_t t;} +void f___rvv_uint64m1x3_t () {__rvv_uint64m1x3_t t;} +void f___rvv_int64m1x4_t () {__rvv_int64m1x4_t t;} +void f___rvv_uint64m1x4_t () {__rvv_uint64m1x4_t t;} +void f___rvv_int64m1x5_t () {__rvv_int64m1x5_t t;} +void f___rvv_uint64m1x5_t () {__rvv_uint64m1x5_t t;} +void f___rvv_int64m1x6_t () {__rvv_int64m1x6_t t;} +void f___rvv_uint64m1x6_t () {__rvv_uint64m1x6_t t;} +void f___rvv_int64m1x7_t () {__rvv_int64m1x7_t t;} +void f___rvv_uint64m1x7_t () {__rvv_uint64m1x7_t t;} +void f___rvv_int64m1x8_t () {__rvv_int64m1x8_t t;} +void f___rvv_uint64m1x8_t () {__rvv_uint64m1x8_t t;} +void f___rvv_int64m2x2_t () {__rvv_int64m2x2_t t;} +void f___rvv_uint64m2x2_t () {__rvv_uint64m2x2_t t;} +void f___rvv_int64m2x3_t () {__rvv_int64m2x3_t t;} +void f___rvv_uint64m2x3_t () {__rvv_uint64m2x3_t t;} +void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} +void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} +void f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} +void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} +void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x2_t'} } */ +void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x3_t'} } */ +void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x4_t'} } */ +void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x5_t'} } */ +void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x6_t'} } */ +void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x7_t'} } */ +void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x8_t'} } */ +void f___rvv_float32m1x2_t () {__rvv_float32m1x2_t t;} /* { dg-error {unknown type name '__rvv_float32m1x2_t'} } */ +void f___rvv_float32m1x3_t () {__rvv_float32m1x3_t t;} /* { dg-error {unknown type name '__rvv_float32m1x3_t'} } */ +void f___rvv_float32m1x4_t () {__rvv_float32m1x4_t t;} /* { dg-error {unknown type name '__rvv_float32m1x4_t'} } */ +void f___rvv_float32m1x5_t () {__rvv_float32m1x5_t t;} /* { dg-error {unknown type name '__rvv_float32m1x5_t'} } */ +void f___rvv_float32m1x6_t () {__rvv_float32m1x6_t t;} /* { dg-error {unknown type name '__rvv_float32m1x6_t'} } */ +void f___rvv_float32m1x7_t () {__rvv_float32m1x7_t t;} /* { dg-error {unknown type name '__rvv_float32m1x7_t'} } */ +void f___rvv_float32m1x8_t () {__rvv_float32m1x8_t t;} /* { dg-error {unknown type name '__rvv_float32m1x8_t'} } */ +void f___rvv_float32m2x2_t () {__rvv_float32m2x2_t t;} /* { dg-error {unknown type name '__rvv_float32m2x2_t'} } */ +void f___rvv_float32m2x3_t () {__rvv_float32m2x3_t t;} /* { dg-error {unknown type name '__rvv_float32m2x3_t'} } */ +void f___rvv_float32m2x4_t () {__rvv_float32m2x4_t t;} /* { dg-error {unknown type name '__rvv_float32m2x4_t'} } */ +void f___rvv_float32m4x2_t () {__rvv_float32m4x2_t t;} /* { dg-error {unknown type name '__rvv_float32m4x2_t'} } */ +void f___rvv_float64m1x2_t () {__rvv_float64m1x2_t t;} /* { dg-error {unknown type name '__rvv_float64m1x2_t'} } */ +void f___rvv_float64m1x3_t () {__rvv_float64m1x3_t t;} /* { dg-error {unknown type name '__rvv_float64m1x3_t'} } */ +void f___rvv_float64m1x4_t () {__rvv_float64m1x4_t t;} /* { dg-error {unknown type name '__rvv_float64m1x4_t'} } */ +void f___rvv_float64m1x5_t () {__rvv_float64m1x5_t t;} /* { dg-error {unknown type name '__rvv_float64m1x5_t'} } */ +void f___rvv_float64m1x6_t () {__rvv_float64m1x6_t t;} /* { dg-error {unknown type name '__rvv_float64m1x6_t'} } */ +void f___rvv_float64m1x7_t () {__rvv_float64m1x7_t t;} /* { dg-error {unknown type name '__rvv_float64m1x7_t'} } */ +void f___rvv_float64m1x8_t () {__rvv_float64m1x8_t t;} /* { dg-error {unknown type name '__rvv_float64m1x8_t'} } */ +void f___rvv_float64m2x2_t () {__rvv_float64m2x2_t t;} /* { dg-error {unknown type name '__rvv_float64m2x2_t'} } */ +void f___rvv_float64m2x3_t () {__rvv_float64m2x3_t t;} /* { dg-error {unknown type name '__rvv_float64m2x3_t'} } */ +void f___rvv_float64m2x4_t () {__rvv_float64m2x4_t t;} /* { dg-error {unknown type name '__rvv_float64m2x4_t'} } */ +void f___rvv_float64m4x2_t () {__rvv_float64m4x2_t t;} /* { dg-error {unknown type name '__rvv_float64m4x2_t'} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-11.c new file mode 100644 index 00000000000..a524b415880 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-11.c @@ -0,0 +1,204 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc_zve64f -mabi=ilp32d" } */ + +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} +void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} +void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} +void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} +void f___rvv_uint8mf4x3_t () {__rvv_uint8mf4x3_t t;} +void f___rvv_int8mf4x4_t () {__rvv_int8mf4x4_t t;} +void f___rvv_uint8mf4x4_t () {__rvv_uint8mf4x4_t t;} +void f___rvv_int8mf4x5_t () {__rvv_int8mf4x5_t t;} +void f___rvv_uint8mf4x5_t () {__rvv_uint8mf4x5_t t;} +void f___rvv_int8mf4x6_t () {__rvv_int8mf4x6_t t;} +void f___rvv_uint8mf4x6_t () {__rvv_uint8mf4x6_t t;} +void f___rvv_int8mf4x7_t () {__rvv_int8mf4x7_t t;} +void f___rvv_uint8mf4x7_t () {__rvv_uint8mf4x7_t t;} +void f___rvv_int8mf4x8_t () {__rvv_int8mf4x8_t t;} +void f___rvv_uint8mf4x8_t () {__rvv_uint8mf4x8_t t;} +void f___rvv_int8mf2x2_t () {__rvv_int8mf2x2_t t;} +void f___rvv_uint8mf2x2_t () {__rvv_uint8mf2x2_t t;} +void f___rvv_int8mf2x3_t () {__rvv_int8mf2x3_t t;} +void f___rvv_uint8mf2x3_t () {__rvv_uint8mf2x3_t t;} +void f___rvv_int8mf2x4_t () {__rvv_int8mf2x4_t t;} +void f___rvv_uint8mf2x4_t () {__rvv_uint8mf2x4_t t;} +void f___rvv_int8mf2x5_t () {__rvv_int8mf2x5_t t;} +void f___rvv_uint8mf2x5_t () {__rvv_uint8mf2x5_t t;} +void f___rvv_int8mf2x6_t () {__rvv_int8mf2x6_t t;} +void f___rvv_uint8mf2x6_t () {__rvv_uint8mf2x6_t t;} +void f___rvv_int8mf2x7_t () {__rvv_int8mf2x7_t t;} +void f___rvv_uint8mf2x7_t () {__rvv_uint8mf2x7_t t;} +void f___rvv_int8mf2x8_t () {__rvv_int8mf2x8_t t;} +void f___rvv_uint8mf2x8_t () {__rvv_uint8mf2x8_t t;} +void f___rvv_int8m1x2_t () {__rvv_int8m1x2_t t;} +void f___rvv_uint8m1x2_t () {__rvv_uint8m1x2_t t;} +void f___rvv_int8m1x3_t () {__rvv_int8m1x3_t t;} +void f___rvv_uint8m1x3_t () {__rvv_uint8m1x3_t t;} +void f___rvv_int8m1x4_t () {__rvv_int8m1x4_t t;} +void f___rvv_uint8m1x4_t () {__rvv_uint8m1x4_t t;} +void f___rvv_int8m1x5_t () {__rvv_int8m1x5_t t;} +void f___rvv_uint8m1x5_t () {__rvv_uint8m1x5_t t;} +void f___rvv_int8m1x6_t () {__rvv_int8m1x6_t t;} +void f___rvv_uint8m1x6_t () {__rvv_uint8m1x6_t t;} +void f___rvv_int8m1x7_t () {__rvv_int8m1x7_t t;} +void f___rvv_uint8m1x7_t () {__rvv_uint8m1x7_t t;} +void f___rvv_int8m1x8_t () {__rvv_int8m1x8_t t;} +void f___rvv_uint8m1x8_t () {__rvv_uint8m1x8_t t;} +void f___rvv_int8m2x2_t () {__rvv_int8m2x2_t t;} +void f___rvv_uint8m2x2_t () {__rvv_uint8m2x2_t t;} +void f___rvv_int8m2x3_t () {__rvv_int8m2x3_t t;} +void f___rvv_uint8m2x3_t () {__rvv_uint8m2x3_t t;} +void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} +void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} +void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} +void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} +void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} +void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} +void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} +void f___rvv_uint16mf2x3_t () {__rvv_uint16mf2x3_t t;} +void f___rvv_int16mf2x4_t () {__rvv_int16mf2x4_t t;} +void f___rvv_uint16mf2x4_t () {__rvv_uint16mf2x4_t t;} +void f___rvv_int16mf2x5_t () {__rvv_int16mf2x5_t t;} +void f___rvv_uint16mf2x5_t () {__rvv_uint16mf2x5_t t;} +void f___rvv_int16mf2x6_t () {__rvv_int16mf2x6_t t;} +void f___rvv_uint16mf2x6_t () {__rvv_uint16mf2x6_t t;} +void f___rvv_int16mf2x7_t () {__rvv_int16mf2x7_t t;} +void f___rvv_uint16mf2x7_t () {__rvv_uint16mf2x7_t t;} +void f___rvv_int16mf2x8_t () {__rvv_int16mf2x8_t t;} +void f___rvv_uint16mf2x8_t () {__rvv_uint16mf2x8_t t;} +void f___rvv_int16m1x2_t () {__rvv_int16m1x2_t t;} +void f___rvv_uint16m1x2_t () {__rvv_uint16m1x2_t t;} +void f___rvv_int16m1x3_t () {__rvv_int16m1x3_t t;} +void f___rvv_uint16m1x3_t () {__rvv_uint16m1x3_t t;} +void f___rvv_int16m1x4_t () {__rvv_int16m1x4_t t;} +void f___rvv_uint16m1x4_t () {__rvv_uint16m1x4_t t;} +void f___rvv_int16m1x5_t () {__rvv_int16m1x5_t t;} +void f___rvv_uint16m1x5_t () {__rvv_uint16m1x5_t t;} +void f___rvv_int16m1x6_t () {__rvv_int16m1x6_t t;} +void f___rvv_uint16m1x6_t () {__rvv_uint16m1x6_t t;} +void f___rvv_int16m1x7_t () {__rvv_int16m1x7_t t;} +void f___rvv_uint16m1x7_t () {__rvv_uint16m1x7_t t;} +void f___rvv_int16m1x8_t () {__rvv_int16m1x8_t t;} +void f___rvv_uint16m1x8_t () {__rvv_uint16m1x8_t t;} +void f___rvv_int16m2x2_t () {__rvv_int16m2x2_t t;} +void f___rvv_uint16m2x2_t () {__rvv_uint16m2x2_t t;} +void f___rvv_int16m2x3_t () {__rvv_int16m2x3_t t;} +void f___rvv_uint16m2x3_t () {__rvv_uint16m2x3_t t;} +void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} +void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} +void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} +void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} +void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} +void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} +void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} +void f___rvv_uint32m1x3_t () {__rvv_uint32m1x3_t t;} +void f___rvv_int32m1x4_t () {__rvv_int32m1x4_t t;} +void f___rvv_uint32m1x4_t () {__rvv_uint32m1x4_t t;} +void f___rvv_int32m1x5_t () {__rvv_int32m1x5_t t;} +void f___rvv_uint32m1x5_t () {__rvv_uint32m1x5_t t;} +void f___rvv_int32m1x6_t () {__rvv_int32m1x6_t t;} +void f___rvv_uint32m1x6_t () {__rvv_uint32m1x6_t t;} +void f___rvv_int32m1x7_t () {__rvv_int32m1x7_t t;} +void f___rvv_uint32m1x7_t () {__rvv_uint32m1x7_t t;} +void f___rvv_int32m1x8_t () {__rvv_int32m1x8_t t;} +void f___rvv_uint32m1x8_t () {__rvv_uint32m1x8_t t;} +void f___rvv_int32m2x2_t () {__rvv_int32m2x2_t t;} +void f___rvv_uint32m2x2_t () {__rvv_uint32m2x2_t t;} +void f___rvv_int32m2x3_t () {__rvv_int32m2x3_t t;} +void f___rvv_uint32m2x3_t () {__rvv_uint32m2x3_t t;} +void f___rvv_int32m2x4_t () {__rvv_int32m2x4_t t;} +void f___rvv_uint32m2x4_t () {__rvv_uint32m2x4_t t;} +void f___rvv_int32m4x2_t () {__rvv_int32m4x2_t t;} +void f___rvv_uint32m4x2_t () {__rvv_uint32m4x2_t t;} +void f___rvv_int64m1x2_t () {__rvv_int64m1x2_t t;} +void f___rvv_uint64m1x2_t () {__rvv_uint64m1x2_t t;} +void f___rvv_int64m1x3_t () {__rvv_int64m1x3_t t;} +void f___rvv_uint64m1x3_t () {__rvv_uint64m1x3_t t;} +void f___rvv_int64m1x4_t () {__rvv_int64m1x4_t t;} +void f___rvv_uint64m1x4_t () {__rvv_uint64m1x4_t t;} +void f___rvv_int64m1x5_t () {__rvv_int64m1x5_t t;} +void f___rvv_uint64m1x5_t () {__rvv_uint64m1x5_t t;} +void f___rvv_int64m1x6_t () {__rvv_int64m1x6_t t;} +void f___rvv_uint64m1x6_t () {__rvv_uint64m1x6_t t;} +void f___rvv_int64m1x7_t () {__rvv_int64m1x7_t t;} +void f___rvv_uint64m1x7_t () {__rvv_uint64m1x7_t t;} +void f___rvv_int64m1x8_t () {__rvv_int64m1x8_t t;} +void f___rvv_uint64m1x8_t () {__rvv_uint64m1x8_t t;} +void f___rvv_int64m2x2_t () {__rvv_int64m2x2_t t;} +void f___rvv_uint64m2x2_t () {__rvv_uint64m2x2_t t;} +void f___rvv_int64m2x3_t () {__rvv_int64m2x3_t t;} +void f___rvv_uint64m2x3_t () {__rvv_uint64m2x3_t t;} +void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} +void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} +void f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} +void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} +void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} +void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} +void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} +void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} +void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} +void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} +void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} +void f___rvv_float32m1x2_t () {__rvv_float32m1x2_t t;} +void f___rvv_float32m1x3_t () {__rvv_float32m1x3_t t;} +void f___rvv_float32m1x4_t () {__rvv_float32m1x4_t t;} +void f___rvv_float32m1x5_t () {__rvv_float32m1x5_t t;} +void f___rvv_float32m1x6_t () {__rvv_float32m1x6_t t;} +void f___rvv_float32m1x7_t () {__rvv_float32m1x7_t t;} +void f___rvv_float32m1x8_t () {__rvv_float32m1x8_t t;} +void f___rvv_float32m2x2_t () {__rvv_float32m2x2_t t;} +void f___rvv_float32m2x3_t () {__rvv_float32m2x3_t t;} +void f___rvv_float32m2x4_t () {__rvv_float32m2x4_t t;} +void f___rvv_float32m4x2_t () {__rvv_float32m4x2_t t;} +void f___rvv_float64m1x2_t () {__rvv_float64m1x2_t t;} /* { dg-error {unknown type name '__rvv_float64m1x2_t'} } */ +void f___rvv_float64m1x3_t () {__rvv_float64m1x3_t t;} /* { dg-error {unknown type name '__rvv_float64m1x3_t'} } */ +void f___rvv_float64m1x4_t () {__rvv_float64m1x4_t t;} /* { dg-error {unknown type name '__rvv_float64m1x4_t'} } */ +void f___rvv_float64m1x5_t () {__rvv_float64m1x5_t t;} /* { dg-error {unknown type name '__rvv_float64m1x5_t'} } */ +void f___rvv_float64m1x6_t () {__rvv_float64m1x6_t t;} /* { dg-error {unknown type name '__rvv_float64m1x6_t'} } */ +void f___rvv_float64m1x7_t () {__rvv_float64m1x7_t t;} /* { dg-error {unknown type name '__rvv_float64m1x7_t'} } */ +void f___rvv_float64m1x8_t () {__rvv_float64m1x8_t t;} /* { dg-error {unknown type name '__rvv_float64m1x8_t'} } */ +void f___rvv_float64m2x2_t () {__rvv_float64m2x2_t t;} /* { dg-error {unknown type name '__rvv_float64m2x2_t'} } */ +void f___rvv_float64m2x3_t () {__rvv_float64m2x3_t t;} /* { dg-error {unknown type name '__rvv_float64m2x3_t'} } */ +void f___rvv_float64m2x4_t () {__rvv_float64m2x4_t t;} /* { dg-error {unknown type name '__rvv_float64m2x4_t'} } */ +void f___rvv_float64m4x2_t () {__rvv_float64m4x2_t t;} /* { dg-error {unknown type name '__rvv_float64m4x2_t'} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-12.c new file mode 100644 index 00000000000..925aa9eccc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-12.c @@ -0,0 +1,204 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc_zve64d -mabi=ilp32d" } */ + +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} +void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} +void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} +void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} +void f___rvv_uint8mf4x3_t () {__rvv_uint8mf4x3_t t;} +void f___rvv_int8mf4x4_t () {__rvv_int8mf4x4_t t;} +void f___rvv_uint8mf4x4_t () {__rvv_uint8mf4x4_t t;} +void f___rvv_int8mf4x5_t () {__rvv_int8mf4x5_t t;} +void f___rvv_uint8mf4x5_t () {__rvv_uint8mf4x5_t t;} +void f___rvv_int8mf4x6_t () {__rvv_int8mf4x6_t t;} +void f___rvv_uint8mf4x6_t () {__rvv_uint8mf4x6_t t;} +void f___rvv_int8mf4x7_t () {__rvv_int8mf4x7_t t;} +void f___rvv_uint8mf4x7_t () {__rvv_uint8mf4x7_t t;} +void f___rvv_int8mf4x8_t () {__rvv_int8mf4x8_t t;} +void f___rvv_uint8mf4x8_t () {__rvv_uint8mf4x8_t t;} +void f___rvv_int8mf2x2_t () {__rvv_int8mf2x2_t t;} +void f___rvv_uint8mf2x2_t () {__rvv_uint8mf2x2_t t;} +void f___rvv_int8mf2x3_t () {__rvv_int8mf2x3_t t;} +void f___rvv_uint8mf2x3_t () {__rvv_uint8mf2x3_t t;} +void f___rvv_int8mf2x4_t () {__rvv_int8mf2x4_t t;} +void f___rvv_uint8mf2x4_t () {__rvv_uint8mf2x4_t t;} +void f___rvv_int8mf2x5_t () {__rvv_int8mf2x5_t t;} +void f___rvv_uint8mf2x5_t () {__rvv_uint8mf2x5_t t;} +void f___rvv_int8mf2x6_t () {__rvv_int8mf2x6_t t;} +void f___rvv_uint8mf2x6_t () {__rvv_uint8mf2x6_t t;} +void f___rvv_int8mf2x7_t () {__rvv_int8mf2x7_t t;} +void f___rvv_uint8mf2x7_t () {__rvv_uint8mf2x7_t t;} +void f___rvv_int8mf2x8_t () {__rvv_int8mf2x8_t t;} +void f___rvv_uint8mf2x8_t () {__rvv_uint8mf2x8_t t;} +void f___rvv_int8m1x2_t () {__rvv_int8m1x2_t t;} +void f___rvv_uint8m1x2_t () {__rvv_uint8m1x2_t t;} +void f___rvv_int8m1x3_t () {__rvv_int8m1x3_t t;} +void f___rvv_uint8m1x3_t () {__rvv_uint8m1x3_t t;} +void f___rvv_int8m1x4_t () {__rvv_int8m1x4_t t;} +void f___rvv_uint8m1x4_t () {__rvv_uint8m1x4_t t;} +void f___rvv_int8m1x5_t () {__rvv_int8m1x5_t t;} +void f___rvv_uint8m1x5_t () {__rvv_uint8m1x5_t t;} +void f___rvv_int8m1x6_t () {__rvv_int8m1x6_t t;} +void f___rvv_uint8m1x6_t () {__rvv_uint8m1x6_t t;} +void f___rvv_int8m1x7_t () {__rvv_int8m1x7_t t;} +void f___rvv_uint8m1x7_t () {__rvv_uint8m1x7_t t;} +void f___rvv_int8m1x8_t () {__rvv_int8m1x8_t t;} +void f___rvv_uint8m1x8_t () {__rvv_uint8m1x8_t t;} +void f___rvv_int8m2x2_t () {__rvv_int8m2x2_t t;} +void f___rvv_uint8m2x2_t () {__rvv_uint8m2x2_t t;} +void f___rvv_int8m2x3_t () {__rvv_int8m2x3_t t;} +void f___rvv_uint8m2x3_t () {__rvv_uint8m2x3_t t;} +void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} +void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} +void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} +void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} +void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} +void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} +void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} +void f___rvv_uint16mf2x3_t () {__rvv_uint16mf2x3_t t;} +void f___rvv_int16mf2x4_t () {__rvv_int16mf2x4_t t;} +void f___rvv_uint16mf2x4_t () {__rvv_uint16mf2x4_t t;} +void f___rvv_int16mf2x5_t () {__rvv_int16mf2x5_t t;} +void f___rvv_uint16mf2x5_t () {__rvv_uint16mf2x5_t t;} +void f___rvv_int16mf2x6_t () {__rvv_int16mf2x6_t t;} +void f___rvv_uint16mf2x6_t () {__rvv_uint16mf2x6_t t;} +void f___rvv_int16mf2x7_t () {__rvv_int16mf2x7_t t;} +void f___rvv_uint16mf2x7_t () {__rvv_uint16mf2x7_t t;} +void f___rvv_int16mf2x8_t () {__rvv_int16mf2x8_t t;} +void f___rvv_uint16mf2x8_t () {__rvv_uint16mf2x8_t t;} +void f___rvv_int16m1x2_t () {__rvv_int16m1x2_t t;} +void f___rvv_uint16m1x2_t () {__rvv_uint16m1x2_t t;} +void f___rvv_int16m1x3_t () {__rvv_int16m1x3_t t;} +void f___rvv_uint16m1x3_t () {__rvv_uint16m1x3_t t;} +void f___rvv_int16m1x4_t () {__rvv_int16m1x4_t t;} +void f___rvv_uint16m1x4_t () {__rvv_uint16m1x4_t t;} +void f___rvv_int16m1x5_t () {__rvv_int16m1x5_t t;} +void f___rvv_uint16m1x5_t () {__rvv_uint16m1x5_t t;} +void f___rvv_int16m1x6_t () {__rvv_int16m1x6_t t;} +void f___rvv_uint16m1x6_t () {__rvv_uint16m1x6_t t;} +void f___rvv_int16m1x7_t () {__rvv_int16m1x7_t t;} +void f___rvv_uint16m1x7_t () {__rvv_uint16m1x7_t t;} +void f___rvv_int16m1x8_t () {__rvv_int16m1x8_t t;} +void f___rvv_uint16m1x8_t () {__rvv_uint16m1x8_t t;} +void f___rvv_int16m2x2_t () {__rvv_int16m2x2_t t;} +void f___rvv_uint16m2x2_t () {__rvv_uint16m2x2_t t;} +void f___rvv_int16m2x3_t () {__rvv_int16m2x3_t t;} +void f___rvv_uint16m2x3_t () {__rvv_uint16m2x3_t t;} +void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} +void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} +void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} +void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} +void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} +void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} +void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} +void f___rvv_uint32m1x3_t () {__rvv_uint32m1x3_t t;} +void f___rvv_int32m1x4_t () {__rvv_int32m1x4_t t;} +void f___rvv_uint32m1x4_t () {__rvv_uint32m1x4_t t;} +void f___rvv_int32m1x5_t () {__rvv_int32m1x5_t t;} +void f___rvv_uint32m1x5_t () {__rvv_uint32m1x5_t t;} +void f___rvv_int32m1x6_t () {__rvv_int32m1x6_t t;} +void f___rvv_uint32m1x6_t () {__rvv_uint32m1x6_t t;} +void f___rvv_int32m1x7_t () {__rvv_int32m1x7_t t;} +void f___rvv_uint32m1x7_t () {__rvv_uint32m1x7_t t;} +void f___rvv_int32m1x8_t () {__rvv_int32m1x8_t t;} +void f___rvv_uint32m1x8_t () {__rvv_uint32m1x8_t t;} +void f___rvv_int32m2x2_t () {__rvv_int32m2x2_t t;} +void f___rvv_uint32m2x2_t () {__rvv_uint32m2x2_t t;} +void f___rvv_int32m2x3_t () {__rvv_int32m2x3_t t;} +void f___rvv_uint32m2x3_t () {__rvv_uint32m2x3_t t;} +void f___rvv_int32m2x4_t () {__rvv_int32m2x4_t t;} +void f___rvv_uint32m2x4_t () {__rvv_uint32m2x4_t t;} +void f___rvv_int32m4x2_t () {__rvv_int32m4x2_t t;} +void f___rvv_uint32m4x2_t () {__rvv_uint32m4x2_t t;} +void f___rvv_int64m1x2_t () {__rvv_int64m1x2_t t;} +void f___rvv_uint64m1x2_t () {__rvv_uint64m1x2_t t;} +void f___rvv_int64m1x3_t () {__rvv_int64m1x3_t t;} +void f___rvv_uint64m1x3_t () {__rvv_uint64m1x3_t t;} +void f___rvv_int64m1x4_t () {__rvv_int64m1x4_t t;} +void f___rvv_uint64m1x4_t () {__rvv_uint64m1x4_t t;} +void f___rvv_int64m1x5_t () {__rvv_int64m1x5_t t;} +void f___rvv_uint64m1x5_t () {__rvv_uint64m1x5_t t;} +void f___rvv_int64m1x6_t () {__rvv_int64m1x6_t t;} +void f___rvv_uint64m1x6_t () {__rvv_uint64m1x6_t t;} +void f___rvv_int64m1x7_t () {__rvv_int64m1x7_t t;} +void f___rvv_uint64m1x7_t () {__rvv_uint64m1x7_t t;} +void f___rvv_int64m1x8_t () {__rvv_int64m1x8_t t;} +void f___rvv_uint64m1x8_t () {__rvv_uint64m1x8_t t;} +void f___rvv_int64m2x2_t () {__rvv_int64m2x2_t t;} +void f___rvv_uint64m2x2_t () {__rvv_uint64m2x2_t t;} +void f___rvv_int64m2x3_t () {__rvv_int64m2x3_t t;} +void f___rvv_uint64m2x3_t () {__rvv_uint64m2x3_t t;} +void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} +void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} +void f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} +void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} +void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} +void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} +void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} +void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} +void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} +void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} +void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} +void f___rvv_float32m1x2_t () {__rvv_float32m1x2_t t;} +void f___rvv_float32m1x3_t () {__rvv_float32m1x3_t t;} +void f___rvv_float32m1x4_t () {__rvv_float32m1x4_t t;} +void f___rvv_float32m1x5_t () {__rvv_float32m1x5_t t;} +void f___rvv_float32m1x6_t () {__rvv_float32m1x6_t t;} +void f___rvv_float32m1x7_t () {__rvv_float32m1x7_t t;} +void f___rvv_float32m1x8_t () {__rvv_float32m1x8_t t;} +void f___rvv_float32m2x2_t () {__rvv_float32m2x2_t t;} +void f___rvv_float32m2x3_t () {__rvv_float32m2x3_t t;} +void f___rvv_float32m2x4_t () {__rvv_float32m2x4_t t;} +void f___rvv_float32m4x2_t () {__rvv_float32m4x2_t t;} +void f___rvv_float64m1x2_t () {__rvv_float64m1x2_t t;} +void f___rvv_float64m1x3_t () {__rvv_float64m1x3_t t;} +void f___rvv_float64m1x4_t () {__rvv_float64m1x4_t t;} +void f___rvv_float64m1x5_t () {__rvv_float64m1x5_t t;} +void f___rvv_float64m1x6_t () {__rvv_float64m1x6_t t;} +void f___rvv_float64m1x7_t () {__rvv_float64m1x7_t t;} +void f___rvv_float64m1x8_t () {__rvv_float64m1x8_t t;} +void f___rvv_float64m2x2_t () {__rvv_float64m2x2_t t;} +void f___rvv_float64m2x3_t () {__rvv_float64m2x3_t t;} +void f___rvv_float64m2x4_t () {__rvv_float64m2x4_t t;} +void f___rvv_float64m4x2_t () {__rvv_float64m4x2_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-13.c new file mode 100644 index 00000000000..13940e56358 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-13.c @@ -0,0 +1,204 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc_zve32x -mabi=ilp32d" } */ + +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x2_t'} } */ +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x2_t'} } */ +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x3_t'} } */ +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x3_t'} } */ +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x4_t'} } */ +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x4_t'} } */ +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x5_t'} } */ +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x5_t'} } */ +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x6_t'} } */ +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x6_t'} } */ +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x7_t'} } */ +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x7_t'} } */ +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x8_t'} } */ +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x8_t'} } */ +void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} +void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} +void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} +void f___rvv_uint8mf4x3_t () {__rvv_uint8mf4x3_t t;} +void f___rvv_int8mf4x4_t () {__rvv_int8mf4x4_t t;} +void f___rvv_uint8mf4x4_t () {__rvv_uint8mf4x4_t t;} +void f___rvv_int8mf4x5_t () {__rvv_int8mf4x5_t t;} +void f___rvv_uint8mf4x5_t () {__rvv_uint8mf4x5_t t;} +void f___rvv_int8mf4x6_t () {__rvv_int8mf4x6_t t;} +void f___rvv_uint8mf4x6_t () {__rvv_uint8mf4x6_t t;} +void f___rvv_int8mf4x7_t () {__rvv_int8mf4x7_t t;} +void f___rvv_uint8mf4x7_t () {__rvv_uint8mf4x7_t t;} +void f___rvv_int8mf4x8_t () {__rvv_int8mf4x8_t t;} +void f___rvv_uint8mf4x8_t () {__rvv_uint8mf4x8_t t;} +void f___rvv_int8mf2x2_t () {__rvv_int8mf2x2_t t;} +void f___rvv_uint8mf2x2_t () {__rvv_uint8mf2x2_t t;} +void f___rvv_int8mf2x3_t () {__rvv_int8mf2x3_t t;} +void f___rvv_uint8mf2x3_t () {__rvv_uint8mf2x3_t t;} +void f___rvv_int8mf2x4_t () {__rvv_int8mf2x4_t t;} +void f___rvv_uint8mf2x4_t () {__rvv_uint8mf2x4_t t;} +void f___rvv_int8mf2x5_t () {__rvv_int8mf2x5_t t;} +void f___rvv_uint8mf2x5_t () {__rvv_uint8mf2x5_t t;} +void f___rvv_int8mf2x6_t () {__rvv_int8mf2x6_t t;} +void f___rvv_uint8mf2x6_t () {__rvv_uint8mf2x6_t t;} +void f___rvv_int8mf2x7_t () {__rvv_int8mf2x7_t t;} +void f___rvv_uint8mf2x7_t () {__rvv_uint8mf2x7_t t;} +void f___rvv_int8mf2x8_t () {__rvv_int8mf2x8_t t;} +void f___rvv_uint8mf2x8_t () {__rvv_uint8mf2x8_t t;} +void f___rvv_int8m1x2_t () {__rvv_int8m1x2_t t;} +void f___rvv_uint8m1x2_t () {__rvv_uint8m1x2_t t;} +void f___rvv_int8m1x3_t () {__rvv_int8m1x3_t t;} +void f___rvv_uint8m1x3_t () {__rvv_uint8m1x3_t t;} +void f___rvv_int8m1x4_t () {__rvv_int8m1x4_t t;} +void f___rvv_uint8m1x4_t () {__rvv_uint8m1x4_t t;} +void f___rvv_int8m1x5_t () {__rvv_int8m1x5_t t;} +void f___rvv_uint8m1x5_t () {__rvv_uint8m1x5_t t;} +void f___rvv_int8m1x6_t () {__rvv_int8m1x6_t t;} +void f___rvv_uint8m1x6_t () {__rvv_uint8m1x6_t t;} +void f___rvv_int8m1x7_t () {__rvv_int8m1x7_t t;} +void f___rvv_uint8m1x7_t () {__rvv_uint8m1x7_t t;} +void f___rvv_int8m1x8_t () {__rvv_int8m1x8_t t;} +void f___rvv_uint8m1x8_t () {__rvv_uint8m1x8_t t;} +void f___rvv_int8m2x2_t () {__rvv_int8m2x2_t t;} +void f___rvv_uint8m2x2_t () {__rvv_uint8m2x2_t t;} +void f___rvv_int8m2x3_t () {__rvv_int8m2x3_t t;} +void f___rvv_uint8m2x3_t () {__rvv_uint8m2x3_t t;} +void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} +void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} +void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} +void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x2_t'} } */ +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x2_t'} } */ +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x3_t'} } */ +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x3_t'} } */ +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x4_t'} } */ +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x4_t'} } */ +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x5_t'} } */ +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x5_t'} } */ +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x6_t'} } */ +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x6_t'} } */ +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x7_t'} } */ +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x7_t'} } */ +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x8_t'} } */ +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x8_t'} } */ +void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} +void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} +void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} +void f___rvv_uint16mf2x3_t () {__rvv_uint16mf2x3_t t;} +void f___rvv_int16mf2x4_t () {__rvv_int16mf2x4_t t;} +void f___rvv_uint16mf2x4_t () {__rvv_uint16mf2x4_t t;} +void f___rvv_int16mf2x5_t () {__rvv_int16mf2x5_t t;} +void f___rvv_uint16mf2x5_t () {__rvv_uint16mf2x5_t t;} +void f___rvv_int16mf2x6_t () {__rvv_int16mf2x6_t t;} +void f___rvv_uint16mf2x6_t () {__rvv_uint16mf2x6_t t;} +void f___rvv_int16mf2x7_t () {__rvv_int16mf2x7_t t;} +void f___rvv_uint16mf2x7_t () {__rvv_uint16mf2x7_t t;} +void f___rvv_int16mf2x8_t () {__rvv_int16mf2x8_t t;} +void f___rvv_uint16mf2x8_t () {__rvv_uint16mf2x8_t t;} +void f___rvv_int16m1x2_t () {__rvv_int16m1x2_t t;} +void f___rvv_uint16m1x2_t () {__rvv_uint16m1x2_t t;} +void f___rvv_int16m1x3_t () {__rvv_int16m1x3_t t;} +void f___rvv_uint16m1x3_t () {__rvv_uint16m1x3_t t;} +void f___rvv_int16m1x4_t () {__rvv_int16m1x4_t t;} +void f___rvv_uint16m1x4_t () {__rvv_uint16m1x4_t t;} +void f___rvv_int16m1x5_t () {__rvv_int16m1x5_t t;} +void f___rvv_uint16m1x5_t () {__rvv_uint16m1x5_t t;} +void f___rvv_int16m1x6_t () {__rvv_int16m1x6_t t;} +void f___rvv_uint16m1x6_t () {__rvv_uint16m1x6_t t;} +void f___rvv_int16m1x7_t () {__rvv_int16m1x7_t t;} +void f___rvv_uint16m1x7_t () {__rvv_uint16m1x7_t t;} +void f___rvv_int16m1x8_t () {__rvv_int16m1x8_t t;} +void f___rvv_uint16m1x8_t () {__rvv_uint16m1x8_t t;} +void f___rvv_int16m2x2_t () {__rvv_int16m2x2_t t;} +void f___rvv_uint16m2x2_t () {__rvv_uint16m2x2_t t;} +void f___rvv_int16m2x3_t () {__rvv_int16m2x3_t t;} +void f___rvv_uint16m2x3_t () {__rvv_uint16m2x3_t t;} +void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} +void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} +void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} +void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x2_t'} } */ +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x2_t'} } */ +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x3_t'} } */ +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x3_t'} } */ +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x4_t'} } */ +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x4_t'} } */ +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x5_t'} } */ +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x5_t'} } */ +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x6_t'} } */ +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x6_t'} } */ +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x7_t'} } */ +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x7_t'} } */ +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x8_t'} } */ +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x8_t'} } */ +void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} +void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} +void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} +void f___rvv_uint32m1x3_t () {__rvv_uint32m1x3_t t;} +void f___rvv_int32m1x4_t () {__rvv_int32m1x4_t t;} +void f___rvv_uint32m1x4_t () {__rvv_uint32m1x4_t t;} +void f___rvv_int32m1x5_t () {__rvv_int32m1x5_t t;} +void f___rvv_uint32m1x5_t () {__rvv_uint32m1x5_t t;} +void f___rvv_int32m1x6_t () {__rvv_int32m1x6_t t;} +void f___rvv_uint32m1x6_t () {__rvv_uint32m1x6_t t;} +void f___rvv_int32m1x7_t () {__rvv_int32m1x7_t t;} +void f___rvv_uint32m1x7_t () {__rvv_uint32m1x7_t t;} +void f___rvv_int32m1x8_t () {__rvv_int32m1x8_t t;} +void f___rvv_uint32m1x8_t () {__rvv_uint32m1x8_t t;} +void f___rvv_int32m2x2_t () {__rvv_int32m2x2_t t;} +void f___rvv_uint32m2x2_t () {__rvv_uint32m2x2_t t;} +void f___rvv_int32m2x3_t () {__rvv_int32m2x3_t t;} +void f___rvv_uint32m2x3_t () {__rvv_uint32m2x3_t t;} +void f___rvv_int32m2x4_t () {__rvv_int32m2x4_t t;} +void f___rvv_uint32m2x4_t () {__rvv_uint32m2x4_t t;} +void f___rvv_int32m4x2_t () {__rvv_int32m4x2_t t;} +void f___rvv_uint32m4x2_t () {__rvv_uint32m4x2_t t;} +void f___rvv_int64m1x2_t () {__rvv_int64m1x2_t t;} /* { dg-error {unknown type name '__rvv_int64m1x2_t'} } */ +void f___rvv_uint64m1x2_t () {__rvv_uint64m1x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x2_t'} } */ +void f___rvv_int64m1x3_t () {__rvv_int64m1x3_t t;} /* { dg-error {unknown type name '__rvv_int64m1x3_t'} } */ +void f___rvv_uint64m1x3_t () {__rvv_uint64m1x3_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x3_t'} } */ +void f___rvv_int64m1x4_t () {__rvv_int64m1x4_t t;} /* { dg-error {unknown type name '__rvv_int64m1x4_t'} } */ +void f___rvv_uint64m1x4_t () {__rvv_uint64m1x4_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x4_t'} } */ +void f___rvv_int64m1x5_t () {__rvv_int64m1x5_t t;} /* { dg-error {unknown type name '__rvv_int64m1x5_t'} } */ +void f___rvv_uint64m1x5_t () {__rvv_uint64m1x5_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x5_t'} } */ +void f___rvv_int64m1x6_t () {__rvv_int64m1x6_t t;} /* { dg-error {unknown type name '__rvv_int64m1x6_t'} } */ +void f___rvv_uint64m1x6_t () {__rvv_uint64m1x6_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x6_t'} } */ +void f___rvv_int64m1x7_t () {__rvv_int64m1x7_t t;} /* { dg-error {unknown type name '__rvv_int64m1x7_t'} } */ +void f___rvv_uint64m1x7_t () {__rvv_uint64m1x7_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x7_t'} } */ +void f___rvv_int64m1x8_t () {__rvv_int64m1x8_t t;} /* { dg-error {unknown type name '__rvv_int64m1x8_t'} } */ +void f___rvv_uint64m1x8_t () {__rvv_uint64m1x8_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x8_t'} } */ +void f___rvv_int64m2x2_t () {__rvv_int64m2x2_t t;} /* { dg-error {unknown type name '__rvv_int64m2x2_t'} } */ +void f___rvv_uint64m2x2_t () {__rvv_uint64m2x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x2_t'} } */ +void f___rvv_int64m2x3_t () {__rvv_int64m2x3_t t;} /* { dg-error {unknown type name '__rvv_int64m2x3_t'} } */ +void f___rvv_uint64m2x3_t () {__rvv_uint64m2x3_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x3_t'} } */ +void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} /* { dg-error {unknown type name '__rvv_int64m2x4_t'} } */ +void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x4_t'} } */ +void f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} /* { dg-error {unknown type name '__rvv_int64m4x2_t'} } */ +void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m4x2_t'} } */ +void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x2_t'} } */ +void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x3_t'} } */ +void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x4_t'} } */ +void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x5_t'} } */ +void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x6_t'} } */ +void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x7_t'} } */ +void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x8_t'} } */ +void f___rvv_float32m1x2_t () {__rvv_float32m1x2_t t;} /* { dg-error {unknown type name '__rvv_float32m1x2_t'} } */ +void f___rvv_float32m1x3_t () {__rvv_float32m1x3_t t;} /* { dg-error {unknown type name '__rvv_float32m1x3_t'} } */ +void f___rvv_float32m1x4_t () {__rvv_float32m1x4_t t;} /* { dg-error {unknown type name '__rvv_float32m1x4_t'} } */ +void f___rvv_float32m1x5_t () {__rvv_float32m1x5_t t;} /* { dg-error {unknown type name '__rvv_float32m1x5_t'} } */ +void f___rvv_float32m1x6_t () {__rvv_float32m1x6_t t;} /* { dg-error {unknown type name '__rvv_float32m1x6_t'} } */ +void f___rvv_float32m1x7_t () {__rvv_float32m1x7_t t;} /* { dg-error {unknown type name '__rvv_float32m1x7_t'} } */ +void f___rvv_float32m1x8_t () {__rvv_float32m1x8_t t;} /* { dg-error {unknown type name '__rvv_float32m1x8_t'} } */ +void f___rvv_float32m2x2_t () {__rvv_float32m2x2_t t;} /* { dg-error {unknown type name '__rvv_float32m2x2_t'} } */ +void f___rvv_float32m2x3_t () {__rvv_float32m2x3_t t;} /* { dg-error {unknown type name '__rvv_float32m2x3_t'} } */ +void f___rvv_float32m2x4_t () {__rvv_float32m2x4_t t;} /* { dg-error {unknown type name '__rvv_float32m2x4_t'} } */ +void f___rvv_float32m4x2_t () {__rvv_float32m4x2_t t;} /* { dg-error {unknown type name '__rvv_float32m4x2_t'} } */ +void f___rvv_float64m1x2_t () {__rvv_float64m1x2_t t;} /* { dg-error {unknown type name '__rvv_float64m1x2_t'} } */ +void f___rvv_float64m1x3_t () {__rvv_float64m1x3_t t;} /* { dg-error {unknown type name '__rvv_float64m1x3_t'} } */ +void f___rvv_float64m1x4_t () {__rvv_float64m1x4_t t;} /* { dg-error {unknown type name '__rvv_float64m1x4_t'} } */ +void f___rvv_float64m1x5_t () {__rvv_float64m1x5_t t;} /* { dg-error {unknown type name '__rvv_float64m1x5_t'} } */ +void f___rvv_float64m1x6_t () {__rvv_float64m1x6_t t;} /* { dg-error {unknown type name '__rvv_float64m1x6_t'} } */ +void f___rvv_float64m1x7_t () {__rvv_float64m1x7_t t;} /* { dg-error {unknown type name '__rvv_float64m1x7_t'} } */ +void f___rvv_float64m1x8_t () {__rvv_float64m1x8_t t;} /* { dg-error {unknown type name '__rvv_float64m1x8_t'} } */ +void f___rvv_float64m2x2_t () {__rvv_float64m2x2_t t;} /* { dg-error {unknown type name '__rvv_float64m2x2_t'} } */ +void f___rvv_float64m2x3_t () {__rvv_float64m2x3_t t;} /* { dg-error {unknown type name '__rvv_float64m2x3_t'} } */ +void f___rvv_float64m2x4_t () {__rvv_float64m2x4_t t;} /* { dg-error {unknown type name '__rvv_float64m2x4_t'} } */ +void f___rvv_float64m4x2_t () {__rvv_float64m4x2_t t;} /* { dg-error {unknown type name '__rvv_float64m4x2_t'} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-14.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-14.c new file mode 100644 index 00000000000..163152ae923 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-14.c @@ -0,0 +1,204 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc_zve32x_zvl64b -mabi=ilp32d" } */ + +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} +void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} +void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} +void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} +void f___rvv_uint8mf4x3_t () {__rvv_uint8mf4x3_t t;} +void f___rvv_int8mf4x4_t () {__rvv_int8mf4x4_t t;} +void f___rvv_uint8mf4x4_t () {__rvv_uint8mf4x4_t t;} +void f___rvv_int8mf4x5_t () {__rvv_int8mf4x5_t t;} +void f___rvv_uint8mf4x5_t () {__rvv_uint8mf4x5_t t;} +void f___rvv_int8mf4x6_t () {__rvv_int8mf4x6_t t;} +void f___rvv_uint8mf4x6_t () {__rvv_uint8mf4x6_t t;} +void f___rvv_int8mf4x7_t () {__rvv_int8mf4x7_t t;} +void f___rvv_uint8mf4x7_t () {__rvv_uint8mf4x7_t t;} +void f___rvv_int8mf4x8_t () {__rvv_int8mf4x8_t t;} +void f___rvv_uint8mf4x8_t () {__rvv_uint8mf4x8_t t;} +void f___rvv_int8mf2x2_t () {__rvv_int8mf2x2_t t;} +void f___rvv_uint8mf2x2_t () {__rvv_uint8mf2x2_t t;} +void f___rvv_int8mf2x3_t () {__rvv_int8mf2x3_t t;} +void f___rvv_uint8mf2x3_t () {__rvv_uint8mf2x3_t t;} +void f___rvv_int8mf2x4_t () {__rvv_int8mf2x4_t t;} +void f___rvv_uint8mf2x4_t () {__rvv_uint8mf2x4_t t;} +void f___rvv_int8mf2x5_t () {__rvv_int8mf2x5_t t;} +void f___rvv_uint8mf2x5_t () {__rvv_uint8mf2x5_t t;} +void f___rvv_int8mf2x6_t () {__rvv_int8mf2x6_t t;} +void f___rvv_uint8mf2x6_t () {__rvv_uint8mf2x6_t t;} +void f___rvv_int8mf2x7_t () {__rvv_int8mf2x7_t t;} +void f___rvv_uint8mf2x7_t () {__rvv_uint8mf2x7_t t;} +void f___rvv_int8mf2x8_t () {__rvv_int8mf2x8_t t;} +void f___rvv_uint8mf2x8_t () {__rvv_uint8mf2x8_t t;} +void f___rvv_int8m1x2_t () {__rvv_int8m1x2_t t;} +void f___rvv_uint8m1x2_t () {__rvv_uint8m1x2_t t;} +void f___rvv_int8m1x3_t () {__rvv_int8m1x3_t t;} +void f___rvv_uint8m1x3_t () {__rvv_uint8m1x3_t t;} +void f___rvv_int8m1x4_t () {__rvv_int8m1x4_t t;} +void f___rvv_uint8m1x4_t () {__rvv_uint8m1x4_t t;} +void f___rvv_int8m1x5_t () {__rvv_int8m1x5_t t;} +void f___rvv_uint8m1x5_t () {__rvv_uint8m1x5_t t;} +void f___rvv_int8m1x6_t () {__rvv_int8m1x6_t t;} +void f___rvv_uint8m1x6_t () {__rvv_uint8m1x6_t t;} +void f___rvv_int8m1x7_t () {__rvv_int8m1x7_t t;} +void f___rvv_uint8m1x7_t () {__rvv_uint8m1x7_t t;} +void f___rvv_int8m1x8_t () {__rvv_int8m1x8_t t;} +void f___rvv_uint8m1x8_t () {__rvv_uint8m1x8_t t;} +void f___rvv_int8m2x2_t () {__rvv_int8m2x2_t t;} +void f___rvv_uint8m2x2_t () {__rvv_uint8m2x2_t t;} +void f___rvv_int8m2x3_t () {__rvv_int8m2x3_t t;} +void f___rvv_uint8m2x3_t () {__rvv_uint8m2x3_t t;} +void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} +void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} +void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} +void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} +void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} +void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} +void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} +void f___rvv_uint16mf2x3_t () {__rvv_uint16mf2x3_t t;} +void f___rvv_int16mf2x4_t () {__rvv_int16mf2x4_t t;} +void f___rvv_uint16mf2x4_t () {__rvv_uint16mf2x4_t t;} +void f___rvv_int16mf2x5_t () {__rvv_int16mf2x5_t t;} +void f___rvv_uint16mf2x5_t () {__rvv_uint16mf2x5_t t;} +void f___rvv_int16mf2x6_t () {__rvv_int16mf2x6_t t;} +void f___rvv_uint16mf2x6_t () {__rvv_uint16mf2x6_t t;} +void f___rvv_int16mf2x7_t () {__rvv_int16mf2x7_t t;} +void f___rvv_uint16mf2x7_t () {__rvv_uint16mf2x7_t t;} +void f___rvv_int16mf2x8_t () {__rvv_int16mf2x8_t t;} +void f___rvv_uint16mf2x8_t () {__rvv_uint16mf2x8_t t;} +void f___rvv_int16m1x2_t () {__rvv_int16m1x2_t t;} +void f___rvv_uint16m1x2_t () {__rvv_uint16m1x2_t t;} +void f___rvv_int16m1x3_t () {__rvv_int16m1x3_t t;} +void f___rvv_uint16m1x3_t () {__rvv_uint16m1x3_t t;} +void f___rvv_int16m1x4_t () {__rvv_int16m1x4_t t;} +void f___rvv_uint16m1x4_t () {__rvv_uint16m1x4_t t;} +void f___rvv_int16m1x5_t () {__rvv_int16m1x5_t t;} +void f___rvv_uint16m1x5_t () {__rvv_uint16m1x5_t t;} +void f___rvv_int16m1x6_t () {__rvv_int16m1x6_t t;} +void f___rvv_uint16m1x6_t () {__rvv_uint16m1x6_t t;} +void f___rvv_int16m1x7_t () {__rvv_int16m1x7_t t;} +void f___rvv_uint16m1x7_t () {__rvv_uint16m1x7_t t;} +void f___rvv_int16m1x8_t () {__rvv_int16m1x8_t t;} +void f___rvv_uint16m1x8_t () {__rvv_uint16m1x8_t t;} +void f___rvv_int16m2x2_t () {__rvv_int16m2x2_t t;} +void f___rvv_uint16m2x2_t () {__rvv_uint16m2x2_t t;} +void f___rvv_int16m2x3_t () {__rvv_int16m2x3_t t;} +void f___rvv_uint16m2x3_t () {__rvv_uint16m2x3_t t;} +void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} +void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} +void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} +void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} +void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} +void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} +void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} +void f___rvv_uint32m1x3_t () {__rvv_uint32m1x3_t t;} +void f___rvv_int32m1x4_t () {__rvv_int32m1x4_t t;} +void f___rvv_uint32m1x4_t () {__rvv_uint32m1x4_t t;} +void f___rvv_int32m1x5_t () {__rvv_int32m1x5_t t;} +void f___rvv_uint32m1x5_t () {__rvv_uint32m1x5_t t;} +void f___rvv_int32m1x6_t () {__rvv_int32m1x6_t t;} +void f___rvv_uint32m1x6_t () {__rvv_uint32m1x6_t t;} +void f___rvv_int32m1x7_t () {__rvv_int32m1x7_t t;} +void f___rvv_uint32m1x7_t () {__rvv_uint32m1x7_t t;} +void f___rvv_int32m1x8_t () {__rvv_int32m1x8_t t;} +void f___rvv_uint32m1x8_t () {__rvv_uint32m1x8_t t;} +void f___rvv_int32m2x2_t () {__rvv_int32m2x2_t t;} +void f___rvv_uint32m2x2_t () {__rvv_uint32m2x2_t t;} +void f___rvv_int32m2x3_t () {__rvv_int32m2x3_t t;} +void f___rvv_uint32m2x3_t () {__rvv_uint32m2x3_t t;} +void f___rvv_int32m2x4_t () {__rvv_int32m2x4_t t;} +void f___rvv_uint32m2x4_t () {__rvv_uint32m2x4_t t;} +void f___rvv_int32m4x2_t () {__rvv_int32m4x2_t t;} +void f___rvv_uint32m4x2_t () {__rvv_uint32m4x2_t t;} +void f___rvv_int64m1x2_t () {__rvv_int64m1x2_t t;} /* { dg-error {unknown type name '__rvv_int64m1x2_t'} } */ +void f___rvv_uint64m1x2_t () {__rvv_uint64m1x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x2_t'} } */ +void f___rvv_int64m1x3_t () {__rvv_int64m1x3_t t;} /* { dg-error {unknown type name '__rvv_int64m1x3_t'} } */ +void f___rvv_uint64m1x3_t () {__rvv_uint64m1x3_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x3_t'} } */ +void f___rvv_int64m1x4_t () {__rvv_int64m1x4_t t;} /* { dg-error {unknown type name '__rvv_int64m1x4_t'} } */ +void f___rvv_uint64m1x4_t () {__rvv_uint64m1x4_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x4_t'} } */ +void f___rvv_int64m1x5_t () {__rvv_int64m1x5_t t;} /* { dg-error {unknown type name '__rvv_int64m1x5_t'} } */ +void f___rvv_uint64m1x5_t () {__rvv_uint64m1x5_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x5_t'} } */ +void f___rvv_int64m1x6_t () {__rvv_int64m1x6_t t;} /* { dg-error {unknown type name '__rvv_int64m1x6_t'} } */ +void f___rvv_uint64m1x6_t () {__rvv_uint64m1x6_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x6_t'} } */ +void f___rvv_int64m1x7_t () {__rvv_int64m1x7_t t;} /* { dg-error {unknown type name '__rvv_int64m1x7_t'} } */ +void f___rvv_uint64m1x7_t () {__rvv_uint64m1x7_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x7_t'} } */ +void f___rvv_int64m1x8_t () {__rvv_int64m1x8_t t;} /* { dg-error {unknown type name '__rvv_int64m1x8_t'} } */ +void f___rvv_uint64m1x8_t () {__rvv_uint64m1x8_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x8_t'} } */ +void f___rvv_int64m2x2_t () {__rvv_int64m2x2_t t;} /* { dg-error {unknown type name '__rvv_int64m2x2_t'} } */ +void f___rvv_uint64m2x2_t () {__rvv_uint64m2x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x2_t'} } */ +void f___rvv_int64m2x3_t () {__rvv_int64m2x3_t t;} /* { dg-error {unknown type name '__rvv_int64m2x3_t'} } */ +void f___rvv_uint64m2x3_t () {__rvv_uint64m2x3_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x3_t'} } */ +void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} /* { dg-error {unknown type name '__rvv_int64m2x4_t'} } */ +void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x4_t'} } */ +void f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} /* { dg-error {unknown type name '__rvv_int64m4x2_t'} } */ +void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m4x2_t'} } */ +void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x2_t'} } */ +void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x3_t'} } */ +void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x4_t'} } */ +void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x5_t'} } */ +void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x6_t'} } */ +void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x7_t'} } */ +void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x8_t'} } */ +void f___rvv_float32m1x2_t () {__rvv_float32m1x2_t t;} /* { dg-error {unknown type name '__rvv_float32m1x2_t'} } */ +void f___rvv_float32m1x3_t () {__rvv_float32m1x3_t t;} /* { dg-error {unknown type name '__rvv_float32m1x3_t'} } */ +void f___rvv_float32m1x4_t () {__rvv_float32m1x4_t t;} /* { dg-error {unknown type name '__rvv_float32m1x4_t'} } */ +void f___rvv_float32m1x5_t () {__rvv_float32m1x5_t t;} /* { dg-error {unknown type name '__rvv_float32m1x5_t'} } */ +void f___rvv_float32m1x6_t () {__rvv_float32m1x6_t t;} /* { dg-error {unknown type name '__rvv_float32m1x6_t'} } */ +void f___rvv_float32m1x7_t () {__rvv_float32m1x7_t t;} /* { dg-error {unknown type name '__rvv_float32m1x7_t'} } */ +void f___rvv_float32m1x8_t () {__rvv_float32m1x8_t t;} /* { dg-error {unknown type name '__rvv_float32m1x8_t'} } */ +void f___rvv_float32m2x2_t () {__rvv_float32m2x2_t t;} /* { dg-error {unknown type name '__rvv_float32m2x2_t'} } */ +void f___rvv_float32m2x3_t () {__rvv_float32m2x3_t t;} /* { dg-error {unknown type name '__rvv_float32m2x3_t'} } */ +void f___rvv_float32m2x4_t () {__rvv_float32m2x4_t t;} /* { dg-error {unknown type name '__rvv_float32m2x4_t'} } */ +void f___rvv_float32m4x2_t () {__rvv_float32m4x2_t t;} /* { dg-error {unknown type name '__rvv_float32m4x2_t'} } */ +void f___rvv_float64m1x2_t () {__rvv_float64m1x2_t t;} /* { dg-error {unknown type name '__rvv_float64m1x2_t'} } */ +void f___rvv_float64m1x3_t () {__rvv_float64m1x3_t t;} /* { dg-error {unknown type name '__rvv_float64m1x3_t'} } */ +void f___rvv_float64m1x4_t () {__rvv_float64m1x4_t t;} /* { dg-error {unknown type name '__rvv_float64m1x4_t'} } */ +void f___rvv_float64m1x5_t () {__rvv_float64m1x5_t t;} /* { dg-error {unknown type name '__rvv_float64m1x5_t'} } */ +void f___rvv_float64m1x6_t () {__rvv_float64m1x6_t t;} /* { dg-error {unknown type name '__rvv_float64m1x6_t'} } */ +void f___rvv_float64m1x7_t () {__rvv_float64m1x7_t t;} /* { dg-error {unknown type name '__rvv_float64m1x7_t'} } */ +void f___rvv_float64m1x8_t () {__rvv_float64m1x8_t t;} /* { dg-error {unknown type name '__rvv_float64m1x8_t'} } */ +void f___rvv_float64m2x2_t () {__rvv_float64m2x2_t t;} /* { dg-error {unknown type name '__rvv_float64m2x2_t'} } */ +void f___rvv_float64m2x3_t () {__rvv_float64m2x3_t t;} /* { dg-error {unknown type name '__rvv_float64m2x3_t'} } */ +void f___rvv_float64m2x4_t () {__rvv_float64m2x4_t t;} /* { dg-error {unknown type name '__rvv_float64m2x4_t'} } */ +void f___rvv_float64m4x2_t () {__rvv_float64m4x2_t t;} /* { dg-error {unknown type name '__rvv_float64m4x2_t'} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-15.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-15.c new file mode 100644 index 00000000000..b52d86c6a36 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-15.c @@ -0,0 +1,204 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc_zve32f -mabi=ilp32d" } */ + +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x2_t'} } */ +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x2_t'} } */ +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x3_t'} } */ +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x3_t'} } */ +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x4_t'} } */ +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x4_t'} } */ +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x5_t'} } */ +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x5_t'} } */ +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x6_t'} } */ +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x6_t'} } */ +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x7_t'} } */ +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x7_t'} } */ +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x8_t'} } */ +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x8_t'} } */ +void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} +void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} +void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} +void f___rvv_uint8mf4x3_t () {__rvv_uint8mf4x3_t t;} +void f___rvv_int8mf4x4_t () {__rvv_int8mf4x4_t t;} +void f___rvv_uint8mf4x4_t () {__rvv_uint8mf4x4_t t;} +void f___rvv_int8mf4x5_t () {__rvv_int8mf4x5_t t;} +void f___rvv_uint8mf4x5_t () {__rvv_uint8mf4x5_t t;} +void f___rvv_int8mf4x6_t () {__rvv_int8mf4x6_t t;} +void f___rvv_uint8mf4x6_t () {__rvv_uint8mf4x6_t t;} +void f___rvv_int8mf4x7_t () {__rvv_int8mf4x7_t t;} +void f___rvv_uint8mf4x7_t () {__rvv_uint8mf4x7_t t;} +void f___rvv_int8mf4x8_t () {__rvv_int8mf4x8_t t;} +void f___rvv_uint8mf4x8_t () {__rvv_uint8mf4x8_t t;} +void f___rvv_int8mf2x2_t () {__rvv_int8mf2x2_t t;} +void f___rvv_uint8mf2x2_t () {__rvv_uint8mf2x2_t t;} +void f___rvv_int8mf2x3_t () {__rvv_int8mf2x3_t t;} +void f___rvv_uint8mf2x3_t () {__rvv_uint8mf2x3_t t;} +void f___rvv_int8mf2x4_t () {__rvv_int8mf2x4_t t;} +void f___rvv_uint8mf2x4_t () {__rvv_uint8mf2x4_t t;} +void f___rvv_int8mf2x5_t () {__rvv_int8mf2x5_t t;} +void f___rvv_uint8mf2x5_t () {__rvv_uint8mf2x5_t t;} +void f___rvv_int8mf2x6_t () {__rvv_int8mf2x6_t t;} +void f___rvv_uint8mf2x6_t () {__rvv_uint8mf2x6_t t;} +void f___rvv_int8mf2x7_t () {__rvv_int8mf2x7_t t;} +void f___rvv_uint8mf2x7_t () {__rvv_uint8mf2x7_t t;} +void f___rvv_int8mf2x8_t () {__rvv_int8mf2x8_t t;} +void f___rvv_uint8mf2x8_t () {__rvv_uint8mf2x8_t t;} +void f___rvv_int8m1x2_t () {__rvv_int8m1x2_t t;} +void f___rvv_uint8m1x2_t () {__rvv_uint8m1x2_t t;} +void f___rvv_int8m1x3_t () {__rvv_int8m1x3_t t;} +void f___rvv_uint8m1x3_t () {__rvv_uint8m1x3_t t;} +void f___rvv_int8m1x4_t () {__rvv_int8m1x4_t t;} +void f___rvv_uint8m1x4_t () {__rvv_uint8m1x4_t t;} +void f___rvv_int8m1x5_t () {__rvv_int8m1x5_t t;} +void f___rvv_uint8m1x5_t () {__rvv_uint8m1x5_t t;} +void f___rvv_int8m1x6_t () {__rvv_int8m1x6_t t;} +void f___rvv_uint8m1x6_t () {__rvv_uint8m1x6_t t;} +void f___rvv_int8m1x7_t () {__rvv_int8m1x7_t t;} +void f___rvv_uint8m1x7_t () {__rvv_uint8m1x7_t t;} +void f___rvv_int8m1x8_t () {__rvv_int8m1x8_t t;} +void f___rvv_uint8m1x8_t () {__rvv_uint8m1x8_t t;} +void f___rvv_int8m2x2_t () {__rvv_int8m2x2_t t;} +void f___rvv_uint8m2x2_t () {__rvv_uint8m2x2_t t;} +void f___rvv_int8m2x3_t () {__rvv_int8m2x3_t t;} +void f___rvv_uint8m2x3_t () {__rvv_uint8m2x3_t t;} +void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} +void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} +void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} +void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x2_t'} } */ +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x2_t'} } */ +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x3_t'} } */ +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x3_t'} } */ +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x4_t'} } */ +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x4_t'} } */ +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x5_t'} } */ +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x5_t'} } */ +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x6_t'} } */ +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x6_t'} } */ +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x7_t'} } */ +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x7_t'} } */ +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x8_t'} } */ +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x8_t'} } */ +void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} +void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} +void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} +void f___rvv_uint16mf2x3_t () {__rvv_uint16mf2x3_t t;} +void f___rvv_int16mf2x4_t () {__rvv_int16mf2x4_t t;} +void f___rvv_uint16mf2x4_t () {__rvv_uint16mf2x4_t t;} +void f___rvv_int16mf2x5_t () {__rvv_int16mf2x5_t t;} +void f___rvv_uint16mf2x5_t () {__rvv_uint16mf2x5_t t;} +void f___rvv_int16mf2x6_t () {__rvv_int16mf2x6_t t;} +void f___rvv_uint16mf2x6_t () {__rvv_uint16mf2x6_t t;} +void f___rvv_int16mf2x7_t () {__rvv_int16mf2x7_t t;} +void f___rvv_uint16mf2x7_t () {__rvv_uint16mf2x7_t t;} +void f___rvv_int16mf2x8_t () {__rvv_int16mf2x8_t t;} +void f___rvv_uint16mf2x8_t () {__rvv_uint16mf2x8_t t;} +void f___rvv_int16m1x2_t () {__rvv_int16m1x2_t t;} +void f___rvv_uint16m1x2_t () {__rvv_uint16m1x2_t t;} +void f___rvv_int16m1x3_t () {__rvv_int16m1x3_t t;} +void f___rvv_uint16m1x3_t () {__rvv_uint16m1x3_t t;} +void f___rvv_int16m1x4_t () {__rvv_int16m1x4_t t;} +void f___rvv_uint16m1x4_t () {__rvv_uint16m1x4_t t;} +void f___rvv_int16m1x5_t () {__rvv_int16m1x5_t t;} +void f___rvv_uint16m1x5_t () {__rvv_uint16m1x5_t t;} +void f___rvv_int16m1x6_t () {__rvv_int16m1x6_t t;} +void f___rvv_uint16m1x6_t () {__rvv_uint16m1x6_t t;} +void f___rvv_int16m1x7_t () {__rvv_int16m1x7_t t;} +void f___rvv_uint16m1x7_t () {__rvv_uint16m1x7_t t;} +void f___rvv_int16m1x8_t () {__rvv_int16m1x8_t t;} +void f___rvv_uint16m1x8_t () {__rvv_uint16m1x8_t t;} +void f___rvv_int16m2x2_t () {__rvv_int16m2x2_t t;} +void f___rvv_uint16m2x2_t () {__rvv_uint16m2x2_t t;} +void f___rvv_int16m2x3_t () {__rvv_int16m2x3_t t;} +void f___rvv_uint16m2x3_t () {__rvv_uint16m2x3_t t;} +void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} +void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} +void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} +void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x2_t'} } */ +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x2_t'} } */ +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x3_t'} } */ +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x3_t'} } */ +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x4_t'} } */ +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x4_t'} } */ +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x5_t'} } */ +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x5_t'} } */ +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x6_t'} } */ +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x6_t'} } */ +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x7_t'} } */ +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x7_t'} } */ +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x8_t'} } */ +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x8_t'} } */ +void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} +void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} +void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} +void f___rvv_uint32m1x3_t () {__rvv_uint32m1x3_t t;} +void f___rvv_int32m1x4_t () {__rvv_int32m1x4_t t;} +void f___rvv_uint32m1x4_t () {__rvv_uint32m1x4_t t;} +void f___rvv_int32m1x5_t () {__rvv_int32m1x5_t t;} +void f___rvv_uint32m1x5_t () {__rvv_uint32m1x5_t t;} +void f___rvv_int32m1x6_t () {__rvv_int32m1x6_t t;} +void f___rvv_uint32m1x6_t () {__rvv_uint32m1x6_t t;} +void f___rvv_int32m1x7_t () {__rvv_int32m1x7_t t;} +void f___rvv_uint32m1x7_t () {__rvv_uint32m1x7_t t;} +void f___rvv_int32m1x8_t () {__rvv_int32m1x8_t t;} +void f___rvv_uint32m1x8_t () {__rvv_uint32m1x8_t t;} +void f___rvv_int32m2x2_t () {__rvv_int32m2x2_t t;} +void f___rvv_uint32m2x2_t () {__rvv_uint32m2x2_t t;} +void f___rvv_int32m2x3_t () {__rvv_int32m2x3_t t;} +void f___rvv_uint32m2x3_t () {__rvv_uint32m2x3_t t;} +void f___rvv_int32m2x4_t () {__rvv_int32m2x4_t t;} +void f___rvv_uint32m2x4_t () {__rvv_uint32m2x4_t t;} +void f___rvv_int32m4x2_t () {__rvv_int32m4x2_t t;} +void f___rvv_uint32m4x2_t () {__rvv_uint32m4x2_t t;} +void f___rvv_int64m1x2_t () {__rvv_int64m1x2_t t;} /* { dg-error {unknown type name '__rvv_int64m1x2_t'} } */ +void f___rvv_uint64m1x2_t () {__rvv_uint64m1x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x2_t'} } */ +void f___rvv_int64m1x3_t () {__rvv_int64m1x3_t t;} /* { dg-error {unknown type name '__rvv_int64m1x3_t'} } */ +void f___rvv_uint64m1x3_t () {__rvv_uint64m1x3_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x3_t'} } */ +void f___rvv_int64m1x4_t () {__rvv_int64m1x4_t t;} /* { dg-error {unknown type name '__rvv_int64m1x4_t'} } */ +void f___rvv_uint64m1x4_t () {__rvv_uint64m1x4_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x4_t'} } */ +void f___rvv_int64m1x5_t () {__rvv_int64m1x5_t t;} /* { dg-error {unknown type name '__rvv_int64m1x5_t'} } */ +void f___rvv_uint64m1x5_t () {__rvv_uint64m1x5_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x5_t'} } */ +void f___rvv_int64m1x6_t () {__rvv_int64m1x6_t t;} /* { dg-error {unknown type name '__rvv_int64m1x6_t'} } */ +void f___rvv_uint64m1x6_t () {__rvv_uint64m1x6_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x6_t'} } */ +void f___rvv_int64m1x7_t () {__rvv_int64m1x7_t t;} /* { dg-error {unknown type name '__rvv_int64m1x7_t'} } */ +void f___rvv_uint64m1x7_t () {__rvv_uint64m1x7_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x7_t'} } */ +void f___rvv_int64m1x8_t () {__rvv_int64m1x8_t t;} /* { dg-error {unknown type name '__rvv_int64m1x8_t'} } */ +void f___rvv_uint64m1x8_t () {__rvv_uint64m1x8_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x8_t'} } */ +void f___rvv_int64m2x2_t () {__rvv_int64m2x2_t t;} /* { dg-error {unknown type name '__rvv_int64m2x2_t'} } */ +void f___rvv_uint64m2x2_t () {__rvv_uint64m2x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x2_t'} } */ +void f___rvv_int64m2x3_t () {__rvv_int64m2x3_t t;} /* { dg-error {unknown type name '__rvv_int64m2x3_t'} } */ +void f___rvv_uint64m2x3_t () {__rvv_uint64m2x3_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x3_t'} } */ +void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} /* { dg-error {unknown type name '__rvv_int64m2x4_t'} } */ +void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x4_t'} } */ +void f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} /* { dg-error {unknown type name '__rvv_int64m4x2_t'} } */ +void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m4x2_t'} } */ +void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x2_t'} } */ +void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x3_t'} } */ +void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x4_t'} } */ +void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x5_t'} } */ +void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x6_t'} } */ +void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x7_t'} } */ +void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x8_t'} } */ +void f___rvv_float32m1x2_t () {__rvv_float32m1x2_t t;} +void f___rvv_float32m1x3_t () {__rvv_float32m1x3_t t;} +void f___rvv_float32m1x4_t () {__rvv_float32m1x4_t t;} +void f___rvv_float32m1x5_t () {__rvv_float32m1x5_t t;} +void f___rvv_float32m1x6_t () {__rvv_float32m1x6_t t;} +void f___rvv_float32m1x7_t () {__rvv_float32m1x7_t t;} +void f___rvv_float32m1x8_t () {__rvv_float32m1x8_t t;} +void f___rvv_float32m2x2_t () {__rvv_float32m2x2_t t;} +void f___rvv_float32m2x3_t () {__rvv_float32m2x3_t t;} +void f___rvv_float32m2x4_t () {__rvv_float32m2x4_t t;} +void f___rvv_float32m4x2_t () {__rvv_float32m4x2_t t;} +void f___rvv_float64m1x2_t () {__rvv_float64m1x2_t t;} /* { dg-error {unknown type name '__rvv_float64m1x2_t'} } */ +void f___rvv_float64m1x3_t () {__rvv_float64m1x3_t t;} /* { dg-error {unknown type name '__rvv_float64m1x3_t'} } */ +void f___rvv_float64m1x4_t () {__rvv_float64m1x4_t t;} /* { dg-error {unknown type name '__rvv_float64m1x4_t'} } */ +void f___rvv_float64m1x5_t () {__rvv_float64m1x5_t t;} /* { dg-error {unknown type name '__rvv_float64m1x5_t'} } */ +void f___rvv_float64m1x6_t () {__rvv_float64m1x6_t t;} /* { dg-error {unknown type name '__rvv_float64m1x6_t'} } */ +void f___rvv_float64m1x7_t () {__rvv_float64m1x7_t t;} /* { dg-error {unknown type name '__rvv_float64m1x7_t'} } */ +void f___rvv_float64m1x8_t () {__rvv_float64m1x8_t t;} /* { dg-error {unknown type name '__rvv_float64m1x8_t'} } */ +void f___rvv_float64m2x2_t () {__rvv_float64m2x2_t t;} /* { dg-error {unknown type name '__rvv_float64m2x2_t'} } */ +void f___rvv_float64m2x3_t () {__rvv_float64m2x3_t t;} /* { dg-error {unknown type name '__rvv_float64m2x3_t'} } */ +void f___rvv_float64m2x4_t () {__rvv_float64m2x4_t t;} /* { dg-error {unknown type name '__rvv_float64m2x4_t'} } */ +void f___rvv_float64m4x2_t () {__rvv_float64m4x2_t t;} /* { dg-error {unknown type name '__rvv_float64m4x2_t'} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c new file mode 100644 index 00000000000..be2cbb5efd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c @@ -0,0 +1,204 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc_zve32f_zvl64b -mabi=ilp32d" } */ + +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} +void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} +void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} +void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} +void f___rvv_uint8mf4x3_t () {__rvv_uint8mf4x3_t t;} +void f___rvv_int8mf4x4_t () {__rvv_int8mf4x4_t t;} +void f___rvv_uint8mf4x4_t () {__rvv_uint8mf4x4_t t;} +void f___rvv_int8mf4x5_t () {__rvv_int8mf4x5_t t;} +void f___rvv_uint8mf4x5_t () {__rvv_uint8mf4x5_t t;} +void f___rvv_int8mf4x6_t () {__rvv_int8mf4x6_t t;} +void f___rvv_uint8mf4x6_t () {__rvv_uint8mf4x6_t t;} +void f___rvv_int8mf4x7_t () {__rvv_int8mf4x7_t t;} +void f___rvv_uint8mf4x7_t () {__rvv_uint8mf4x7_t t;} +void f___rvv_int8mf4x8_t () {__rvv_int8mf4x8_t t;} +void f___rvv_uint8mf4x8_t () {__rvv_uint8mf4x8_t t;} +void f___rvv_int8mf2x2_t () {__rvv_int8mf2x2_t t;} +void f___rvv_uint8mf2x2_t () {__rvv_uint8mf2x2_t t;} +void f___rvv_int8mf2x3_t () {__rvv_int8mf2x3_t t;} +void f___rvv_uint8mf2x3_t () {__rvv_uint8mf2x3_t t;} +void f___rvv_int8mf2x4_t () {__rvv_int8mf2x4_t t;} +void f___rvv_uint8mf2x4_t () {__rvv_uint8mf2x4_t t;} +void f___rvv_int8mf2x5_t () {__rvv_int8mf2x5_t t;} +void f___rvv_uint8mf2x5_t () {__rvv_uint8mf2x5_t t;} +void f___rvv_int8mf2x6_t () {__rvv_int8mf2x6_t t;} +void f___rvv_uint8mf2x6_t () {__rvv_uint8mf2x6_t t;} +void f___rvv_int8mf2x7_t () {__rvv_int8mf2x7_t t;} +void f___rvv_uint8mf2x7_t () {__rvv_uint8mf2x7_t t;} +void f___rvv_int8mf2x8_t () {__rvv_int8mf2x8_t t;} +void f___rvv_uint8mf2x8_t () {__rvv_uint8mf2x8_t t;} +void f___rvv_int8m1x2_t () {__rvv_int8m1x2_t t;} +void f___rvv_uint8m1x2_t () {__rvv_uint8m1x2_t t;} +void f___rvv_int8m1x3_t () {__rvv_int8m1x3_t t;} +void f___rvv_uint8m1x3_t () {__rvv_uint8m1x3_t t;} +void f___rvv_int8m1x4_t () {__rvv_int8m1x4_t t;} +void f___rvv_uint8m1x4_t () {__rvv_uint8m1x4_t t;} +void f___rvv_int8m1x5_t () {__rvv_int8m1x5_t t;} +void f___rvv_uint8m1x5_t () {__rvv_uint8m1x5_t t;} +void f___rvv_int8m1x6_t () {__rvv_int8m1x6_t t;} +void f___rvv_uint8m1x6_t () {__rvv_uint8m1x6_t t;} +void f___rvv_int8m1x7_t () {__rvv_int8m1x7_t t;} +void f___rvv_uint8m1x7_t () {__rvv_uint8m1x7_t t;} +void f___rvv_int8m1x8_t () {__rvv_int8m1x8_t t;} +void f___rvv_uint8m1x8_t () {__rvv_uint8m1x8_t t;} +void f___rvv_int8m2x2_t () {__rvv_int8m2x2_t t;} +void f___rvv_uint8m2x2_t () {__rvv_uint8m2x2_t t;} +void f___rvv_int8m2x3_t () {__rvv_int8m2x3_t t;} +void f___rvv_uint8m2x3_t () {__rvv_uint8m2x3_t t;} +void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} +void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} +void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} +void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} +void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} +void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} +void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} +void f___rvv_uint16mf2x3_t () {__rvv_uint16mf2x3_t t;} +void f___rvv_int16mf2x4_t () {__rvv_int16mf2x4_t t;} +void f___rvv_uint16mf2x4_t () {__rvv_uint16mf2x4_t t;} +void f___rvv_int16mf2x5_t () {__rvv_int16mf2x5_t t;} +void f___rvv_uint16mf2x5_t () {__rvv_uint16mf2x5_t t;} +void f___rvv_int16mf2x6_t () {__rvv_int16mf2x6_t t;} +void f___rvv_uint16mf2x6_t () {__rvv_uint16mf2x6_t t;} +void f___rvv_int16mf2x7_t () {__rvv_int16mf2x7_t t;} +void f___rvv_uint16mf2x7_t () {__rvv_uint16mf2x7_t t;} +void f___rvv_int16mf2x8_t () {__rvv_int16mf2x8_t t;} +void f___rvv_uint16mf2x8_t () {__rvv_uint16mf2x8_t t;} +void f___rvv_int16m1x2_t () {__rvv_int16m1x2_t t;} +void f___rvv_uint16m1x2_t () {__rvv_uint16m1x2_t t;} +void f___rvv_int16m1x3_t () {__rvv_int16m1x3_t t;} +void f___rvv_uint16m1x3_t () {__rvv_uint16m1x3_t t;} +void f___rvv_int16m1x4_t () {__rvv_int16m1x4_t t;} +void f___rvv_uint16m1x4_t () {__rvv_uint16m1x4_t t;} +void f___rvv_int16m1x5_t () {__rvv_int16m1x5_t t;} +void f___rvv_uint16m1x5_t () {__rvv_uint16m1x5_t t;} +void f___rvv_int16m1x6_t () {__rvv_int16m1x6_t t;} +void f___rvv_uint16m1x6_t () {__rvv_uint16m1x6_t t;} +void f___rvv_int16m1x7_t () {__rvv_int16m1x7_t t;} +void f___rvv_uint16m1x7_t () {__rvv_uint16m1x7_t t;} +void f___rvv_int16m1x8_t () {__rvv_int16m1x8_t t;} +void f___rvv_uint16m1x8_t () {__rvv_uint16m1x8_t t;} +void f___rvv_int16m2x2_t () {__rvv_int16m2x2_t t;} +void f___rvv_uint16m2x2_t () {__rvv_uint16m2x2_t t;} +void f___rvv_int16m2x3_t () {__rvv_int16m2x3_t t;} +void f___rvv_uint16m2x3_t () {__rvv_uint16m2x3_t t;} +void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} +void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} +void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} +void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} +void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} +void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} +void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} +void f___rvv_uint32m1x3_t () {__rvv_uint32m1x3_t t;} +void f___rvv_int32m1x4_t () {__rvv_int32m1x4_t t;} +void f___rvv_uint32m1x4_t () {__rvv_uint32m1x4_t t;} +void f___rvv_int32m1x5_t () {__rvv_int32m1x5_t t;} +void f___rvv_uint32m1x5_t () {__rvv_uint32m1x5_t t;} +void f___rvv_int32m1x6_t () {__rvv_int32m1x6_t t;} +void f___rvv_uint32m1x6_t () {__rvv_uint32m1x6_t t;} +void f___rvv_int32m1x7_t () {__rvv_int32m1x7_t t;} +void f___rvv_uint32m1x7_t () {__rvv_uint32m1x7_t t;} +void f___rvv_int32m1x8_t () {__rvv_int32m1x8_t t;} +void f___rvv_uint32m1x8_t () {__rvv_uint32m1x8_t t;} +void f___rvv_int32m2x2_t () {__rvv_int32m2x2_t t;} +void f___rvv_uint32m2x2_t () {__rvv_uint32m2x2_t t;} +void f___rvv_int32m2x3_t () {__rvv_int32m2x3_t t;} +void f___rvv_uint32m2x3_t () {__rvv_uint32m2x3_t t;} +void f___rvv_int32m2x4_t () {__rvv_int32m2x4_t t;} +void f___rvv_uint32m2x4_t () {__rvv_uint32m2x4_t t;} +void f___rvv_int32m4x2_t () {__rvv_int32m4x2_t t;} +void f___rvv_uint32m4x2_t () {__rvv_uint32m4x2_t t;} +void f___rvv_int64m1x2_t () {__rvv_int64m1x2_t t;} /* { dg-error {unknown type name '__rvv_int64m1x2_t'} } */ +void f___rvv_uint64m1x2_t () {__rvv_uint64m1x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x2_t'} } */ +void f___rvv_int64m1x3_t () {__rvv_int64m1x3_t t;} /* { dg-error {unknown type name '__rvv_int64m1x3_t'} } */ +void f___rvv_uint64m1x3_t () {__rvv_uint64m1x3_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x3_t'} } */ +void f___rvv_int64m1x4_t () {__rvv_int64m1x4_t t;} /* { dg-error {unknown type name '__rvv_int64m1x4_t'} } */ +void f___rvv_uint64m1x4_t () {__rvv_uint64m1x4_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x4_t'} } */ +void f___rvv_int64m1x5_t () {__rvv_int64m1x5_t t;} /* { dg-error {unknown type name '__rvv_int64m1x5_t'} } */ +void f___rvv_uint64m1x5_t () {__rvv_uint64m1x5_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x5_t'} } */ +void f___rvv_int64m1x6_t () {__rvv_int64m1x6_t t;} /* { dg-error {unknown type name '__rvv_int64m1x6_t'} } */ +void f___rvv_uint64m1x6_t () {__rvv_uint64m1x6_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x6_t'} } */ +void f___rvv_int64m1x7_t () {__rvv_int64m1x7_t t;} /* { dg-error {unknown type name '__rvv_int64m1x7_t'} } */ +void f___rvv_uint64m1x7_t () {__rvv_uint64m1x7_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x7_t'} } */ +void f___rvv_int64m1x8_t () {__rvv_int64m1x8_t t;} /* { dg-error {unknown type name '__rvv_int64m1x8_t'} } */ +void f___rvv_uint64m1x8_t () {__rvv_uint64m1x8_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x8_t'} } */ +void f___rvv_int64m2x2_t () {__rvv_int64m2x2_t t;} /* { dg-error {unknown type name '__rvv_int64m2x2_t'} } */ +void f___rvv_uint64m2x2_t () {__rvv_uint64m2x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x2_t'} } */ +void f___rvv_int64m2x3_t () {__rvv_int64m2x3_t t;} /* { dg-error {unknown type name '__rvv_int64m2x3_t'} } */ +void f___rvv_uint64m2x3_t () {__rvv_uint64m2x3_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x3_t'} } */ +void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} /* { dg-error {unknown type name '__rvv_int64m2x4_t'} } */ +void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x4_t'} } */ +void f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} /* { dg-error {unknown type name '__rvv_int64m4x2_t'} } */ +void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m4x2_t'} } */ +void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} +void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} +void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} +void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} +void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} +void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} +void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} +void f___rvv_float32m1x2_t () {__rvv_float32m1x2_t t;} +void f___rvv_float32m1x3_t () {__rvv_float32m1x3_t t;} +void f___rvv_float32m1x4_t () {__rvv_float32m1x4_t t;} +void f___rvv_float32m1x5_t () {__rvv_float32m1x5_t t;} +void f___rvv_float32m1x6_t () {__rvv_float32m1x6_t t;} +void f___rvv_float32m1x7_t () {__rvv_float32m1x7_t t;} +void f___rvv_float32m1x8_t () {__rvv_float32m1x8_t t;} +void f___rvv_float32m2x2_t () {__rvv_float32m2x2_t t;} +void f___rvv_float32m2x3_t () {__rvv_float32m2x3_t t;} +void f___rvv_float32m2x4_t () {__rvv_float32m2x4_t t;} +void f___rvv_float32m4x2_t () {__rvv_float32m4x2_t t;} +void f___rvv_float64m1x2_t () {__rvv_float64m1x2_t t;} /* { dg-error {unknown type name '__rvv_float64m1x2_t'} } */ +void f___rvv_float64m1x3_t () {__rvv_float64m1x3_t t;} /* { dg-error {unknown type name '__rvv_float64m1x3_t'} } */ +void f___rvv_float64m1x4_t () {__rvv_float64m1x4_t t;} /* { dg-error {unknown type name '__rvv_float64m1x4_t'} } */ +void f___rvv_float64m1x5_t () {__rvv_float64m1x5_t t;} /* { dg-error {unknown type name '__rvv_float64m1x5_t'} } */ +void f___rvv_float64m1x6_t () {__rvv_float64m1x6_t t;} /* { dg-error {unknown type name '__rvv_float64m1x6_t'} } */ +void f___rvv_float64m1x7_t () {__rvv_float64m1x7_t t;} /* { dg-error {unknown type name '__rvv_float64m1x7_t'} } */ +void f___rvv_float64m1x8_t () {__rvv_float64m1x8_t t;} /* { dg-error {unknown type name '__rvv_float64m1x8_t'} } */ +void f___rvv_float64m2x2_t () {__rvv_float64m2x2_t t;} /* { dg-error {unknown type name '__rvv_float64m2x2_t'} } */ +void f___rvv_float64m2x3_t () {__rvv_float64m2x3_t t;} /* { dg-error {unknown type name '__rvv_float64m2x3_t'} } */ +void f___rvv_float64m2x4_t () {__rvv_float64m2x4_t t;} /* { dg-error {unknown type name '__rvv_float64m2x4_t'} } */ +void f___rvv_float64m4x2_t () {__rvv_float64m4x2_t t;} /* { dg-error {unknown type name '__rvv_float64m4x2_t'} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-8.c new file mode 100644 index 00000000000..282ee488be0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-8.c @@ -0,0 +1,205 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */ + +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} +void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} +void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} +void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} +void f___rvv_uint8mf4x3_t () {__rvv_uint8mf4x3_t t;} +void f___rvv_int8mf4x4_t () {__rvv_int8mf4x4_t t;} +void f___rvv_uint8mf4x4_t () {__rvv_uint8mf4x4_t t;} +void f___rvv_int8mf4x5_t () {__rvv_int8mf4x5_t t;} +void f___rvv_uint8mf4x5_t () {__rvv_uint8mf4x5_t t;} +void f___rvv_int8mf4x6_t () {__rvv_int8mf4x6_t t;} +void f___rvv_uint8mf4x6_t () {__rvv_uint8mf4x6_t t;} +void f___rvv_int8mf4x7_t () {__rvv_int8mf4x7_t t;} +void f___rvv_uint8mf4x7_t () {__rvv_uint8mf4x7_t t;} +void f___rvv_int8mf4x8_t () {__rvv_int8mf4x8_t t;} +void f___rvv_uint8mf4x8_t () {__rvv_uint8mf4x8_t t;} +void f___rvv_int8mf2x2_t () {__rvv_int8mf2x2_t t;} +void f___rvv_uint8mf2x2_t () {__rvv_uint8mf2x2_t t;} +void f___rvv_int8mf2x3_t () {__rvv_int8mf2x3_t t;} +void f___rvv_uint8mf2x3_t () {__rvv_uint8mf2x3_t t;} +void f___rvv_int8mf2x4_t () {__rvv_int8mf2x4_t t;} +void f___rvv_uint8mf2x4_t () {__rvv_uint8mf2x4_t t;} +void f___rvv_int8mf2x5_t () {__rvv_int8mf2x5_t t;} +void f___rvv_uint8mf2x5_t () {__rvv_uint8mf2x5_t t;} +void f___rvv_int8mf2x6_t () {__rvv_int8mf2x6_t t;} +void f___rvv_uint8mf2x6_t () {__rvv_uint8mf2x6_t t;} +void f___rvv_int8mf2x7_t () {__rvv_int8mf2x7_t t;} +void f___rvv_uint8mf2x7_t () {__rvv_uint8mf2x7_t t;} +void f___rvv_int8mf2x8_t () {__rvv_int8mf2x8_t t;} +void f___rvv_uint8mf2x8_t () {__rvv_uint8mf2x8_t t;} +void f___rvv_int8m1x2_t () {__rvv_int8m1x2_t t;} +void f___rvv_uint8m1x2_t () {__rvv_uint8m1x2_t t;} +void f___rvv_int8m1x3_t () {__rvv_int8m1x3_t t;} +void f___rvv_uint8m1x3_t () {__rvv_uint8m1x3_t t;} +void f___rvv_int8m1x4_t () {__rvv_int8m1x4_t t;} +void f___rvv_uint8m1x4_t () {__rvv_uint8m1x4_t t;} +void f___rvv_int8m1x5_t () {__rvv_int8m1x5_t t;} +void f___rvv_uint8m1x5_t () {__rvv_uint8m1x5_t t;} +void f___rvv_int8m1x6_t () {__rvv_int8m1x6_t t;} +void f___rvv_uint8m1x6_t () {__rvv_uint8m1x6_t t;} +void f___rvv_int8m1x7_t () {__rvv_int8m1x7_t t;} +void f___rvv_uint8m1x7_t () {__rvv_uint8m1x7_t t;} +void f___rvv_int8m1x8_t () {__rvv_int8m1x8_t t;} +void f___rvv_uint8m1x8_t () {__rvv_uint8m1x8_t t;} +void f___rvv_int8m2x2_t () {__rvv_int8m2x2_t t;} +void f___rvv_uint8m2x2_t () {__rvv_uint8m2x2_t t;} +void f___rvv_int8m2x3_t () {__rvv_int8m2x3_t t;} +void f___rvv_uint8m2x3_t () {__rvv_uint8m2x3_t t;} +void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} +void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} +void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} +void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} +void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} +void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} +void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} +void f___rvv_uint16mf2x3_t () {__rvv_uint16mf2x3_t t;} +void f___rvv_int16mf2x4_t () {__rvv_int16mf2x4_t t;} +void f___rvv_uint16mf2x4_t () {__rvv_uint16mf2x4_t t;} +void f___rvv_int16mf2x5_t () {__rvv_int16mf2x5_t t;} +void f___rvv_uint16mf2x5_t () {__rvv_uint16mf2x5_t t;} +void f___rvv_int16mf2x6_t () {__rvv_int16mf2x6_t t;} +void f___rvv_uint16mf2x6_t () {__rvv_uint16mf2x6_t t;} +void f___rvv_int16mf2x7_t () {__rvv_int16mf2x7_t t;} +void f___rvv_uint16mf2x7_t () {__rvv_uint16mf2x7_t t;} +void f___rvv_int16mf2x8_t () {__rvv_int16mf2x8_t t;} +void f___rvv_uint16mf2x8_t () {__rvv_uint16mf2x8_t t;} +void f___rvv_int16m1x2_t () {__rvv_int16m1x2_t t;} +void f___rvv_uint16m1x2_t () {__rvv_uint16m1x2_t t;} +void f___rvv_int16m1x3_t () {__rvv_int16m1x3_t t;} +void f___rvv_uint16m1x3_t () {__rvv_uint16m1x3_t t;} +void f___rvv_int16m1x4_t () {__rvv_int16m1x4_t t;} +void f___rvv_uint16m1x4_t () {__rvv_uint16m1x4_t t;} +void f___rvv_int16m1x5_t () {__rvv_int16m1x5_t t;} +void f___rvv_uint16m1x5_t () {__rvv_uint16m1x5_t t;} +void f___rvv_int16m1x6_t () {__rvv_int16m1x6_t t;} +void f___rvv_uint16m1x6_t () {__rvv_uint16m1x6_t t;} +void f___rvv_int16m1x7_t () {__rvv_int16m1x7_t t;} +void f___rvv_uint16m1x7_t () {__rvv_uint16m1x7_t t;} +void f___rvv_int16m1x8_t () {__rvv_int16m1x8_t t;} +void f___rvv_uint16m1x8_t () {__rvv_uint16m1x8_t t;} +void f___rvv_int16m2x2_t () {__rvv_int16m2x2_t t;} +void f___rvv_uint16m2x2_t () {__rvv_uint16m2x2_t t;} +void f___rvv_int16m2x3_t () {__rvv_int16m2x3_t t;} +void f___rvv_uint16m2x3_t () {__rvv_uint16m2x3_t t;} +void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} +void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} +void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} +void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} +void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} +void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} +void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} +void f___rvv_uint32m1x3_t () {__rvv_uint32m1x3_t t;} +void f___rvv_int32m1x4_t () {__rvv_int32m1x4_t t;} +void f___rvv_uint32m1x4_t () {__rvv_uint32m1x4_t t;} +void f___rvv_int32m1x5_t () {__rvv_int32m1x5_t t;} +void f___rvv_uint32m1x5_t () {__rvv_uint32m1x5_t t;} +void f___rvv_int32m1x6_t () {__rvv_int32m1x6_t t;} +void f___rvv_uint32m1x6_t () {__rvv_uint32m1x6_t t;} +void f___rvv_int32m1x7_t () {__rvv_int32m1x7_t t;} +void f___rvv_uint32m1x7_t () {__rvv_uint32m1x7_t t;} +void f___rvv_int32m1x8_t () {__rvv_int32m1x8_t t;} +void f___rvv_uint32m1x8_t () {__rvv_uint32m1x8_t t;} +void f___rvv_int32m2x2_t () {__rvv_int32m2x2_t t;} +void f___rvv_uint32m2x2_t () {__rvv_uint32m2x2_t t;} +void f___rvv_int32m2x3_t () {__rvv_int32m2x3_t t;} +void f___rvv_uint32m2x3_t () {__rvv_uint32m2x3_t t;} +void f___rvv_int32m2x4_t () {__rvv_int32m2x4_t t;} +void f___rvv_uint32m2x4_t () {__rvv_uint32m2x4_t t;} +void f___rvv_int32m4x2_t () {__rvv_int32m4x2_t t;} +void f___rvv_uint32m4x2_t () {__rvv_uint32m4x2_t t;} +void f___rvv_int64m1x2_t () {__rvv_int64m1x2_t t;} +void f___rvv_uint64m1x2_t () {__rvv_uint64m1x2_t t;} +void f___rvv_int64m1x3_t () {__rvv_int64m1x3_t t;} +void f___rvv_uint64m1x3_t () {__rvv_uint64m1x3_t t;} +void f___rvv_int64m1x4_t () {__rvv_int64m1x4_t t;} +void f___rvv_uint64m1x4_t () {__rvv_uint64m1x4_t t;} +void f___rvv_int64m1x5_t () {__rvv_int64m1x5_t t;} +void f___rvv_uint64m1x5_t () {__rvv_uint64m1x5_t t;} +void f___rvv_int64m1x6_t () {__rvv_int64m1x6_t t;} +void f___rvv_uint64m1x6_t () {__rvv_uint64m1x6_t t;} +void f___rvv_int64m1x7_t () {__rvv_int64m1x7_t t;} +void f___rvv_uint64m1x7_t () {__rvv_uint64m1x7_t t;} +void f___rvv_int64m1x8_t () {__rvv_int64m1x8_t t;} +void f___rvv_uint64m1x8_t () {__rvv_uint64m1x8_t t;} +void f___rvv_int64m2x2_t () {__rvv_int64m2x2_t t;} +void f___rvv_uint64m2x2_t () {__rvv_uint64m2x2_t t;} +void f___rvv_int64m2x3_t () {__rvv_int64m2x3_t t;} +void f___rvv_uint64m2x3_t () {__rvv_uint64m2x3_t t;} +void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} +void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} +void f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} +void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} +void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} +void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} +void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} +void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} +void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} +void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} +void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} +void f___rvv_float32m1x2_t () {__rvv_float32m1x2_t t;} +void f___rvv_float32m1x3_t () {__rvv_float32m1x3_t t;} +void f___rvv_float32m1x4_t () {__rvv_float32m1x4_t t;} +void f___rvv_float32m1x5_t () {__rvv_float32m1x5_t t;} +void f___rvv_float32m1x6_t () {__rvv_float32m1x6_t t;} +void f___rvv_float32m1x7_t () {__rvv_float32m1x7_t t;} +void f___rvv_float32m1x8_t () {__rvv_float32m1x8_t t;} +void f___rvv_float32m2x2_t () {__rvv_float32m2x2_t t;} +void f___rvv_float32m2x3_t () {__rvv_float32m2x3_t t;} +void f___rvv_float32m2x4_t () {__rvv_float32m2x4_t t;} +void f___rvv_float32m4x2_t () {__rvv_float32m4x2_t t;} +void f___rvv_float64m1x2_t () {__rvv_float64m1x2_t t;} +void f___rvv_float64m1x3_t () {__rvv_float64m1x3_t t;} +void f___rvv_float64m1x4_t () {__rvv_float64m1x4_t t;} +void f___rvv_float64m1x5_t () {__rvv_float64m1x5_t t;} +void f___rvv_float64m1x6_t () {__rvv_float64m1x6_t t;} +void f___rvv_float64m1x7_t () {__rvv_float64m1x7_t t;} +void f___rvv_float64m1x8_t () {__rvv_float64m1x8_t t;} +void f___rvv_float64m2x2_t () {__rvv_float64m2x2_t t;} +void f___rvv_float64m2x3_t () {__rvv_float64m2x3_t t;} +void f___rvv_float64m2x4_t () {__rvv_float64m2x4_t t;} +void f___rvv_float64m4x2_t () {__rvv_float64m4x2_t t;} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-9.c new file mode 100644 index 00000000000..37f78d1c7c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-9.c @@ -0,0 +1,204 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc -mabi=ilp32d" } */ + +void f___rvv_int8mf8x2_t () {__rvv_int8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x2_t'} } */ +void f___rvv_uint8mf8x2_t () {__rvv_uint8mf8x2_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x2_t'} } */ +void f___rvv_int8mf8x3_t () {__rvv_int8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x3_t'} } */ +void f___rvv_uint8mf8x3_t () {__rvv_uint8mf8x3_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x3_t'} } */ +void f___rvv_int8mf8x4_t () {__rvv_int8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x4_t'} } */ +void f___rvv_uint8mf8x4_t () {__rvv_uint8mf8x4_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x4_t'} } */ +void f___rvv_int8mf8x5_t () {__rvv_int8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x5_t'} } */ +void f___rvv_uint8mf8x5_t () {__rvv_uint8mf8x5_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x5_t'} } */ +void f___rvv_int8mf8x6_t () {__rvv_int8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x6_t'} } */ +void f___rvv_uint8mf8x6_t () {__rvv_uint8mf8x6_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x6_t'} } */ +void f___rvv_int8mf8x7_t () {__rvv_int8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x7_t'} } */ +void f___rvv_uint8mf8x7_t () {__rvv_uint8mf8x7_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x7_t'} } */ +void f___rvv_int8mf8x8_t () {__rvv_int8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_int8mf8x8_t'} } */ +void f___rvv_uint8mf8x8_t () {__rvv_uint8mf8x8_t t;} /* { dg-error {unknown type name '__rvv_uint8mf8x8_t'} } */ +void f___rvv_int8mf4x2_t () {__rvv_int8mf4x2_t t;} /* { dg-error {unknown type name '__rvv_int8mf4x2_t'} } */ +void f___rvv_uint8mf4x2_t () {__rvv_uint8mf4x2_t t;} /* { dg-error {unknown type name '__rvv_uint8mf4x2_t'} } */ +void f___rvv_int8mf4x3_t () {__rvv_int8mf4x3_t t;} /* { dg-error {unknown type name '__rvv_int8mf4x3_t'} } */ +void f___rvv_uint8mf4x3_t () {__rvv_uint8mf4x3_t t;} /* { dg-error {unknown type name '__rvv_uint8mf4x3_t'} } */ +void f___rvv_int8mf4x4_t () {__rvv_int8mf4x4_t t;} /* { dg-error {unknown type name '__rvv_int8mf4x4_t'} } */ +void f___rvv_uint8mf4x4_t () {__rvv_uint8mf4x4_t t;} /* { dg-error {unknown type name '__rvv_uint8mf4x4_t'} } */ +void f___rvv_int8mf4x5_t () {__rvv_int8mf4x5_t t;} /* { dg-error {unknown type name '__rvv_int8mf4x5_t'} } */ +void f___rvv_uint8mf4x5_t () {__rvv_uint8mf4x5_t t;} /* { dg-error {unknown type name '__rvv_uint8mf4x5_t'} } */ +void f___rvv_int8mf4x6_t () {__rvv_int8mf4x6_t t;} /* { dg-error {unknown type name '__rvv_int8mf4x6_t'} } */ +void f___rvv_uint8mf4x6_t () {__rvv_uint8mf4x6_t t;} /* { dg-error {unknown type name '__rvv_uint8mf4x6_t'} } */ +void f___rvv_int8mf4x7_t () {__rvv_int8mf4x7_t t;} /* { dg-error {unknown type name '__rvv_int8mf4x7_t'} } */ +void f___rvv_uint8mf4x7_t () {__rvv_uint8mf4x7_t t;} /* { dg-error {unknown type name '__rvv_uint8mf4x7_t'} } */ +void f___rvv_int8mf4x8_t () {__rvv_int8mf4x8_t t;} /* { dg-error {unknown type name '__rvv_int8mf4x8_t'} } */ +void f___rvv_uint8mf4x8_t () {__rvv_uint8mf4x8_t t;} /* { dg-error {unknown type name '__rvv_uint8mf4x8_t'} } */ +void f___rvv_int8mf2x2_t () {__rvv_int8mf2x2_t t;} /* { dg-error {unknown type name '__rvv_int8mf2x2_t'} } */ +void f___rvv_uint8mf2x2_t () {__rvv_uint8mf2x2_t t;} /* { dg-error {unknown type name '__rvv_uint8mf2x2_t'} } */ +void f___rvv_int8mf2x3_t () {__rvv_int8mf2x3_t t;} /* { dg-error {unknown type name '__rvv_int8mf2x3_t'} } */ +void f___rvv_uint8mf2x3_t () {__rvv_uint8mf2x3_t t;} /* { dg-error {unknown type name '__rvv_uint8mf2x3_t'} } */ +void f___rvv_int8mf2x4_t () {__rvv_int8mf2x4_t t;} /* { dg-error {unknown type name '__rvv_int8mf2x4_t'} } */ +void f___rvv_uint8mf2x4_t () {__rvv_uint8mf2x4_t t;} /* { dg-error {unknown type name '__rvv_uint8mf2x4_t'} } */ +void f___rvv_int8mf2x5_t () {__rvv_int8mf2x5_t t;} /* { dg-error {unknown type name '__rvv_int8mf2x5_t'} } */ +void f___rvv_uint8mf2x5_t () {__rvv_uint8mf2x5_t t;} /* { dg-error {unknown type name '__rvv_uint8mf2x5_t'} } */ +void f___rvv_int8mf2x6_t () {__rvv_int8mf2x6_t t;} /* { dg-error {unknown type name '__rvv_int8mf2x6_t'} } */ +void f___rvv_uint8mf2x6_t () {__rvv_uint8mf2x6_t t;} /* { dg-error {unknown type name '__rvv_uint8mf2x6_t'} } */ +void f___rvv_int8mf2x7_t () {__rvv_int8mf2x7_t t;} /* { dg-error {unknown type name '__rvv_int8mf2x7_t'} } */ +void f___rvv_uint8mf2x7_t () {__rvv_uint8mf2x7_t t;} /* { dg-error {unknown type name '__rvv_uint8mf2x7_t'} } */ +void f___rvv_int8mf2x8_t () {__rvv_int8mf2x8_t t;} /* { dg-error {unknown type name '__rvv_int8mf2x8_t'} } */ +void f___rvv_uint8mf2x8_t () {__rvv_uint8mf2x8_t t;} /* { dg-error {unknown type name '__rvv_uint8mf2x8_t'} } */ +void f___rvv_int8m1x2_t () {__rvv_int8m1x2_t t;} /* { dg-error {unknown type name '__rvv_int8m1x2_t'} } */ +void f___rvv_uint8m1x2_t () {__rvv_uint8m1x2_t t;} /* { dg-error {unknown type name '__rvv_uint8m1x2_t'} } */ +void f___rvv_int8m1x3_t () {__rvv_int8m1x3_t t;} /* { dg-error {unknown type name '__rvv_int8m1x3_t'} } */ +void f___rvv_uint8m1x3_t () {__rvv_uint8m1x3_t t;} /* { dg-error {unknown type name '__rvv_uint8m1x3_t'} } */ +void f___rvv_int8m1x4_t () {__rvv_int8m1x4_t t;} /* { dg-error {unknown type name '__rvv_int8m1x4_t'} } */ +void f___rvv_uint8m1x4_t () {__rvv_uint8m1x4_t t;} /* { dg-error {unknown type name '__rvv_uint8m1x4_t'} } */ +void f___rvv_int8m1x5_t () {__rvv_int8m1x5_t t;} /* { dg-error {unknown type name '__rvv_int8m1x5_t'} } */ +void f___rvv_uint8m1x5_t () {__rvv_uint8m1x5_t t;} /* { dg-error {unknown type name '__rvv_uint8m1x5_t'} } */ +void f___rvv_int8m1x6_t () {__rvv_int8m1x6_t t;} /* { dg-error {unknown type name '__rvv_int8m1x6_t'} } */ +void f___rvv_uint8m1x6_t () {__rvv_uint8m1x6_t t;} /* { dg-error {unknown type name '__rvv_uint8m1x6_t'} } */ +void f___rvv_int8m1x7_t () {__rvv_int8m1x7_t t;} /* { dg-error {unknown type name '__rvv_int8m1x7_t'} } */ +void f___rvv_uint8m1x7_t () {__rvv_uint8m1x7_t t;} /* { dg-error {unknown type name '__rvv_uint8m1x7_t'} } */ +void f___rvv_int8m1x8_t () {__rvv_int8m1x8_t t;} /* { dg-error {unknown type name '__rvv_int8m1x8_t'} } */ +void f___rvv_uint8m1x8_t () {__rvv_uint8m1x8_t t;} /* { dg-error {unknown type name '__rvv_uint8m1x8_t'} } */ +void f___rvv_int8m2x2_t () {__rvv_int8m2x2_t t;} /* { dg-error {unknown type name '__rvv_int8m2x2_t'} } */ +void f___rvv_uint8m2x2_t () {__rvv_uint8m2x2_t t;} /* { dg-error {unknown type name '__rvv_uint8m2x2_t'} } */ +void f___rvv_int8m2x3_t () {__rvv_int8m2x3_t t;} /* { dg-error {unknown type name '__rvv_int8m2x3_t'} } */ +void f___rvv_uint8m2x3_t () {__rvv_uint8m2x3_t t;} /* { dg-error {unknown type name '__rvv_uint8m2x3_t'} } */ +void f___rvv_int8m2x4_t () {__rvv_int8m2x4_t t;} /* { dg-error {unknown type name '__rvv_int8m2x4_t'} } */ +void f___rvv_uint8m2x4_t () {__rvv_uint8m2x4_t t;} /* { dg-error {unknown type name '__rvv_uint8m2x4_t'} } */ +void f___rvv_int8m4x2_t () {__rvv_int8m4x2_t t;} /* { dg-error {unknown type name '__rvv_int8m4x2_t'} } */ +void f___rvv_uint8m4x2_t () {__rvv_uint8m4x2_t t;} /* { dg-error {unknown type name '__rvv_uint8m4x2_t'} } */ +void f___rvv_int16mf4x2_t () {__rvv_int16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x2_t'} } */ +void f___rvv_uint16mf4x2_t () {__rvv_uint16mf4x2_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x2_t'} } */ +void f___rvv_int16mf4x3_t () {__rvv_int16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x3_t'} } */ +void f___rvv_uint16mf4x3_t () {__rvv_uint16mf4x3_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x3_t'} } */ +void f___rvv_int16mf4x4_t () {__rvv_int16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x4_t'} } */ +void f___rvv_uint16mf4x4_t () {__rvv_uint16mf4x4_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x4_t'} } */ +void f___rvv_int16mf4x5_t () {__rvv_int16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x5_t'} } */ +void f___rvv_uint16mf4x5_t () {__rvv_uint16mf4x5_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x5_t'} } */ +void f___rvv_int16mf4x6_t () {__rvv_int16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x6_t'} } */ +void f___rvv_uint16mf4x6_t () {__rvv_uint16mf4x6_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x6_t'} } */ +void f___rvv_int16mf4x7_t () {__rvv_int16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x7_t'} } */ +void f___rvv_uint16mf4x7_t () {__rvv_uint16mf4x7_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x7_t'} } */ +void f___rvv_int16mf4x8_t () {__rvv_int16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_int16mf4x8_t'} } */ +void f___rvv_uint16mf4x8_t () {__rvv_uint16mf4x8_t t;} /* { dg-error {unknown type name '__rvv_uint16mf4x8_t'} } */ +void f___rvv_int16mf2x2_t () {__rvv_int16mf2x2_t t;} /* { dg-error {unknown type name '__rvv_int16mf2x2_t'} } */ +void f___rvv_uint16mf2x2_t () {__rvv_uint16mf2x2_t t;} /* { dg-error {unknown type name '__rvv_uint16mf2x2_t'} } */ +void f___rvv_int16mf2x3_t () {__rvv_int16mf2x3_t t;} /* { dg-error {unknown type name '__rvv_int16mf2x3_t'} } */ +void f___rvv_uint16mf2x3_t () {__rvv_uint16mf2x3_t t;} /* { dg-error {unknown type name '__rvv_uint16mf2x3_t'} } */ +void f___rvv_int16mf2x4_t () {__rvv_int16mf2x4_t t;} /* { dg-error {unknown type name '__rvv_int16mf2x4_t'} } */ +void f___rvv_uint16mf2x4_t () {__rvv_uint16mf2x4_t t;} /* { dg-error {unknown type name '__rvv_uint16mf2x4_t'} } */ +void f___rvv_int16mf2x5_t () {__rvv_int16mf2x5_t t;} /* { dg-error {unknown type name '__rvv_int16mf2x5_t'} } */ +void f___rvv_uint16mf2x5_t () {__rvv_uint16mf2x5_t t;} /* { dg-error {unknown type name '__rvv_uint16mf2x5_t'} } */ +void f___rvv_int16mf2x6_t () {__rvv_int16mf2x6_t t;} /* { dg-error {unknown type name '__rvv_int16mf2x6_t'} } */ +void f___rvv_uint16mf2x6_t () {__rvv_uint16mf2x6_t t;} /* { dg-error {unknown type name '__rvv_uint16mf2x6_t'} } */ +void f___rvv_int16mf2x7_t () {__rvv_int16mf2x7_t t;} /* { dg-error {unknown type name '__rvv_int16mf2x7_t'} } */ +void f___rvv_uint16mf2x7_t () {__rvv_uint16mf2x7_t t;} /* { dg-error {unknown type name '__rvv_uint16mf2x7_t'} } */ +void f___rvv_int16mf2x8_t () {__rvv_int16mf2x8_t t;} /* { dg-error {unknown type name '__rvv_int16mf2x8_t'} } */ +void f___rvv_uint16mf2x8_t () {__rvv_uint16mf2x8_t t;} /* { dg-error {unknown type name '__rvv_uint16mf2x8_t'} } */ +void f___rvv_int16m1x2_t () {__rvv_int16m1x2_t t;} /* { dg-error {unknown type name '__rvv_int16m1x2_t'} } */ +void f___rvv_uint16m1x2_t () {__rvv_uint16m1x2_t t;} /* { dg-error {unknown type name '__rvv_uint16m1x2_t'} } */ +void f___rvv_int16m1x3_t () {__rvv_int16m1x3_t t;} /* { dg-error {unknown type name '__rvv_int16m1x3_t'} } */ +void f___rvv_uint16m1x3_t () {__rvv_uint16m1x3_t t;} /* { dg-error {unknown type name '__rvv_uint16m1x3_t'} } */ +void f___rvv_int16m1x4_t () {__rvv_int16m1x4_t t;} /* { dg-error {unknown type name '__rvv_int16m1x4_t'} } */ +void f___rvv_uint16m1x4_t () {__rvv_uint16m1x4_t t;} /* { dg-error {unknown type name '__rvv_uint16m1x4_t'} } */ +void f___rvv_int16m1x5_t () {__rvv_int16m1x5_t t;} /* { dg-error {unknown type name '__rvv_int16m1x5_t'} } */ +void f___rvv_uint16m1x5_t () {__rvv_uint16m1x5_t t;} /* { dg-error {unknown type name '__rvv_uint16m1x5_t'} } */ +void f___rvv_int16m1x6_t () {__rvv_int16m1x6_t t;} /* { dg-error {unknown type name '__rvv_int16m1x6_t'} } */ +void f___rvv_uint16m1x6_t () {__rvv_uint16m1x6_t t;} /* { dg-error {unknown type name '__rvv_uint16m1x6_t'} } */ +void f___rvv_int16m1x7_t () {__rvv_int16m1x7_t t;} /* { dg-error {unknown type name '__rvv_int16m1x7_t'} } */ +void f___rvv_uint16m1x7_t () {__rvv_uint16m1x7_t t;} /* { dg-error {unknown type name '__rvv_uint16m1x7_t'} } */ +void f___rvv_int16m1x8_t () {__rvv_int16m1x8_t t;} /* { dg-error {unknown type name '__rvv_int16m1x8_t'} } */ +void f___rvv_uint16m1x8_t () {__rvv_uint16m1x8_t t;} /* { dg-error {unknown type name '__rvv_uint16m1x8_t'} } */ +void f___rvv_int16m2x2_t () {__rvv_int16m2x2_t t;} /* { dg-error {unknown type name '__rvv_int16m2x2_t'} } */ +void f___rvv_uint16m2x2_t () {__rvv_uint16m2x2_t t;} /* { dg-error {unknown type name '__rvv_uint16m2x2_t'} } */ +void f___rvv_int16m2x3_t () {__rvv_int16m2x3_t t;} /* { dg-error {unknown type name '__rvv_int16m2x3_t'} } */ +void f___rvv_uint16m2x3_t () {__rvv_uint16m2x3_t t;} /* { dg-error {unknown type name '__rvv_uint16m2x3_t'} } */ +void f___rvv_int16m2x4_t () {__rvv_int16m2x4_t t;} /* { dg-error {unknown type name '__rvv_int16m2x4_t'} } */ +void f___rvv_uint16m2x4_t () {__rvv_uint16m2x4_t t;} /* { dg-error {unknown type name '__rvv_uint16m2x4_t'} } */ +void f___rvv_int16m4x2_t () {__rvv_int16m4x2_t t;} /* { dg-error {unknown type name '__rvv_int16m4x2_t'} } */ +void f___rvv_uint16m4x2_t () {__rvv_uint16m4x2_t t;} /* { dg-error {unknown type name '__rvv_uint16m4x2_t'} } */ +void f___rvv_int32mf2x2_t () {__rvv_int32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x2_t'} } */ +void f___rvv_uint32mf2x2_t () {__rvv_uint32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x2_t'} } */ +void f___rvv_int32mf2x3_t () {__rvv_int32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x3_t'} } */ +void f___rvv_uint32mf2x3_t () {__rvv_uint32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x3_t'} } */ +void f___rvv_int32mf2x4_t () {__rvv_int32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x4_t'} } */ +void f___rvv_uint32mf2x4_t () {__rvv_uint32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x4_t'} } */ +void f___rvv_int32mf2x5_t () {__rvv_int32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x5_t'} } */ +void f___rvv_uint32mf2x5_t () {__rvv_uint32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x5_t'} } */ +void f___rvv_int32mf2x6_t () {__rvv_int32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x6_t'} } */ +void f___rvv_uint32mf2x6_t () {__rvv_uint32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x6_t'} } */ +void f___rvv_int32mf2x7_t () {__rvv_int32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x7_t'} } */ +void f___rvv_uint32mf2x7_t () {__rvv_uint32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x7_t'} } */ +void f___rvv_int32mf2x8_t () {__rvv_int32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_int32mf2x8_t'} } */ +void f___rvv_uint32mf2x8_t () {__rvv_uint32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_uint32mf2x8_t'} } */ +void f___rvv_int32m1x2_t () {__rvv_int32m1x2_t t;} /* { dg-error {unknown type name '__rvv_int32m1x2_t'} } */ +void f___rvv_uint32m1x2_t () {__rvv_uint32m1x2_t t;} /* { dg-error {unknown type name '__rvv_uint32m1x2_t'} } */ +void f___rvv_int32m1x3_t () {__rvv_int32m1x3_t t;} /* { dg-error {unknown type name '__rvv_int32m1x3_t'} } */ +void f___rvv_uint32m1x3_t () {__rvv_uint32m1x3_t t;} /* { dg-error {unknown type name '__rvv_uint32m1x3_t'} } */ +void f___rvv_int32m1x4_t () {__rvv_int32m1x4_t t;} /* { dg-error {unknown type name '__rvv_int32m1x4_t'} } */ +void f___rvv_uint32m1x4_t () {__rvv_uint32m1x4_t t;} /* { dg-error {unknown type name '__rvv_uint32m1x4_t'} } */ +void f___rvv_int32m1x5_t () {__rvv_int32m1x5_t t;} /* { dg-error {unknown type name '__rvv_int32m1x5_t'} } */ +void f___rvv_uint32m1x5_t () {__rvv_uint32m1x5_t t;} /* { dg-error {unknown type name '__rvv_uint32m1x5_t'} } */ +void f___rvv_int32m1x6_t () {__rvv_int32m1x6_t t;} /* { dg-error {unknown type name '__rvv_int32m1x6_t'} } */ +void f___rvv_uint32m1x6_t () {__rvv_uint32m1x6_t t;} /* { dg-error {unknown type name '__rvv_uint32m1x6_t'} } */ +void f___rvv_int32m1x7_t () {__rvv_int32m1x7_t t;} /* { dg-error {unknown type name '__rvv_int32m1x7_t'} } */ +void f___rvv_uint32m1x7_t () {__rvv_uint32m1x7_t t;} /* { dg-error {unknown type name '__rvv_uint32m1x7_t'} } */ +void f___rvv_int32m1x8_t () {__rvv_int32m1x8_t t;} /* { dg-error {unknown type name '__rvv_int32m1x8_t'} } */ +void f___rvv_uint32m1x8_t () {__rvv_uint32m1x8_t t;} /* { dg-error {unknown type name '__rvv_uint32m1x8_t'} } */ +void f___rvv_int32m2x2_t () {__rvv_int32m2x2_t t;} /* { dg-error {unknown type name '__rvv_int32m2x2_t'} } */ +void f___rvv_uint32m2x2_t () {__rvv_uint32m2x2_t t;} /* { dg-error {unknown type name '__rvv_uint32m2x2_t'} } */ +void f___rvv_int32m2x3_t () {__rvv_int32m2x3_t t;} /* { dg-error {unknown type name '__rvv_int32m2x3_t'} } */ +void f___rvv_uint32m2x3_t () {__rvv_uint32m2x3_t t;} /* { dg-error {unknown type name '__rvv_uint32m2x3_t'} } */ +void f___rvv_int32m2x4_t () {__rvv_int32m2x4_t t;} /* { dg-error {unknown type name '__rvv_int32m2x4_t'} } */ +void f___rvv_uint32m2x4_t () {__rvv_uint32m2x4_t t;} /* { dg-error {unknown type name '__rvv_uint32m2x4_t'} } */ +void f___rvv_int32m4x2_t () {__rvv_int32m4x2_t t;} /* { dg-error {unknown type name '__rvv_int32m4x2_t'} } */ +void f___rvv_uint32m4x2_t () {__rvv_uint32m4x2_t t;} /* { dg-error {unknown type name '__rvv_uint32m4x2_t'} } */ +void f___rvv_int64m1x2_t () {__rvv_int64m1x2_t t;} /* { dg-error {unknown type name '__rvv_int64m1x2_t'} } */ +void f___rvv_uint64m1x2_t () {__rvv_uint64m1x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x2_t'} } */ +void f___rvv_int64m1x3_t () {__rvv_int64m1x3_t t;} /* { dg-error {unknown type name '__rvv_int64m1x3_t'} } */ +void f___rvv_uint64m1x3_t () {__rvv_uint64m1x3_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x3_t'} } */ +void f___rvv_int64m1x4_t () {__rvv_int64m1x4_t t;} /* { dg-error {unknown type name '__rvv_int64m1x4_t'} } */ +void f___rvv_uint64m1x4_t () {__rvv_uint64m1x4_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x4_t'} } */ +void f___rvv_int64m1x5_t () {__rvv_int64m1x5_t t;} /* { dg-error {unknown type name '__rvv_int64m1x5_t'} } */ +void f___rvv_uint64m1x5_t () {__rvv_uint64m1x5_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x5_t'} } */ +void f___rvv_int64m1x6_t () {__rvv_int64m1x6_t t;} /* { dg-error {unknown type name '__rvv_int64m1x6_t'} } */ +void f___rvv_uint64m1x6_t () {__rvv_uint64m1x6_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x6_t'} } */ +void f___rvv_int64m1x7_t () {__rvv_int64m1x7_t t;} /* { dg-error {unknown type name '__rvv_int64m1x7_t'} } */ +void f___rvv_uint64m1x7_t () {__rvv_uint64m1x7_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x7_t'} } */ +void f___rvv_int64m1x8_t () {__rvv_int64m1x8_t t;} /* { dg-error {unknown type name '__rvv_int64m1x8_t'} } */ +void f___rvv_uint64m1x8_t () {__rvv_uint64m1x8_t t;} /* { dg-error {unknown type name '__rvv_uint64m1x8_t'} } */ +void f___rvv_int64m2x2_t () {__rvv_int64m2x2_t t;} /* { dg-error {unknown type name '__rvv_int64m2x2_t'} } */ +void f___rvv_uint64m2x2_t () {__rvv_uint64m2x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x2_t'} } */ +void f___rvv_int64m2x3_t () {__rvv_int64m2x3_t t;} /* { dg-error {unknown type name '__rvv_int64m2x3_t'} } */ +void f___rvv_uint64m2x3_t () {__rvv_uint64m2x3_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x3_t'} } */ +void f___rvv_int64m2x4_t () {__rvv_int64m2x4_t t;} /* { dg-error {unknown type name '__rvv_int64m2x4_t'} } */ +void f___rvv_uint64m2x4_t () {__rvv_uint64m2x4_t t;} /* { dg-error {unknown type name '__rvv_uint64m2x4_t'} } */ +void f___rvv_int64m4x2_t () {__rvv_int64m4x2_t t;} /* { dg-error {unknown type name '__rvv_int64m4x2_t'} } */ +void f___rvv_uint64m4x2_t () {__rvv_uint64m4x2_t t;} /* { dg-error {unknown type name '__rvv_uint64m4x2_t'} } */ +void f___rvv_float32mf2x2_t () {__rvv_float32mf2x2_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x2_t'} } */ +void f___rvv_float32mf2x3_t () {__rvv_float32mf2x3_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x3_t'} } */ +void f___rvv_float32mf2x4_t () {__rvv_float32mf2x4_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x4_t'} } */ +void f___rvv_float32mf2x5_t () {__rvv_float32mf2x5_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x5_t'} } */ +void f___rvv_float32mf2x6_t () {__rvv_float32mf2x6_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x6_t'} } */ +void f___rvv_float32mf2x7_t () {__rvv_float32mf2x7_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x7_t'} } */ +void f___rvv_float32mf2x8_t () {__rvv_float32mf2x8_t t;} /* { dg-error {unknown type name '__rvv_float32mf2x8_t'} } */ +void f___rvv_float32m1x2_t () {__rvv_float32m1x2_t t;} /* { dg-error {unknown type name '__rvv_float32m1x2_t'} } */ +void f___rvv_float32m1x3_t () {__rvv_float32m1x3_t t;} /* { dg-error {unknown type name '__rvv_float32m1x3_t'} } */ +void f___rvv_float32m1x4_t () {__rvv_float32m1x4_t t;} /* { dg-error {unknown type name '__rvv_float32m1x4_t'} } */ +void f___rvv_float32m1x5_t () {__rvv_float32m1x5_t t;} /* { dg-error {unknown type name '__rvv_float32m1x5_t'} } */ +void f___rvv_float32m1x6_t () {__rvv_float32m1x6_t t;} /* { dg-error {unknown type name '__rvv_float32m1x6_t'} } */ +void f___rvv_float32m1x7_t () {__rvv_float32m1x7_t t;} /* { dg-error {unknown type name '__rvv_float32m1x7_t'} } */ +void f___rvv_float32m1x8_t () {__rvv_float32m1x8_t t;} /* { dg-error {unknown type name '__rvv_float32m1x8_t'} } */ +void f___rvv_float32m2x2_t () {__rvv_float32m2x2_t t;} /* { dg-error {unknown type name '__rvv_float32m2x2_t'} } */ +void f___rvv_float32m2x3_t () {__rvv_float32m2x3_t t;} /* { dg-error {unknown type name '__rvv_float32m2x3_t'} } */ +void f___rvv_float32m2x4_t () {__rvv_float32m2x4_t t;} /* { dg-error {unknown type name '__rvv_float32m2x4_t'} } */ +void f___rvv_float32m4x2_t () {__rvv_float32m4x2_t t;} /* { dg-error {unknown type name '__rvv_float32m4x2_t'} } */ +void f___rvv_float64m1x2_t () {__rvv_float64m1x2_t t;} /* { dg-error {unknown type name '__rvv_float64m1x2_t'} } */ +void f___rvv_float64m1x3_t () {__rvv_float64m1x3_t t;} /* { dg-error {unknown type name '__rvv_float64m1x3_t'} } */ +void f___rvv_float64m1x4_t () {__rvv_float64m1x4_t t;} /* { dg-error {unknown type name '__rvv_float64m1x4_t'} } */ +void f___rvv_float64m1x5_t () {__rvv_float64m1x5_t t;} /* { dg-error {unknown type name '__rvv_float64m1x5_t'} } */ +void f___rvv_float64m1x6_t () {__rvv_float64m1x6_t t;} /* { dg-error {unknown type name '__rvv_float64m1x6_t'} } */ +void f___rvv_float64m1x7_t () {__rvv_float64m1x7_t t;} /* { dg-error {unknown type name '__rvv_float64m1x7_t'} } */ +void f___rvv_float64m1x8_t () {__rvv_float64m1x8_t t;} /* { dg-error {unknown type name '__rvv_float64m1x8_t'} } */ +void f___rvv_float64m2x2_t () {__rvv_float64m2x2_t t;} /* { dg-error {unknown type name '__rvv_float64m2x2_t'} } */ +void f___rvv_float64m2x3_t () {__rvv_float64m2x3_t t;} /* { dg-error {unknown type name '__rvv_float64m2x3_t'} } */ +void f___rvv_float64m2x4_t () {__rvv_float64m2x4_t t;} /* { dg-error {unknown type name '__rvv_float64m2x4_t'} } */ +void f___rvv_float64m4x2_t () {__rvv_float64m4x2_t t;} /* { dg-error {unknown type name '__rvv_float64m4x2_t'} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-10.c new file mode 100644 index 00000000000..fdc28c77426 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-10.c @@ -0,0 +1,206 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc_zve64f -mabi=ilp32d" } */ + +#include "riscv_vector.h" + +void f_vint8mf8x2_t () {vint8mf8x2_t t;} +void f_vuint8mf8x2_t () {vuint8mf8x2_t t;} +void f_vint8mf8x3_t () {vint8mf8x3_t t;} +void f_vuint8mf8x3_t () {vuint8mf8x3_t t;} +void f_vint8mf8x4_t () {vint8mf8x4_t t;} +void f_vuint8mf8x4_t () {vuint8mf8x4_t t;} +void f_vint8mf8x5_t () {vint8mf8x5_t t;} +void f_vuint8mf8x5_t () {vuint8mf8x5_t t;} +void f_vint8mf8x6_t () {vint8mf8x6_t t;} +void f_vuint8mf8x6_t () {vuint8mf8x6_t t;} +void f_vint8mf8x7_t () {vint8mf8x7_t t;} +void f_vuint8mf8x7_t () {vuint8mf8x7_t t;} +void f_vint8mf8x8_t () {vint8mf8x8_t t;} +void f_vuint8mf8x8_t () {vuint8mf8x8_t t;} +void f_vint8mf4x2_t () {vint8mf4x2_t t;} +void f_vuint8mf4x2_t () {vuint8mf4x2_t t;} +void f_vint8mf4x3_t () {vint8mf4x3_t t;} +void f_vuint8mf4x3_t () {vuint8mf4x3_t t;} +void f_vint8mf4x4_t () {vint8mf4x4_t t;} +void f_vuint8mf4x4_t () {vuint8mf4x4_t t;} +void f_vint8mf4x5_t () {vint8mf4x5_t t;} +void f_vuint8mf4x5_t () {vuint8mf4x5_t t;} +void f_vint8mf4x6_t () {vint8mf4x6_t t;} +void f_vuint8mf4x6_t () {vuint8mf4x6_t t;} +void f_vint8mf4x7_t () {vint8mf4x7_t t;} +void f_vuint8mf4x7_t () {vuint8mf4x7_t t;} +void f_vint8mf4x8_t () {vint8mf4x8_t t;} +void f_vuint8mf4x8_t () {vuint8mf4x8_t t;} +void f_vint8mf2x2_t () {vint8mf2x2_t t;} +void f_vuint8mf2x2_t () {vuint8mf2x2_t t;} +void f_vint8mf2x3_t () {vint8mf2x3_t t;} +void f_vuint8mf2x3_t () {vuint8mf2x3_t t;} +void f_vint8mf2x4_t () {vint8mf2x4_t t;} +void f_vuint8mf2x4_t () {vuint8mf2x4_t t;} +void f_vint8mf2x5_t () {vint8mf2x5_t t;} +void f_vuint8mf2x5_t () {vuint8mf2x5_t t;} +void f_vint8mf2x6_t () {vint8mf2x6_t t;} +void f_vuint8mf2x6_t () {vuint8mf2x6_t t;} +void f_vint8mf2x7_t () {vint8mf2x7_t t;} +void f_vuint8mf2x7_t () {vuint8mf2x7_t t;} +void f_vint8mf2x8_t () {vint8mf2x8_t t;} +void f_vuint8mf2x8_t () {vuint8mf2x8_t t;} +void f_vint8m1x2_t () {vint8m1x2_t t;} +void f_vuint8m1x2_t () {vuint8m1x2_t t;} +void f_vint8m1x3_t () {vint8m1x3_t t;} +void f_vuint8m1x3_t () {vuint8m1x3_t t;} +void f_vint8m1x4_t () {vint8m1x4_t t;} +void f_vuint8m1x4_t () {vuint8m1x4_t t;} +void f_vint8m1x5_t () {vint8m1x5_t t;} +void f_vuint8m1x5_t () {vuint8m1x5_t t;} +void f_vint8m1x6_t () {vint8m1x6_t t;} +void f_vuint8m1x6_t () {vuint8m1x6_t t;} +void f_vint8m1x7_t () {vint8m1x7_t t;} +void f_vuint8m1x7_t () {vuint8m1x7_t t;} +void f_vint8m1x8_t () {vint8m1x8_t t;} +void f_vuint8m1x8_t () {vuint8m1x8_t t;} +void f_vint8m2x2_t () {vint8m2x2_t t;} +void f_vuint8m2x2_t () {vuint8m2x2_t t;} +void f_vint8m2x3_t () {vint8m2x3_t t;} +void f_vuint8m2x3_t () {vuint8m2x3_t t;} +void f_vint8m2x4_t () {vint8m2x4_t t;} +void f_vuint8m2x4_t () {vuint8m2x4_t t;} +void f_vint8m4x2_t () {vint8m4x2_t t;} +void f_vuint8m4x2_t () {vuint8m4x2_t t;} +void f_vint16mf4x2_t () {vint16mf4x2_t t;} +void f_vuint16mf4x2_t () {vuint16mf4x2_t t;} +void f_vint16mf4x3_t () {vint16mf4x3_t t;} +void f_vuint16mf4x3_t () {vuint16mf4x3_t t;} +void f_vint16mf4x4_t () {vint16mf4x4_t t;} +void f_vuint16mf4x4_t () {vuint16mf4x4_t t;} +void f_vint16mf4x5_t () {vint16mf4x5_t t;} +void f_vuint16mf4x5_t () {vuint16mf4x5_t t;} +void f_vint16mf4x6_t () {vint16mf4x6_t t;} +void f_vuint16mf4x6_t () {vuint16mf4x6_t t;} +void f_vint16mf4x7_t () {vint16mf4x7_t t;} +void f_vuint16mf4x7_t () {vuint16mf4x7_t t;} +void f_vint16mf4x8_t () {vint16mf4x8_t t;} +void f_vuint16mf4x8_t () {vuint16mf4x8_t t;} +void f_vint16mf2x2_t () {vint16mf2x2_t t;} +void f_vuint16mf2x2_t () {vuint16mf2x2_t t;} +void f_vint16mf2x3_t () {vint16mf2x3_t t;} +void f_vuint16mf2x3_t () {vuint16mf2x3_t t;} +void f_vint16mf2x4_t () {vint16mf2x4_t t;} +void f_vuint16mf2x4_t () {vuint16mf2x4_t t;} +void f_vint16mf2x5_t () {vint16mf2x5_t t;} +void f_vuint16mf2x5_t () {vuint16mf2x5_t t;} +void f_vint16mf2x6_t () {vint16mf2x6_t t;} +void f_vuint16mf2x6_t () {vuint16mf2x6_t t;} +void f_vint16mf2x7_t () {vint16mf2x7_t t;} +void f_vuint16mf2x7_t () {vuint16mf2x7_t t;} +void f_vint16mf2x8_t () {vint16mf2x8_t t;} +void f_vuint16mf2x8_t () {vuint16mf2x8_t t;} +void f_vint16m1x2_t () {vint16m1x2_t t;} +void f_vuint16m1x2_t () {vuint16m1x2_t t;} +void f_vint16m1x3_t () {vint16m1x3_t t;} +void f_vuint16m1x3_t () {vuint16m1x3_t t;} +void f_vint16m1x4_t () {vint16m1x4_t t;} +void f_vuint16m1x4_t () {vuint16m1x4_t t;} +void f_vint16m1x5_t () {vint16m1x5_t t;} +void f_vuint16m1x5_t () {vuint16m1x5_t t;} +void f_vint16m1x6_t () {vint16m1x6_t t;} +void f_vuint16m1x6_t () {vuint16m1x6_t t;} +void f_vint16m1x7_t () {vint16m1x7_t t;} +void f_vuint16m1x7_t () {vuint16m1x7_t t;} +void f_vint16m1x8_t () {vint16m1x8_t t;} +void f_vuint16m1x8_t () {vuint16m1x8_t t;} +void f_vint16m2x2_t () {vint16m2x2_t t;} +void f_vuint16m2x2_t () {vuint16m2x2_t t;} +void f_vint16m2x3_t () {vint16m2x3_t t;} +void f_vuint16m2x3_t () {vuint16m2x3_t t;} +void f_vint16m2x4_t () {vint16m2x4_t t;} +void f_vuint16m2x4_t () {vuint16m2x4_t t;} +void f_vint16m4x2_t () {vint16m4x2_t t;} +void f_vuint16m4x2_t () {vuint16m4x2_t t;} +void f_vint32mf2x2_t () {vint32mf2x2_t t;} +void f_vuint32mf2x2_t () {vuint32mf2x2_t t;} +void f_vint32mf2x3_t () {vint32mf2x3_t t;} +void f_vuint32mf2x3_t () {vuint32mf2x3_t t;} +void f_vint32mf2x4_t () {vint32mf2x4_t t;} +void f_vuint32mf2x4_t () {vuint32mf2x4_t t;} +void f_vint32mf2x5_t () {vint32mf2x5_t t;} +void f_vuint32mf2x5_t () {vuint32mf2x5_t t;} +void f_vint32mf2x6_t () {vint32mf2x6_t t;} +void f_vuint32mf2x6_t () {vuint32mf2x6_t t;} +void f_vint32mf2x7_t () {vint32mf2x7_t t;} +void f_vuint32mf2x7_t () {vuint32mf2x7_t t;} +void f_vint32mf2x8_t () {vint32mf2x8_t t;} +void f_vuint32mf2x8_t () {vuint32mf2x8_t t;} +void f_vint32m1x2_t () {vint32m1x2_t t;} +void f_vuint32m1x2_t () {vuint32m1x2_t t;} +void f_vint32m1x3_t () {vint32m1x3_t t;} +void f_vuint32m1x3_t () {vuint32m1x3_t t;} +void f_vint32m1x4_t () {vint32m1x4_t t;} +void f_vuint32m1x4_t () {vuint32m1x4_t t;} +void f_vint32m1x5_t () {vint32m1x5_t t;} +void f_vuint32m1x5_t () {vuint32m1x5_t t;} +void f_vint32m1x6_t () {vint32m1x6_t t;} +void f_vuint32m1x6_t () {vuint32m1x6_t t;} +void f_vint32m1x7_t () {vint32m1x7_t t;} +void f_vuint32m1x7_t () {vuint32m1x7_t t;} +void f_vint32m1x8_t () {vint32m1x8_t t;} +void f_vuint32m1x8_t () {vuint32m1x8_t t;} +void f_vint32m2x2_t () {vint32m2x2_t t;} +void f_vuint32m2x2_t () {vuint32m2x2_t t;} +void f_vint32m2x3_t () {vint32m2x3_t t;} +void f_vuint32m2x3_t () {vuint32m2x3_t t;} +void f_vint32m2x4_t () {vint32m2x4_t t;} +void f_vuint32m2x4_t () {vuint32m2x4_t t;} +void f_vint32m4x2_t () {vint32m4x2_t t;} +void f_vuint32m4x2_t () {vuint32m4x2_t t;} +void f_vint64m1x2_t () {vint64m1x2_t t;} +void f_vuint64m1x2_t () {vuint64m1x2_t t;} +void f_vint64m1x3_t () {vint64m1x3_t t;} +void f_vuint64m1x3_t () {vuint64m1x3_t t;} +void f_vint64m1x4_t () {vint64m1x4_t t;} +void f_vuint64m1x4_t () {vuint64m1x4_t t;} +void f_vint64m1x5_t () {vint64m1x5_t t;} +void f_vuint64m1x5_t () {vuint64m1x5_t t;} +void f_vint64m1x6_t () {vint64m1x6_t t;} +void f_vuint64m1x6_t () {vuint64m1x6_t t;} +void f_vint64m1x7_t () {vint64m1x7_t t;} +void f_vuint64m1x7_t () {vuint64m1x7_t t;} +void f_vint64m1x8_t () {vint64m1x8_t t;} +void f_vuint64m1x8_t () {vuint64m1x8_t t;} +void f_vint64m2x2_t () {vint64m2x2_t t;} +void f_vuint64m2x2_t () {vuint64m2x2_t t;} +void f_vint64m2x3_t () {vint64m2x3_t t;} +void f_vuint64m2x3_t () {vuint64m2x3_t t;} +void f_vint64m2x4_t () {vint64m2x4_t t;} +void f_vuint64m2x4_t () {vuint64m2x4_t t;} +void f_vint64m4x2_t () {vint64m4x2_t t;} +void f_vuint64m4x2_t () {vuint64m4x2_t t;} +void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} +void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} +void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} +void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;} +void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;} +void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;} +void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;} +void f_vfloat32m1x2_t () {vfloat32m1x2_t t;} +void f_vfloat32m1x3_t () {vfloat32m1x3_t t;} +void f_vfloat32m1x4_t () {vfloat32m1x4_t t;} +void f_vfloat32m1x5_t () {vfloat32m1x5_t t;} +void f_vfloat32m1x6_t () {vfloat32m1x6_t t;} +void f_vfloat32m1x7_t () {vfloat32m1x7_t t;} +void f_vfloat32m1x8_t () {vfloat32m1x8_t t;} +void f_vfloat32m2x2_t () {vfloat32m2x2_t t;} +void f_vfloat32m2x3_t () {vfloat32m2x3_t t;} +void f_vfloat32m2x4_t () {vfloat32m2x4_t t;} +void f_vfloat32m4x2_t () {vfloat32m4x2_t t;} +void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} /* { dg-error {unknown type name 'vfloat64m1x2_t'} } */ +void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} /* { dg-error {unknown type name 'vfloat64m1x3_t'} } */ +void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} /* { dg-error {unknown type name 'vfloat64m1x4_t'} } */ +void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} /* { dg-error {unknown type name 'vfloat64m1x5_t'} } */ +void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} /* { dg-error {unknown type name 'vfloat64m1x6_t'} } */ +void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} /* { dg-error {unknown type name 'vfloat64m1x7_t'} } */ +void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} /* { dg-error {unknown type name 'vfloat64m1x8_t'} } */ +void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} /* { dg-error {unknown type name 'vfloat64m2x2_t'} } */ +void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} /* { dg-error {unknown type name 'vfloat64m2x3_t'} } */ +void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} /* { dg-error {unknown type name 'vfloat64m2x4_t'} } */ +void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} /* { dg-error {unknown type name 'vfloat64m4x2_t'} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-11.c new file mode 100644 index 00000000000..901d2edcbc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-11.c @@ -0,0 +1,206 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc_zve64d -mabi=ilp32d" } */ + +#include "riscv_vector.h" + +void f_vint8mf8x2_t () {vint8mf8x2_t t;} +void f_vuint8mf8x2_t () {vuint8mf8x2_t t;} +void f_vint8mf8x3_t () {vint8mf8x3_t t;} +void f_vuint8mf8x3_t () {vuint8mf8x3_t t;} +void f_vint8mf8x4_t () {vint8mf8x4_t t;} +void f_vuint8mf8x4_t () {vuint8mf8x4_t t;} +void f_vint8mf8x5_t () {vint8mf8x5_t t;} +void f_vuint8mf8x5_t () {vuint8mf8x5_t t;} +void f_vint8mf8x6_t () {vint8mf8x6_t t;} +void f_vuint8mf8x6_t () {vuint8mf8x6_t t;} +void f_vint8mf8x7_t () {vint8mf8x7_t t;} +void f_vuint8mf8x7_t () {vuint8mf8x7_t t;} +void f_vint8mf8x8_t () {vint8mf8x8_t t;} +void f_vuint8mf8x8_t () {vuint8mf8x8_t t;} +void f_vint8mf4x2_t () {vint8mf4x2_t t;} +void f_vuint8mf4x2_t () {vuint8mf4x2_t t;} +void f_vint8mf4x3_t () {vint8mf4x3_t t;} +void f_vuint8mf4x3_t () {vuint8mf4x3_t t;} +void f_vint8mf4x4_t () {vint8mf4x4_t t;} +void f_vuint8mf4x4_t () {vuint8mf4x4_t t;} +void f_vint8mf4x5_t () {vint8mf4x5_t t;} +void f_vuint8mf4x5_t () {vuint8mf4x5_t t;} +void f_vint8mf4x6_t () {vint8mf4x6_t t;} +void f_vuint8mf4x6_t () {vuint8mf4x6_t t;} +void f_vint8mf4x7_t () {vint8mf4x7_t t;} +void f_vuint8mf4x7_t () {vuint8mf4x7_t t;} +void f_vint8mf4x8_t () {vint8mf4x8_t t;} +void f_vuint8mf4x8_t () {vuint8mf4x8_t t;} +void f_vint8mf2x2_t () {vint8mf2x2_t t;} +void f_vuint8mf2x2_t () {vuint8mf2x2_t t;} +void f_vint8mf2x3_t () {vint8mf2x3_t t;} +void f_vuint8mf2x3_t () {vuint8mf2x3_t t;} +void f_vint8mf2x4_t () {vint8mf2x4_t t;} +void f_vuint8mf2x4_t () {vuint8mf2x4_t t;} +void f_vint8mf2x5_t () {vint8mf2x5_t t;} +void f_vuint8mf2x5_t () {vuint8mf2x5_t t;} +void f_vint8mf2x6_t () {vint8mf2x6_t t;} +void f_vuint8mf2x6_t () {vuint8mf2x6_t t;} +void f_vint8mf2x7_t () {vint8mf2x7_t t;} +void f_vuint8mf2x7_t () {vuint8mf2x7_t t;} +void f_vint8mf2x8_t () {vint8mf2x8_t t;} +void f_vuint8mf2x8_t () {vuint8mf2x8_t t;} +void f_vint8m1x2_t () {vint8m1x2_t t;} +void f_vuint8m1x2_t () {vuint8m1x2_t t;} +void f_vint8m1x3_t () {vint8m1x3_t t;} +void f_vuint8m1x3_t () {vuint8m1x3_t t;} +void f_vint8m1x4_t () {vint8m1x4_t t;} +void f_vuint8m1x4_t () {vuint8m1x4_t t;} +void f_vint8m1x5_t () {vint8m1x5_t t;} +void f_vuint8m1x5_t () {vuint8m1x5_t t;} +void f_vint8m1x6_t () {vint8m1x6_t t;} +void f_vuint8m1x6_t () {vuint8m1x6_t t;} +void f_vint8m1x7_t () {vint8m1x7_t t;} +void f_vuint8m1x7_t () {vuint8m1x7_t t;} +void f_vint8m1x8_t () {vint8m1x8_t t;} +void f_vuint8m1x8_t () {vuint8m1x8_t t;} +void f_vint8m2x2_t () {vint8m2x2_t t;} +void f_vuint8m2x2_t () {vuint8m2x2_t t;} +void f_vint8m2x3_t () {vint8m2x3_t t;} +void f_vuint8m2x3_t () {vuint8m2x3_t t;} +void f_vint8m2x4_t () {vint8m2x4_t t;} +void f_vuint8m2x4_t () {vuint8m2x4_t t;} +void f_vint8m4x2_t () {vint8m4x2_t t;} +void f_vuint8m4x2_t () {vuint8m4x2_t t;} +void f_vint16mf4x2_t () {vint16mf4x2_t t;} +void f_vuint16mf4x2_t () {vuint16mf4x2_t t;} +void f_vint16mf4x3_t () {vint16mf4x3_t t;} +void f_vuint16mf4x3_t () {vuint16mf4x3_t t;} +void f_vint16mf4x4_t () {vint16mf4x4_t t;} +void f_vuint16mf4x4_t () {vuint16mf4x4_t t;} +void f_vint16mf4x5_t () {vint16mf4x5_t t;} +void f_vuint16mf4x5_t () {vuint16mf4x5_t t;} +void f_vint16mf4x6_t () {vint16mf4x6_t t;} +void f_vuint16mf4x6_t () {vuint16mf4x6_t t;} +void f_vint16mf4x7_t () {vint16mf4x7_t t;} +void f_vuint16mf4x7_t () {vuint16mf4x7_t t;} +void f_vint16mf4x8_t () {vint16mf4x8_t t;} +void f_vuint16mf4x8_t () {vuint16mf4x8_t t;} +void f_vint16mf2x2_t () {vint16mf2x2_t t;} +void f_vuint16mf2x2_t () {vuint16mf2x2_t t;} +void f_vint16mf2x3_t () {vint16mf2x3_t t;} +void f_vuint16mf2x3_t () {vuint16mf2x3_t t;} +void f_vint16mf2x4_t () {vint16mf2x4_t t;} +void f_vuint16mf2x4_t () {vuint16mf2x4_t t;} +void f_vint16mf2x5_t () {vint16mf2x5_t t;} +void f_vuint16mf2x5_t () {vuint16mf2x5_t t;} +void f_vint16mf2x6_t () {vint16mf2x6_t t;} +void f_vuint16mf2x6_t () {vuint16mf2x6_t t;} +void f_vint16mf2x7_t () {vint16mf2x7_t t;} +void f_vuint16mf2x7_t () {vuint16mf2x7_t t;} +void f_vint16mf2x8_t () {vint16mf2x8_t t;} +void f_vuint16mf2x8_t () {vuint16mf2x8_t t;} +void f_vint16m1x2_t () {vint16m1x2_t t;} +void f_vuint16m1x2_t () {vuint16m1x2_t t;} +void f_vint16m1x3_t () {vint16m1x3_t t;} +void f_vuint16m1x3_t () {vuint16m1x3_t t;} +void f_vint16m1x4_t () {vint16m1x4_t t;} +void f_vuint16m1x4_t () {vuint16m1x4_t t;} +void f_vint16m1x5_t () {vint16m1x5_t t;} +void f_vuint16m1x5_t () {vuint16m1x5_t t;} +void f_vint16m1x6_t () {vint16m1x6_t t;} +void f_vuint16m1x6_t () {vuint16m1x6_t t;} +void f_vint16m1x7_t () {vint16m1x7_t t;} +void f_vuint16m1x7_t () {vuint16m1x7_t t;} +void f_vint16m1x8_t () {vint16m1x8_t t;} +void f_vuint16m1x8_t () {vuint16m1x8_t t;} +void f_vint16m2x2_t () {vint16m2x2_t t;} +void f_vuint16m2x2_t () {vuint16m2x2_t t;} +void f_vint16m2x3_t () {vint16m2x3_t t;} +void f_vuint16m2x3_t () {vuint16m2x3_t t;} +void f_vint16m2x4_t () {vint16m2x4_t t;} +void f_vuint16m2x4_t () {vuint16m2x4_t t;} +void f_vint16m4x2_t () {vint16m4x2_t t;} +void f_vuint16m4x2_t () {vuint16m4x2_t t;} +void f_vint32mf2x2_t () {vint32mf2x2_t t;} +void f_vuint32mf2x2_t () {vuint32mf2x2_t t;} +void f_vint32mf2x3_t () {vint32mf2x3_t t;} +void f_vuint32mf2x3_t () {vuint32mf2x3_t t;} +void f_vint32mf2x4_t () {vint32mf2x4_t t;} +void f_vuint32mf2x4_t () {vuint32mf2x4_t t;} +void f_vint32mf2x5_t () {vint32mf2x5_t t;} +void f_vuint32mf2x5_t () {vuint32mf2x5_t t;} +void f_vint32mf2x6_t () {vint32mf2x6_t t;} +void f_vuint32mf2x6_t () {vuint32mf2x6_t t;} +void f_vint32mf2x7_t () {vint32mf2x7_t t;} +void f_vuint32mf2x7_t () {vuint32mf2x7_t t;} +void f_vint32mf2x8_t () {vint32mf2x8_t t;} +void f_vuint32mf2x8_t () {vuint32mf2x8_t t;} +void f_vint32m1x2_t () {vint32m1x2_t t;} +void f_vuint32m1x2_t () {vuint32m1x2_t t;} +void f_vint32m1x3_t () {vint32m1x3_t t;} +void f_vuint32m1x3_t () {vuint32m1x3_t t;} +void f_vint32m1x4_t () {vint32m1x4_t t;} +void f_vuint32m1x4_t () {vuint32m1x4_t t;} +void f_vint32m1x5_t () {vint32m1x5_t t;} +void f_vuint32m1x5_t () {vuint32m1x5_t t;} +void f_vint32m1x6_t () {vint32m1x6_t t;} +void f_vuint32m1x6_t () {vuint32m1x6_t t;} +void f_vint32m1x7_t () {vint32m1x7_t t;} +void f_vuint32m1x7_t () {vuint32m1x7_t t;} +void f_vint32m1x8_t () {vint32m1x8_t t;} +void f_vuint32m1x8_t () {vuint32m1x8_t t;} +void f_vint32m2x2_t () {vint32m2x2_t t;} +void f_vuint32m2x2_t () {vuint32m2x2_t t;} +void f_vint32m2x3_t () {vint32m2x3_t t;} +void f_vuint32m2x3_t () {vuint32m2x3_t t;} +void f_vint32m2x4_t () {vint32m2x4_t t;} +void f_vuint32m2x4_t () {vuint32m2x4_t t;} +void f_vint32m4x2_t () {vint32m4x2_t t;} +void f_vuint32m4x2_t () {vuint32m4x2_t t;} +void f_vint64m1x2_t () {vint64m1x2_t t;} +void f_vuint64m1x2_t () {vuint64m1x2_t t;} +void f_vint64m1x3_t () {vint64m1x3_t t;} +void f_vuint64m1x3_t () {vuint64m1x3_t t;} +void f_vint64m1x4_t () {vint64m1x4_t t;} +void f_vuint64m1x4_t () {vuint64m1x4_t t;} +void f_vint64m1x5_t () {vint64m1x5_t t;} +void f_vuint64m1x5_t () {vuint64m1x5_t t;} +void f_vint64m1x6_t () {vint64m1x6_t t;} +void f_vuint64m1x6_t () {vuint64m1x6_t t;} +void f_vint64m1x7_t () {vint64m1x7_t t;} +void f_vuint64m1x7_t () {vuint64m1x7_t t;} +void f_vint64m1x8_t () {vint64m1x8_t t;} +void f_vuint64m1x8_t () {vuint64m1x8_t t;} +void f_vint64m2x2_t () {vint64m2x2_t t;} +void f_vuint64m2x2_t () {vuint64m2x2_t t;} +void f_vint64m2x3_t () {vint64m2x3_t t;} +void f_vuint64m2x3_t () {vuint64m2x3_t t;} +void f_vint64m2x4_t () {vint64m2x4_t t;} +void f_vuint64m2x4_t () {vuint64m2x4_t t;} +void f_vint64m4x2_t () {vint64m4x2_t t;} +void f_vuint64m4x2_t () {vuint64m4x2_t t;} +void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} +void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} +void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} +void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;} +void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;} +void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;} +void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;} +void f_vfloat32m1x2_t () {vfloat32m1x2_t t;} +void f_vfloat32m1x3_t () {vfloat32m1x3_t t;} +void f_vfloat32m1x4_t () {vfloat32m1x4_t t;} +void f_vfloat32m1x5_t () {vfloat32m1x5_t t;} +void f_vfloat32m1x6_t () {vfloat32m1x6_t t;} +void f_vfloat32m1x7_t () {vfloat32m1x7_t t;} +void f_vfloat32m1x8_t () {vfloat32m1x8_t t;} +void f_vfloat32m2x2_t () {vfloat32m2x2_t t;} +void f_vfloat32m2x3_t () {vfloat32m2x3_t t;} +void f_vfloat32m2x4_t () {vfloat32m2x4_t t;} +void f_vfloat32m4x2_t () {vfloat32m4x2_t t;} +void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} +void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} +void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} +void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} +void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} +void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} +void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} +void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} +void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} +void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} +void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-12.c new file mode 100644 index 00000000000..332ff7627b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-12.c @@ -0,0 +1,206 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc_zve32x -mabi=ilp32d" } */ + +#include "riscv_vector.h" + +void f_vint8mf8x2_t () {vint8mf8x2_t t;} /* { dg-error {unknown type name 'vint8mf8x2_t'} } */ +void f_vuint8mf8x2_t () {vuint8mf8x2_t t;} /* { dg-error {unknown type name 'vuint8mf8x2_t'} } */ +void f_vint8mf8x3_t () {vint8mf8x3_t t;} /* { dg-error {unknown type name 'vint8mf8x3_t'} } */ +void f_vuint8mf8x3_t () {vuint8mf8x3_t t;} /* { dg-error {unknown type name 'vuint8mf8x3_t'} } */ +void f_vint8mf8x4_t () {vint8mf8x4_t t;} /* { dg-error {unknown type name 'vint8mf8x4_t'} } */ +void f_vuint8mf8x4_t () {vuint8mf8x4_t t;} /* { dg-error {unknown type name 'vuint8mf8x4_t'} } */ +void f_vint8mf8x5_t () {vint8mf8x5_t t;} /* { dg-error {unknown type name 'vint8mf8x5_t'} } */ +void f_vuint8mf8x5_t () {vuint8mf8x5_t t;} /* { dg-error {unknown type name 'vuint8mf8x5_t'} } */ +void f_vint8mf8x6_t () {vint8mf8x6_t t;} /* { dg-error {unknown type name 'vint8mf8x6_t'} } */ +void f_vuint8mf8x6_t () {vuint8mf8x6_t t;} /* { dg-error {unknown type name 'vuint8mf8x6_t'} } */ +void f_vint8mf8x7_t () {vint8mf8x7_t t;} /* { dg-error {unknown type name 'vint8mf8x7_t'} } */ +void f_vuint8mf8x7_t () {vuint8mf8x7_t t;} /* { dg-error {unknown type name 'vuint8mf8x7_t'} } */ +void f_vint8mf8x8_t () {vint8mf8x8_t t;} /* { dg-error {unknown type name 'vint8mf8x8_t'} } */ +void f_vuint8mf8x8_t () {vuint8mf8x8_t t;} /* { dg-error {unknown type name 'vuint8mf8x8_t'} } */ +void f_vint8mf4x2_t () {vint8mf4x2_t t;} +void f_vuint8mf4x2_t () {vuint8mf4x2_t t;} +void f_vint8mf4x3_t () {vint8mf4x3_t t;} +void f_vuint8mf4x3_t () {vuint8mf4x3_t t;} +void f_vint8mf4x4_t () {vint8mf4x4_t t;} +void f_vuint8mf4x4_t () {vuint8mf4x4_t t;} +void f_vint8mf4x5_t () {vint8mf4x5_t t;} +void f_vuint8mf4x5_t () {vuint8mf4x5_t t;} +void f_vint8mf4x6_t () {vint8mf4x6_t t;} +void f_vuint8mf4x6_t () {vuint8mf4x6_t t;} +void f_vint8mf4x7_t () {vint8mf4x7_t t;} +void f_vuint8mf4x7_t () {vuint8mf4x7_t t;} +void f_vint8mf4x8_t () {vint8mf4x8_t t;} +void f_vuint8mf4x8_t () {vuint8mf4x8_t t;} +void f_vint8mf2x2_t () {vint8mf2x2_t t;} +void f_vuint8mf2x2_t () {vuint8mf2x2_t t;} +void f_vint8mf2x3_t () {vint8mf2x3_t t;} +void f_vuint8mf2x3_t () {vuint8mf2x3_t t;} +void f_vint8mf2x4_t () {vint8mf2x4_t t;} +void f_vuint8mf2x4_t () {vuint8mf2x4_t t;} +void f_vint8mf2x5_t () {vint8mf2x5_t t;} +void f_vuint8mf2x5_t () {vuint8mf2x5_t t;} +void f_vint8mf2x6_t () {vint8mf2x6_t t;} +void f_vuint8mf2x6_t () {vuint8mf2x6_t t;} +void f_vint8mf2x7_t () {vint8mf2x7_t t;} +void f_vuint8mf2x7_t () {vuint8mf2x7_t t;} +void f_vint8mf2x8_t () {vint8mf2x8_t t;} +void f_vuint8mf2x8_t () {vuint8mf2x8_t t;} +void f_vint8m1x2_t () {vint8m1x2_t t;} +void f_vuint8m1x2_t () {vuint8m1x2_t t;} +void f_vint8m1x3_t () {vint8m1x3_t t;} +void f_vuint8m1x3_t () {vuint8m1x3_t t;} +void f_vint8m1x4_t () {vint8m1x4_t t;} +void f_vuint8m1x4_t () {vuint8m1x4_t t;} +void f_vint8m1x5_t () {vint8m1x5_t t;} +void f_vuint8m1x5_t () {vuint8m1x5_t t;} +void f_vint8m1x6_t () {vint8m1x6_t t;} +void f_vuint8m1x6_t () {vuint8m1x6_t t;} +void f_vint8m1x7_t () {vint8m1x7_t t;} +void f_vuint8m1x7_t () {vuint8m1x7_t t;} +void f_vint8m1x8_t () {vint8m1x8_t t;} +void f_vuint8m1x8_t () {vuint8m1x8_t t;} +void f_vint8m2x2_t () {vint8m2x2_t t;} +void f_vuint8m2x2_t () {vuint8m2x2_t t;} +void f_vint8m2x3_t () {vint8m2x3_t t;} +void f_vuint8m2x3_t () {vuint8m2x3_t t;} +void f_vint8m2x4_t () {vint8m2x4_t t;} +void f_vuint8m2x4_t () {vuint8m2x4_t t;} +void f_vint8m4x2_t () {vint8m4x2_t t;} +void f_vuint8m4x2_t () {vuint8m4x2_t t;} +void f_vint16mf4x2_t () {vint16mf4x2_t t;} /* { dg-error {unknown type name 'vint16mf4x2_t'} } */ +void f_vuint16mf4x2_t () {vuint16mf4x2_t t;} /* { dg-error {unknown type name 'vuint16mf4x2_t'} } */ +void f_vint16mf4x3_t () {vint16mf4x3_t t;} /* { dg-error {unknown type name 'vint16mf4x3_t'} } */ +void f_vuint16mf4x3_t () {vuint16mf4x3_t t;} /* { dg-error {unknown type name 'vuint16mf4x3_t'} } */ +void f_vint16mf4x4_t () {vint16mf4x4_t t;} /* { dg-error {unknown type name 'vint16mf4x4_t'} } */ +void f_vuint16mf4x4_t () {vuint16mf4x4_t t;} /* { dg-error {unknown type name 'vuint16mf4x4_t'} } */ +void f_vint16mf4x5_t () {vint16mf4x5_t t;} /* { dg-error {unknown type name 'vint16mf4x5_t'} } */ +void f_vuint16mf4x5_t () {vuint16mf4x5_t t;} /* { dg-error {unknown type name 'vuint16mf4x5_t'} } */ +void f_vint16mf4x6_t () {vint16mf4x6_t t;} /* { dg-error {unknown type name 'vint16mf4x6_t'} } */ +void f_vuint16mf4x6_t () {vuint16mf4x6_t t;} /* { dg-error {unknown type name 'vuint16mf4x6_t'} } */ +void f_vint16mf4x7_t () {vint16mf4x7_t t;} /* { dg-error {unknown type name 'vint16mf4x7_t'} } */ +void f_vuint16mf4x7_t () {vuint16mf4x7_t t;} /* { dg-error {unknown type name 'vuint16mf4x7_t'} } */ +void f_vint16mf4x8_t () {vint16mf4x8_t t;} /* { dg-error {unknown type name 'vint16mf4x8_t'} } */ +void f_vuint16mf4x8_t () {vuint16mf4x8_t t;} /* { dg-error {unknown type name 'vuint16mf4x8_t'} } */ +void f_vint16mf2x2_t () {vint16mf2x2_t t;} +void f_vuint16mf2x2_t () {vuint16mf2x2_t t;} +void f_vint16mf2x3_t () {vint16mf2x3_t t;} +void f_vuint16mf2x3_t () {vuint16mf2x3_t t;} +void f_vint16mf2x4_t () {vint16mf2x4_t t;} +void f_vuint16mf2x4_t () {vuint16mf2x4_t t;} +void f_vint16mf2x5_t () {vint16mf2x5_t t;} +void f_vuint16mf2x5_t () {vuint16mf2x5_t t;} +void f_vint16mf2x6_t () {vint16mf2x6_t t;} +void f_vuint16mf2x6_t () {vuint16mf2x6_t t;} +void f_vint16mf2x7_t () {vint16mf2x7_t t;} +void f_vuint16mf2x7_t () {vuint16mf2x7_t t;} +void f_vint16mf2x8_t () {vint16mf2x8_t t;} +void f_vuint16mf2x8_t () {vuint16mf2x8_t t;} +void f_vint16m1x2_t () {vint16m1x2_t t;} +void f_vuint16m1x2_t () {vuint16m1x2_t t;} +void f_vint16m1x3_t () {vint16m1x3_t t;} +void f_vuint16m1x3_t () {vuint16m1x3_t t;} +void f_vint16m1x4_t () {vint16m1x4_t t;} +void f_vuint16m1x4_t () {vuint16m1x4_t t;} +void f_vint16m1x5_t () {vint16m1x5_t t;} +void f_vuint16m1x5_t () {vuint16m1x5_t t;} +void f_vint16m1x6_t () {vint16m1x6_t t;} +void f_vuint16m1x6_t () {vuint16m1x6_t t;} +void f_vint16m1x7_t () {vint16m1x7_t t;} +void f_vuint16m1x7_t () {vuint16m1x7_t t;} +void f_vint16m1x8_t () {vint16m1x8_t t;} +void f_vuint16m1x8_t () {vuint16m1x8_t t;} +void f_vint16m2x2_t () {vint16m2x2_t t;} +void f_vuint16m2x2_t () {vuint16m2x2_t t;} +void f_vint16m2x3_t () {vint16m2x3_t t;} +void f_vuint16m2x3_t () {vuint16m2x3_t t;} +void f_vint16m2x4_t () {vint16m2x4_t t;} +void f_vuint16m2x4_t () {vuint16m2x4_t t;} +void f_vint16m4x2_t () {vint16m4x2_t t;} +void f_vuint16m4x2_t () {vuint16m4x2_t t;} +void f_vint32mf2x2_t () {vint32mf2x2_t t;} /* { dg-error {unknown type name 'vint32mf2x2_t'} } */ +void f_vuint32mf2x2_t () {vuint32mf2x2_t t;} /* { dg-error {unknown type name 'vuint32mf2x2_t'} } */ +void f_vint32mf2x3_t () {vint32mf2x3_t t;} /* { dg-error {unknown type name 'vint32mf2x3_t'} } */ +void f_vuint32mf2x3_t () {vuint32mf2x3_t t;} /* { dg-error {unknown type name 'vuint32mf2x3_t'} } */ +void f_vint32mf2x4_t () {vint32mf2x4_t t;} /* { dg-error {unknown type name 'vint32mf2x4_t'} } */ +void f_vuint32mf2x4_t () {vuint32mf2x4_t t;} /* { dg-error {unknown type name 'vuint32mf2x4_t'} } */ +void f_vint32mf2x5_t () {vint32mf2x5_t t;} /* { dg-error {unknown type name 'vint32mf2x5_t'} } */ +void f_vuint32mf2x5_t () {vuint32mf2x5_t t;} /* { dg-error {unknown type name 'vuint32mf2x5_t'} } */ +void f_vint32mf2x6_t () {vint32mf2x6_t t;} /* { dg-error {unknown type name 'vint32mf2x6_t'} } */ +void f_vuint32mf2x6_t () {vuint32mf2x6_t t;} /* { dg-error {unknown type name 'vuint32mf2x6_t'} } */ +void f_vint32mf2x7_t () {vint32mf2x7_t t;} /* { dg-error {unknown type name 'vint32mf2x7_t'} } */ +void f_vuint32mf2x7_t () {vuint32mf2x7_t t;} /* { dg-error {unknown type name 'vuint32mf2x7_t'} } */ +void f_vint32mf2x8_t () {vint32mf2x8_t t;} /* { dg-error {unknown type name 'vint32mf2x8_t'} } */ +void f_vuint32mf2x8_t () {vuint32mf2x8_t t;} /* { dg-error {unknown type name 'vuint32mf2x8_t'} } */ +void f_vint32m1x2_t () {vint32m1x2_t t;} +void f_vuint32m1x2_t () {vuint32m1x2_t t;} +void f_vint32m1x3_t () {vint32m1x3_t t;} +void f_vuint32m1x3_t () {vuint32m1x3_t t;} +void f_vint32m1x4_t () {vint32m1x4_t t;} +void f_vuint32m1x4_t () {vuint32m1x4_t t;} +void f_vint32m1x5_t () {vint32m1x5_t t;} +void f_vuint32m1x5_t () {vuint32m1x5_t t;} +void f_vint32m1x6_t () {vint32m1x6_t t;} +void f_vuint32m1x6_t () {vuint32m1x6_t t;} +void f_vint32m1x7_t () {vint32m1x7_t t;} +void f_vuint32m1x7_t () {vuint32m1x7_t t;} +void f_vint32m1x8_t () {vint32m1x8_t t;} +void f_vuint32m1x8_t () {vuint32m1x8_t t;} +void f_vint32m2x2_t () {vint32m2x2_t t;} +void f_vuint32m2x2_t () {vuint32m2x2_t t;} +void f_vint32m2x3_t () {vint32m2x3_t t;} +void f_vuint32m2x3_t () {vuint32m2x3_t t;} +void f_vint32m2x4_t () {vint32m2x4_t t;} +void f_vuint32m2x4_t () {vuint32m2x4_t t;} +void f_vint32m4x2_t () {vint32m4x2_t t;} +void f_vuint32m4x2_t () {vuint32m4x2_t t;} +void f_vint64m1x2_t () {vint64m1x2_t t;} /* { dg-error {unknown type name 'vint64m1x2_t'} } */ +void f_vuint64m1x2_t () {vuint64m1x2_t t;} /* { dg-error {unknown type name 'vuint64m1x2_t'} } */ +void f_vint64m1x3_t () {vint64m1x3_t t;} /* { dg-error {unknown type name 'vint64m1x3_t'} } */ +void f_vuint64m1x3_t () {vuint64m1x3_t t;} /* { dg-error {unknown type name 'vuint64m1x3_t'} } */ +void f_vint64m1x4_t () {vint64m1x4_t t;} /* { dg-error {unknown type name 'vint64m1x4_t'} } */ +void f_vuint64m1x4_t () {vuint64m1x4_t t;} /* { dg-error {unknown type name 'vuint64m1x4_t'} } */ +void f_vint64m1x5_t () {vint64m1x5_t t;} /* { dg-error {unknown type name 'vint64m1x5_t'} } */ +void f_vuint64m1x5_t () {vuint64m1x5_t t;} /* { dg-error {unknown type name 'vuint64m1x5_t'} } */ +void f_vint64m1x6_t () {vint64m1x6_t t;} /* { dg-error {unknown type name 'vint64m1x6_t'} } */ +void f_vuint64m1x6_t () {vuint64m1x6_t t;} /* { dg-error {unknown type name 'vuint64m1x6_t'} } */ +void f_vint64m1x7_t () {vint64m1x7_t t;} /* { dg-error {unknown type name 'vint64m1x7_t'} } */ +void f_vuint64m1x7_t () {vuint64m1x7_t t;} /* { dg-error {unknown type name 'vuint64m1x7_t'} } */ +void f_vint64m1x8_t () {vint64m1x8_t t;} /* { dg-error {unknown type name 'vint64m1x8_t'} } */ +void f_vuint64m1x8_t () {vuint64m1x8_t t;} /* { dg-error {unknown type name 'vuint64m1x8_t'} } */ +void f_vint64m2x2_t () {vint64m2x2_t t;} /* { dg-error {unknown type name 'vint64m2x2_t'} } */ +void f_vuint64m2x2_t () {vuint64m2x2_t t;} /* { dg-error {unknown type name 'vuint64m2x2_t'} } */ +void f_vint64m2x3_t () {vint64m2x3_t t;} /* { dg-error {unknown type name 'vint64m2x3_t'} } */ +void f_vuint64m2x3_t () {vuint64m2x3_t t;} /* { dg-error {unknown type name 'vuint64m2x3_t'} } */ +void f_vint64m2x4_t () {vint64m2x4_t t;} /* { dg-error {unknown type name 'vint64m2x4_t'} } */ +void f_vuint64m2x4_t () {vuint64m2x4_t t;} /* { dg-error {unknown type name 'vuint64m2x4_t'} } */ +void f_vint64m4x2_t () {vint64m4x2_t t;} /* { dg-error {unknown type name 'vint64m4x2_t'} } */ +void f_vuint64m4x2_t () {vuint64m4x2_t t;} /* { dg-error {unknown type name 'vuint64m4x2_t'} } */ +void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} /* { dg-error {unknown type name 'vfloat32mf2x2_t'} } */ +void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} /* { dg-error {unknown type name 'vfloat32mf2x3_t'} } */ +void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} /* { dg-error {unknown type name 'vfloat32mf2x4_t'} } */ +void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;} /* { dg-error {unknown type name 'vfloat32mf2x5_t'} } */ +void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;} /* { dg-error {unknown type name 'vfloat32mf2x6_t'} } */ +void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;} /* { dg-error {unknown type name 'vfloat32mf2x7_t'} } */ +void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;} /* { dg-error {unknown type name 'vfloat32mf2x8_t'} } */ +void f_vfloat32m1x2_t () {vfloat32m1x2_t t;} /* { dg-error {unknown type name 'vfloat32m1x2_t'} } */ +void f_vfloat32m1x3_t () {vfloat32m1x3_t t;} /* { dg-error {unknown type name 'vfloat32m1x3_t'} } */ +void f_vfloat32m1x4_t () {vfloat32m1x4_t t;} /* { dg-error {unknown type name 'vfloat32m1x4_t'} } */ +void f_vfloat32m1x5_t () {vfloat32m1x5_t t;} /* { dg-error {unknown type name 'vfloat32m1x5_t'} } */ +void f_vfloat32m1x6_t () {vfloat32m1x6_t t;} /* { dg-error {unknown type name 'vfloat32m1x6_t'} } */ +void f_vfloat32m1x7_t () {vfloat32m1x7_t t;} /* { dg-error {unknown type name 'vfloat32m1x7_t'} } */ +void f_vfloat32m1x8_t () {vfloat32m1x8_t t;} /* { dg-error {unknown type name 'vfloat32m1x8_t'} } */ +void f_vfloat32m2x2_t () {vfloat32m2x2_t t;} /* { dg-error {unknown type name 'vfloat32m2x2_t'} } */ +void f_vfloat32m2x3_t () {vfloat32m2x3_t t;} /* { dg-error {unknown type name 'vfloat32m2x3_t'} } */ +void f_vfloat32m2x4_t () {vfloat32m2x4_t t;} /* { dg-error {unknown type name 'vfloat32m2x4_t'} } */ +void f_vfloat32m4x2_t () {vfloat32m4x2_t t;} /* { dg-error {unknown type name 'vfloat32m4x2_t'} } */ +void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} /* { dg-error {unknown type name 'vfloat64m1x2_t'} } */ +void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} /* { dg-error {unknown type name 'vfloat64m1x3_t'} } */ +void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} /* { dg-error {unknown type name 'vfloat64m1x4_t'} } */ +void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} /* { dg-error {unknown type name 'vfloat64m1x5_t'} } */ +void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} /* { dg-error {unknown type name 'vfloat64m1x6_t'} } */ +void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} /* { dg-error {unknown type name 'vfloat64m1x7_t'} } */ +void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} /* { dg-error {unknown type name 'vfloat64m1x8_t'} } */ +void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} /* { dg-error {unknown type name 'vfloat64m2x2_t'} } */ +void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} /* { dg-error {unknown type name 'vfloat64m2x3_t'} } */ +void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} /* { dg-error {unknown type name 'vfloat64m2x4_t'} } */ +void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} /* { dg-error {unknown type name 'vfloat64m4x2_t'} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-13.c new file mode 100644 index 00000000000..ed180749cb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-13.c @@ -0,0 +1,206 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc_zve32x_zvl64b -mabi=ilp32d" } */ + +#include "riscv_vector.h" + +void f_vint8mf8x2_t () {vint8mf8x2_t t;} +void f_vuint8mf8x2_t () {vuint8mf8x2_t t;} +void f_vint8mf8x3_t () {vint8mf8x3_t t;} +void f_vuint8mf8x3_t () {vuint8mf8x3_t t;} +void f_vint8mf8x4_t () {vint8mf8x4_t t;} +void f_vuint8mf8x4_t () {vuint8mf8x4_t t;} +void f_vint8mf8x5_t () {vint8mf8x5_t t;} +void f_vuint8mf8x5_t () {vuint8mf8x5_t t;} +void f_vint8mf8x6_t () {vint8mf8x6_t t;} +void f_vuint8mf8x6_t () {vuint8mf8x6_t t;} +void f_vint8mf8x7_t () {vint8mf8x7_t t;} +void f_vuint8mf8x7_t () {vuint8mf8x7_t t;} +void f_vint8mf8x8_t () {vint8mf8x8_t t;} +void f_vuint8mf8x8_t () {vuint8mf8x8_t t;} +void f_vint8mf4x2_t () {vint8mf4x2_t t;} +void f_vuint8mf4x2_t () {vuint8mf4x2_t t;} +void f_vint8mf4x3_t () {vint8mf4x3_t t;} +void f_vuint8mf4x3_t () {vuint8mf4x3_t t;} +void f_vint8mf4x4_t () {vint8mf4x4_t t;} +void f_vuint8mf4x4_t () {vuint8mf4x4_t t;} +void f_vint8mf4x5_t () {vint8mf4x5_t t;} +void f_vuint8mf4x5_t () {vuint8mf4x5_t t;} +void f_vint8mf4x6_t () {vint8mf4x6_t t;} +void f_vuint8mf4x6_t () {vuint8mf4x6_t t;} +void f_vint8mf4x7_t () {vint8mf4x7_t t;} +void f_vuint8mf4x7_t () {vuint8mf4x7_t t;} +void f_vint8mf4x8_t () {vint8mf4x8_t t;} +void f_vuint8mf4x8_t () {vuint8mf4x8_t t;} +void f_vint8mf2x2_t () {vint8mf2x2_t t;} +void f_vuint8mf2x2_t () {vuint8mf2x2_t t;} +void f_vint8mf2x3_t () {vint8mf2x3_t t;} +void f_vuint8mf2x3_t () {vuint8mf2x3_t t;} +void f_vint8mf2x4_t () {vint8mf2x4_t t;} +void f_vuint8mf2x4_t () {vuint8mf2x4_t t;} +void f_vint8mf2x5_t () {vint8mf2x5_t t;} +void f_vuint8mf2x5_t () {vuint8mf2x5_t t;} +void f_vint8mf2x6_t () {vint8mf2x6_t t;} +void f_vuint8mf2x6_t () {vuint8mf2x6_t t;} +void f_vint8mf2x7_t () {vint8mf2x7_t t;} +void f_vuint8mf2x7_t () {vuint8mf2x7_t t;} +void f_vint8mf2x8_t () {vint8mf2x8_t t;} +void f_vuint8mf2x8_t () {vuint8mf2x8_t t;} +void f_vint8m1x2_t () {vint8m1x2_t t;} +void f_vuint8m1x2_t () {vuint8m1x2_t t;} +void f_vint8m1x3_t () {vint8m1x3_t t;} +void f_vuint8m1x3_t () {vuint8m1x3_t t;} +void f_vint8m1x4_t () {vint8m1x4_t t;} +void f_vuint8m1x4_t () {vuint8m1x4_t t;} +void f_vint8m1x5_t () {vint8m1x5_t t;} +void f_vuint8m1x5_t () {vuint8m1x5_t t;} +void f_vint8m1x6_t () {vint8m1x6_t t;} +void f_vuint8m1x6_t () {vuint8m1x6_t t;} +void f_vint8m1x7_t () {vint8m1x7_t t;} +void f_vuint8m1x7_t () {vuint8m1x7_t t;} +void f_vint8m1x8_t () {vint8m1x8_t t;} +void f_vuint8m1x8_t () {vuint8m1x8_t t;} +void f_vint8m2x2_t () {vint8m2x2_t t;} +void f_vuint8m2x2_t () {vuint8m2x2_t t;} +void f_vint8m2x3_t () {vint8m2x3_t t;} +void f_vuint8m2x3_t () {vuint8m2x3_t t;} +void f_vint8m2x4_t () {vint8m2x4_t t;} +void f_vuint8m2x4_t () {vuint8m2x4_t t;} +void f_vint8m4x2_t () {vint8m4x2_t t;} +void f_vuint8m4x2_t () {vuint8m4x2_t t;} +void f_vint16mf4x2_t () {vint16mf4x2_t t;} +void f_vuint16mf4x2_t () {vuint16mf4x2_t t;} +void f_vint16mf4x3_t () {vint16mf4x3_t t;} +void f_vuint16mf4x3_t () {vuint16mf4x3_t t;} +void f_vint16mf4x4_t () {vint16mf4x4_t t;} +void f_vuint16mf4x4_t () {vuint16mf4x4_t t;} +void f_vint16mf4x5_t () {vint16mf4x5_t t;} +void f_vuint16mf4x5_t () {vuint16mf4x5_t t;} +void f_vint16mf4x6_t () {vint16mf4x6_t t;} +void f_vuint16mf4x6_t () {vuint16mf4x6_t t;} +void f_vint16mf4x7_t () {vint16mf4x7_t t;} +void f_vuint16mf4x7_t () {vuint16mf4x7_t t;} +void f_vint16mf4x8_t () {vint16mf4x8_t t;} +void f_vuint16mf4x8_t () {vuint16mf4x8_t t;} +void f_vint16mf2x2_t () {vint16mf2x2_t t;} +void f_vuint16mf2x2_t () {vuint16mf2x2_t t;} +void f_vint16mf2x3_t () {vint16mf2x3_t t;} +void f_vuint16mf2x3_t () {vuint16mf2x3_t t;} +void f_vint16mf2x4_t () {vint16mf2x4_t t;} +void f_vuint16mf2x4_t () {vuint16mf2x4_t t;} +void f_vint16mf2x5_t () {vint16mf2x5_t t;} +void f_vuint16mf2x5_t () {vuint16mf2x5_t t;} +void f_vint16mf2x6_t () {vint16mf2x6_t t;} +void f_vuint16mf2x6_t () {vuint16mf2x6_t t;} +void f_vint16mf2x7_t () {vint16mf2x7_t t;} +void f_vuint16mf2x7_t () {vuint16mf2x7_t t;} +void f_vint16mf2x8_t () {vint16mf2x8_t t;} +void f_vuint16mf2x8_t () {vuint16mf2x8_t t;} +void f_vint16m1x2_t () {vint16m1x2_t t;} +void f_vuint16m1x2_t () {vuint16m1x2_t t;} +void f_vint16m1x3_t () {vint16m1x3_t t;} +void f_vuint16m1x3_t () {vuint16m1x3_t t;} +void f_vint16m1x4_t () {vint16m1x4_t t;} +void f_vuint16m1x4_t () {vuint16m1x4_t t;} +void f_vint16m1x5_t () {vint16m1x5_t t;} +void f_vuint16m1x5_t () {vuint16m1x5_t t;} +void f_vint16m1x6_t () {vint16m1x6_t t;} +void f_vuint16m1x6_t () {vuint16m1x6_t t;} +void f_vint16m1x7_t () {vint16m1x7_t t;} +void f_vuint16m1x7_t () {vuint16m1x7_t t;} +void f_vint16m1x8_t () {vint16m1x8_t t;} +void f_vuint16m1x8_t () {vuint16m1x8_t t;} +void f_vint16m2x2_t () {vint16m2x2_t t;} +void f_vuint16m2x2_t () {vuint16m2x2_t t;} +void f_vint16m2x3_t () {vint16m2x3_t t;} +void f_vuint16m2x3_t () {vuint16m2x3_t t;} +void f_vint16m2x4_t () {vint16m2x4_t t;} +void f_vuint16m2x4_t () {vuint16m2x4_t t;} +void f_vint16m4x2_t () {vint16m4x2_t t;} +void f_vuint16m4x2_t () {vuint16m4x2_t t;} +void f_vint32mf2x2_t () {vint32mf2x2_t t;} +void f_vuint32mf2x2_t () {vuint32mf2x2_t t;} +void f_vint32mf2x3_t () {vint32mf2x3_t t;} +void f_vuint32mf2x3_t () {vuint32mf2x3_t t;} +void f_vint32mf2x4_t () {vint32mf2x4_t t;} +void f_vuint32mf2x4_t () {vuint32mf2x4_t t;} +void f_vint32mf2x5_t () {vint32mf2x5_t t;} +void f_vuint32mf2x5_t () {vuint32mf2x5_t t;} +void f_vint32mf2x6_t () {vint32mf2x6_t t;} +void f_vuint32mf2x6_t () {vuint32mf2x6_t t;} +void f_vint32mf2x7_t () {vint32mf2x7_t t;} +void f_vuint32mf2x7_t () {vuint32mf2x7_t t;} +void f_vint32mf2x8_t () {vint32mf2x8_t t;} +void f_vuint32mf2x8_t () {vuint32mf2x8_t t;} +void f_vint32m1x2_t () {vint32m1x2_t t;} +void f_vuint32m1x2_t () {vuint32m1x2_t t;} +void f_vint32m1x3_t () {vint32m1x3_t t;} +void f_vuint32m1x3_t () {vuint32m1x3_t t;} +void f_vint32m1x4_t () {vint32m1x4_t t;} +void f_vuint32m1x4_t () {vuint32m1x4_t t;} +void f_vint32m1x5_t () {vint32m1x5_t t;} +void f_vuint32m1x5_t () {vuint32m1x5_t t;} +void f_vint32m1x6_t () {vint32m1x6_t t;} +void f_vuint32m1x6_t () {vuint32m1x6_t t;} +void f_vint32m1x7_t () {vint32m1x7_t t;} +void f_vuint32m1x7_t () {vuint32m1x7_t t;} +void f_vint32m1x8_t () {vint32m1x8_t t;} +void f_vuint32m1x8_t () {vuint32m1x8_t t;} +void f_vint32m2x2_t () {vint32m2x2_t t;} +void f_vuint32m2x2_t () {vuint32m2x2_t t;} +void f_vint32m2x3_t () {vint32m2x3_t t;} +void f_vuint32m2x3_t () {vuint32m2x3_t t;} +void f_vint32m2x4_t () {vint32m2x4_t t;} +void f_vuint32m2x4_t () {vuint32m2x4_t t;} +void f_vint32m4x2_t () {vint32m4x2_t t;} +void f_vuint32m4x2_t () {vuint32m4x2_t t;} +void f_vint64m1x2_t () {vint64m1x2_t t;} /* { dg-error {unknown type name 'vint64m1x2_t'} } */ +void f_vuint64m1x2_t () {vuint64m1x2_t t;} /* { dg-error {unknown type name 'vuint64m1x2_t'} } */ +void f_vint64m1x3_t () {vint64m1x3_t t;} /* { dg-error {unknown type name 'vint64m1x3_t'} } */ +void f_vuint64m1x3_t () {vuint64m1x3_t t;} /* { dg-error {unknown type name 'vuint64m1x3_t'} } */ +void f_vint64m1x4_t () {vint64m1x4_t t;} /* { dg-error {unknown type name 'vint64m1x4_t'} } */ +void f_vuint64m1x4_t () {vuint64m1x4_t t;} /* { dg-error {unknown type name 'vuint64m1x4_t'} } */ +void f_vint64m1x5_t () {vint64m1x5_t t;} /* { dg-error {unknown type name 'vint64m1x5_t'} } */ +void f_vuint64m1x5_t () {vuint64m1x5_t t;} /* { dg-error {unknown type name 'vuint64m1x5_t'} } */ +void f_vint64m1x6_t () {vint64m1x6_t t;} /* { dg-error {unknown type name 'vint64m1x6_t'} } */ +void f_vuint64m1x6_t () {vuint64m1x6_t t;} /* { dg-error {unknown type name 'vuint64m1x6_t'} } */ +void f_vint64m1x7_t () {vint64m1x7_t t;} /* { dg-error {unknown type name 'vint64m1x7_t'} } */ +void f_vuint64m1x7_t () {vuint64m1x7_t t;} /* { dg-error {unknown type name 'vuint64m1x7_t'} } */ +void f_vint64m1x8_t () {vint64m1x8_t t;} /* { dg-error {unknown type name 'vint64m1x8_t'} } */ +void f_vuint64m1x8_t () {vuint64m1x8_t t;} /* { dg-error {unknown type name 'vuint64m1x8_t'} } */ +void f_vint64m2x2_t () {vint64m2x2_t t;} /* { dg-error {unknown type name 'vint64m2x2_t'} } */ +void f_vuint64m2x2_t () {vuint64m2x2_t t;} /* { dg-error {unknown type name 'vuint64m2x2_t'} } */ +void f_vint64m2x3_t () {vint64m2x3_t t;} /* { dg-error {unknown type name 'vint64m2x3_t'} } */ +void f_vuint64m2x3_t () {vuint64m2x3_t t;} /* { dg-error {unknown type name 'vuint64m2x3_t'} } */ +void f_vint64m2x4_t () {vint64m2x4_t t;} /* { dg-error {unknown type name 'vint64m2x4_t'} } */ +void f_vuint64m2x4_t () {vuint64m2x4_t t;} /* { dg-error {unknown type name 'vuint64m2x4_t'} } */ +void f_vint64m4x2_t () {vint64m4x2_t t;} /* { dg-error {unknown type name 'vint64m4x2_t'} } */ +void f_vuint64m4x2_t () {vuint64m4x2_t t;} /* { dg-error {unknown type name 'vuint64m4x2_t'} } */ +void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} /* { dg-error {unknown type name 'vfloat32mf2x2_t'} } */ +void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} /* { dg-error {unknown type name 'vfloat32mf2x3_t'} } */ +void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} /* { dg-error {unknown type name 'vfloat32mf2x4_t'} } */ +void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;} /* { dg-error {unknown type name 'vfloat32mf2x5_t'} } */ +void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;} /* { dg-error {unknown type name 'vfloat32mf2x6_t'} } */ +void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;} /* { dg-error {unknown type name 'vfloat32mf2x7_t'} } */ +void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;} /* { dg-error {unknown type name 'vfloat32mf2x8_t'} } */ +void f_vfloat32m1x2_t () {vfloat32m1x2_t t;} /* { dg-error {unknown type name 'vfloat32m1x2_t'} } */ +void f_vfloat32m1x3_t () {vfloat32m1x3_t t;} /* { dg-error {unknown type name 'vfloat32m1x3_t'} } */ +void f_vfloat32m1x4_t () {vfloat32m1x4_t t;} /* { dg-error {unknown type name 'vfloat32m1x4_t'} } */ +void f_vfloat32m1x5_t () {vfloat32m1x5_t t;} /* { dg-error {unknown type name 'vfloat32m1x5_t'} } */ +void f_vfloat32m1x6_t () {vfloat32m1x6_t t;} /* { dg-error {unknown type name 'vfloat32m1x6_t'} } */ +void f_vfloat32m1x7_t () {vfloat32m1x7_t t;} /* { dg-error {unknown type name 'vfloat32m1x7_t'} } */ +void f_vfloat32m1x8_t () {vfloat32m1x8_t t;} /* { dg-error {unknown type name 'vfloat32m1x8_t'} } */ +void f_vfloat32m2x2_t () {vfloat32m2x2_t t;} /* { dg-error {unknown type name 'vfloat32m2x2_t'} } */ +void f_vfloat32m2x3_t () {vfloat32m2x3_t t;} /* { dg-error {unknown type name 'vfloat32m2x3_t'} } */ +void f_vfloat32m2x4_t () {vfloat32m2x4_t t;} /* { dg-error {unknown type name 'vfloat32m2x4_t'} } */ +void f_vfloat32m4x2_t () {vfloat32m4x2_t t;} /* { dg-error {unknown type name 'vfloat32m4x2_t'} } */ +void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} /* { dg-error {unknown type name 'vfloat64m1x2_t'} } */ +void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} /* { dg-error {unknown type name 'vfloat64m1x3_t'} } */ +void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} /* { dg-error {unknown type name 'vfloat64m1x4_t'} } */ +void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} /* { dg-error {unknown type name 'vfloat64m1x5_t'} } */ +void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} /* { dg-error {unknown type name 'vfloat64m1x6_t'} } */ +void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} /* { dg-error {unknown type name 'vfloat64m1x7_t'} } */ +void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} /* { dg-error {unknown type name 'vfloat64m1x8_t'} } */ +void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} /* { dg-error {unknown type name 'vfloat64m2x2_t'} } */ +void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} /* { dg-error {unknown type name 'vfloat64m2x3_t'} } */ +void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} /* { dg-error {unknown type name 'vfloat64m2x4_t'} } */ +void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} /* { dg-error {unknown type name 'vfloat64m4x2_t'} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-14.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-14.c new file mode 100644 index 00000000000..70e0989b6e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-14.c @@ -0,0 +1,206 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc_zve32f -mabi=ilp32d" } */ + +#include "riscv_vector.h" + +void f_vint8mf8x2_t () {vint8mf8x2_t t;} /* { dg-error {unknown type name 'vint8mf8x2_t'} } */ +void f_vuint8mf8x2_t () {vuint8mf8x2_t t;} /* { dg-error {unknown type name 'vuint8mf8x2_t'} } */ +void f_vint8mf8x3_t () {vint8mf8x3_t t;} /* { dg-error {unknown type name 'vint8mf8x3_t'} } */ +void f_vuint8mf8x3_t () {vuint8mf8x3_t t;} /* { dg-error {unknown type name 'vuint8mf8x3_t'} } */ +void f_vint8mf8x4_t () {vint8mf8x4_t t;} /* { dg-error {unknown type name 'vint8mf8x4_t'} } */ +void f_vuint8mf8x4_t () {vuint8mf8x4_t t;} /* { dg-error {unknown type name 'vuint8mf8x4_t'} } */ +void f_vint8mf8x5_t () {vint8mf8x5_t t;} /* { dg-error {unknown type name 'vint8mf8x5_t'} } */ +void f_vuint8mf8x5_t () {vuint8mf8x5_t t;} /* { dg-error {unknown type name 'vuint8mf8x5_t'} } */ +void f_vint8mf8x6_t () {vint8mf8x6_t t;} /* { dg-error {unknown type name 'vint8mf8x6_t'} } */ +void f_vuint8mf8x6_t () {vuint8mf8x6_t t;} /* { dg-error {unknown type name 'vuint8mf8x6_t'} } */ +void f_vint8mf8x7_t () {vint8mf8x7_t t;} /* { dg-error {unknown type name 'vint8mf8x7_t'} } */ +void f_vuint8mf8x7_t () {vuint8mf8x7_t t;} /* { dg-error {unknown type name 'vuint8mf8x7_t'} } */ +void f_vint8mf8x8_t () {vint8mf8x8_t t;} /* { dg-error {unknown type name 'vint8mf8x8_t'} } */ +void f_vuint8mf8x8_t () {vuint8mf8x8_t t;} /* { dg-error {unknown type name 'vuint8mf8x8_t'} } */ +void f_vint8mf4x2_t () {vint8mf4x2_t t;} +void f_vuint8mf4x2_t () {vuint8mf4x2_t t;} +void f_vint8mf4x3_t () {vint8mf4x3_t t;} +void f_vuint8mf4x3_t () {vuint8mf4x3_t t;} +void f_vint8mf4x4_t () {vint8mf4x4_t t;} +void f_vuint8mf4x4_t () {vuint8mf4x4_t t;} +void f_vint8mf4x5_t () {vint8mf4x5_t t;} +void f_vuint8mf4x5_t () {vuint8mf4x5_t t;} +void f_vint8mf4x6_t () {vint8mf4x6_t t;} +void f_vuint8mf4x6_t () {vuint8mf4x6_t t;} +void f_vint8mf4x7_t () {vint8mf4x7_t t;} +void f_vuint8mf4x7_t () {vuint8mf4x7_t t;} +void f_vint8mf4x8_t () {vint8mf4x8_t t;} +void f_vuint8mf4x8_t () {vuint8mf4x8_t t;} +void f_vint8mf2x2_t () {vint8mf2x2_t t;} +void f_vuint8mf2x2_t () {vuint8mf2x2_t t;} +void f_vint8mf2x3_t () {vint8mf2x3_t t;} +void f_vuint8mf2x3_t () {vuint8mf2x3_t t;} +void f_vint8mf2x4_t () {vint8mf2x4_t t;} +void f_vuint8mf2x4_t () {vuint8mf2x4_t t;} +void f_vint8mf2x5_t () {vint8mf2x5_t t;} +void f_vuint8mf2x5_t () {vuint8mf2x5_t t;} +void f_vint8mf2x6_t () {vint8mf2x6_t t;} +void f_vuint8mf2x6_t () {vuint8mf2x6_t t;} +void f_vint8mf2x7_t () {vint8mf2x7_t t;} +void f_vuint8mf2x7_t () {vuint8mf2x7_t t;} +void f_vint8mf2x8_t () {vint8mf2x8_t t;} +void f_vuint8mf2x8_t () {vuint8mf2x8_t t;} +void f_vint8m1x2_t () {vint8m1x2_t t;} +void f_vuint8m1x2_t () {vuint8m1x2_t t;} +void f_vint8m1x3_t () {vint8m1x3_t t;} +void f_vuint8m1x3_t () {vuint8m1x3_t t;} +void f_vint8m1x4_t () {vint8m1x4_t t;} +void f_vuint8m1x4_t () {vuint8m1x4_t t;} +void f_vint8m1x5_t () {vint8m1x5_t t;} +void f_vuint8m1x5_t () {vuint8m1x5_t t;} +void f_vint8m1x6_t () {vint8m1x6_t t;} +void f_vuint8m1x6_t () {vuint8m1x6_t t;} +void f_vint8m1x7_t () {vint8m1x7_t t;} +void f_vuint8m1x7_t () {vuint8m1x7_t t;} +void f_vint8m1x8_t () {vint8m1x8_t t;} +void f_vuint8m1x8_t () {vuint8m1x8_t t;} +void f_vint8m2x2_t () {vint8m2x2_t t;} +void f_vuint8m2x2_t () {vuint8m2x2_t t;} +void f_vint8m2x3_t () {vint8m2x3_t t;} +void f_vuint8m2x3_t () {vuint8m2x3_t t;} +void f_vint8m2x4_t () {vint8m2x4_t t;} +void f_vuint8m2x4_t () {vuint8m2x4_t t;} +void f_vint8m4x2_t () {vint8m4x2_t t;} +void f_vuint8m4x2_t () {vuint8m4x2_t t;} +void f_vint16mf4x2_t () {vint16mf4x2_t t;} /* { dg-error {unknown type name 'vint16mf4x2_t'} } */ +void f_vuint16mf4x2_t () {vuint16mf4x2_t t;} /* { dg-error {unknown type name 'vuint16mf4x2_t'} } */ +void f_vint16mf4x3_t () {vint16mf4x3_t t;} /* { dg-error {unknown type name 'vint16mf4x3_t'} } */ +void f_vuint16mf4x3_t () {vuint16mf4x3_t t;} /* { dg-error {unknown type name 'vuint16mf4x3_t'} } */ +void f_vint16mf4x4_t () {vint16mf4x4_t t;} /* { dg-error {unknown type name 'vint16mf4x4_t'} } */ +void f_vuint16mf4x4_t () {vuint16mf4x4_t t;} /* { dg-error {unknown type name 'vuint16mf4x4_t'} } */ +void f_vint16mf4x5_t () {vint16mf4x5_t t;} /* { dg-error {unknown type name 'vint16mf4x5_t'} } */ +void f_vuint16mf4x5_t () {vuint16mf4x5_t t;} /* { dg-error {unknown type name 'vuint16mf4x5_t'} } */ +void f_vint16mf4x6_t () {vint16mf4x6_t t;} /* { dg-error {unknown type name 'vint16mf4x6_t'} } */ +void f_vuint16mf4x6_t () {vuint16mf4x6_t t;} /* { dg-error {unknown type name 'vuint16mf4x6_t'} } */ +void f_vint16mf4x7_t () {vint16mf4x7_t t;} /* { dg-error {unknown type name 'vint16mf4x7_t'} } */ +void f_vuint16mf4x7_t () {vuint16mf4x7_t t;} /* { dg-error {unknown type name 'vuint16mf4x7_t'} } */ +void f_vint16mf4x8_t () {vint16mf4x8_t t;} /* { dg-error {unknown type name 'vint16mf4x8_t'} } */ +void f_vuint16mf4x8_t () {vuint16mf4x8_t t;} /* { dg-error {unknown type name 'vuint16mf4x8_t'} } */ +void f_vint16mf2x2_t () {vint16mf2x2_t t;} +void f_vuint16mf2x2_t () {vuint16mf2x2_t t;} +void f_vint16mf2x3_t () {vint16mf2x3_t t;} +void f_vuint16mf2x3_t () {vuint16mf2x3_t t;} +void f_vint16mf2x4_t () {vint16mf2x4_t t;} +void f_vuint16mf2x4_t () {vuint16mf2x4_t t;} +void f_vint16mf2x5_t () {vint16mf2x5_t t;} +void f_vuint16mf2x5_t () {vuint16mf2x5_t t;} +void f_vint16mf2x6_t () {vint16mf2x6_t t;} +void f_vuint16mf2x6_t () {vuint16mf2x6_t t;} +void f_vint16mf2x7_t () {vint16mf2x7_t t;} +void f_vuint16mf2x7_t () {vuint16mf2x7_t t;} +void f_vint16mf2x8_t () {vint16mf2x8_t t;} +void f_vuint16mf2x8_t () {vuint16mf2x8_t t;} +void f_vint16m1x2_t () {vint16m1x2_t t;} +void f_vuint16m1x2_t () {vuint16m1x2_t t;} +void f_vint16m1x3_t () {vint16m1x3_t t;} +void f_vuint16m1x3_t () {vuint16m1x3_t t;} +void f_vint16m1x4_t () {vint16m1x4_t t;} +void f_vuint16m1x4_t () {vuint16m1x4_t t;} +void f_vint16m1x5_t () {vint16m1x5_t t;} +void f_vuint16m1x5_t () {vuint16m1x5_t t;} +void f_vint16m1x6_t () {vint16m1x6_t t;} +void f_vuint16m1x6_t () {vuint16m1x6_t t;} +void f_vint16m1x7_t () {vint16m1x7_t t;} +void f_vuint16m1x7_t () {vuint16m1x7_t t;} +void f_vint16m1x8_t () {vint16m1x8_t t;} +void f_vuint16m1x8_t () {vuint16m1x8_t t;} +void f_vint16m2x2_t () {vint16m2x2_t t;} +void f_vuint16m2x2_t () {vuint16m2x2_t t;} +void f_vint16m2x3_t () {vint16m2x3_t t;} +void f_vuint16m2x3_t () {vuint16m2x3_t t;} +void f_vint16m2x4_t () {vint16m2x4_t t;} +void f_vuint16m2x4_t () {vuint16m2x4_t t;} +void f_vint16m4x2_t () {vint16m4x2_t t;} +void f_vuint16m4x2_t () {vuint16m4x2_t t;} +void f_vint32mf2x2_t () {vint32mf2x2_t t;} /* { dg-error {unknown type name 'vint32mf2x2_t'} } */ +void f_vuint32mf2x2_t () {vuint32mf2x2_t t;} /* { dg-error {unknown type name 'vuint32mf2x2_t'} } */ +void f_vint32mf2x3_t () {vint32mf2x3_t t;} /* { dg-error {unknown type name 'vint32mf2x3_t'} } */ +void f_vuint32mf2x3_t () {vuint32mf2x3_t t;} /* { dg-error {unknown type name 'vuint32mf2x3_t'} } */ +void f_vint32mf2x4_t () {vint32mf2x4_t t;} /* { dg-error {unknown type name 'vint32mf2x4_t'} } */ +void f_vuint32mf2x4_t () {vuint32mf2x4_t t;} /* { dg-error {unknown type name 'vuint32mf2x4_t'} } */ +void f_vint32mf2x5_t () {vint32mf2x5_t t;} /* { dg-error {unknown type name 'vint32mf2x5_t'} } */ +void f_vuint32mf2x5_t () {vuint32mf2x5_t t;} /* { dg-error {unknown type name 'vuint32mf2x5_t'} } */ +void f_vint32mf2x6_t () {vint32mf2x6_t t;} /* { dg-error {unknown type name 'vint32mf2x6_t'} } */ +void f_vuint32mf2x6_t () {vuint32mf2x6_t t;} /* { dg-error {unknown type name 'vuint32mf2x6_t'} } */ +void f_vint32mf2x7_t () {vint32mf2x7_t t;} /* { dg-error {unknown type name 'vint32mf2x7_t'} } */ +void f_vuint32mf2x7_t () {vuint32mf2x7_t t;} /* { dg-error {unknown type name 'vuint32mf2x7_t'} } */ +void f_vint32mf2x8_t () {vint32mf2x8_t t;} /* { dg-error {unknown type name 'vint32mf2x8_t'} } */ +void f_vuint32mf2x8_t () {vuint32mf2x8_t t;} /* { dg-error {unknown type name 'vuint32mf2x8_t'} } */ +void f_vint32m1x2_t () {vint32m1x2_t t;} +void f_vuint32m1x2_t () {vuint32m1x2_t t;} +void f_vint32m1x3_t () {vint32m1x3_t t;} +void f_vuint32m1x3_t () {vuint32m1x3_t t;} +void f_vint32m1x4_t () {vint32m1x4_t t;} +void f_vuint32m1x4_t () {vuint32m1x4_t t;} +void f_vint32m1x5_t () {vint32m1x5_t t;} +void f_vuint32m1x5_t () {vuint32m1x5_t t;} +void f_vint32m1x6_t () {vint32m1x6_t t;} +void f_vuint32m1x6_t () {vuint32m1x6_t t;} +void f_vint32m1x7_t () {vint32m1x7_t t;} +void f_vuint32m1x7_t () {vuint32m1x7_t t;} +void f_vint32m1x8_t () {vint32m1x8_t t;} +void f_vuint32m1x8_t () {vuint32m1x8_t t;} +void f_vint32m2x2_t () {vint32m2x2_t t;} +void f_vuint32m2x2_t () {vuint32m2x2_t t;} +void f_vint32m2x3_t () {vint32m2x3_t t;} +void f_vuint32m2x3_t () {vuint32m2x3_t t;} +void f_vint32m2x4_t () {vint32m2x4_t t;} +void f_vuint32m2x4_t () {vuint32m2x4_t t;} +void f_vint32m4x2_t () {vint32m4x2_t t;} +void f_vuint32m4x2_t () {vuint32m4x2_t t;} +void f_vint64m1x2_t () {vint64m1x2_t t;} /* { dg-error {unknown type name 'vint64m1x2_t'} } */ +void f_vuint64m1x2_t () {vuint64m1x2_t t;} /* { dg-error {unknown type name 'vuint64m1x2_t'} } */ +void f_vint64m1x3_t () {vint64m1x3_t t;} /* { dg-error {unknown type name 'vint64m1x3_t'} } */ +void f_vuint64m1x3_t () {vuint64m1x3_t t;} /* { dg-error {unknown type name 'vuint64m1x3_t'} } */ +void f_vint64m1x4_t () {vint64m1x4_t t;} /* { dg-error {unknown type name 'vint64m1x4_t'} } */ +void f_vuint64m1x4_t () {vuint64m1x4_t t;} /* { dg-error {unknown type name 'vuint64m1x4_t'} } */ +void f_vint64m1x5_t () {vint64m1x5_t t;} /* { dg-error {unknown type name 'vint64m1x5_t'} } */ +void f_vuint64m1x5_t () {vuint64m1x5_t t;} /* { dg-error {unknown type name 'vuint64m1x5_t'} } */ +void f_vint64m1x6_t () {vint64m1x6_t t;} /* { dg-error {unknown type name 'vint64m1x6_t'} } */ +void f_vuint64m1x6_t () {vuint64m1x6_t t;} /* { dg-error {unknown type name 'vuint64m1x6_t'} } */ +void f_vint64m1x7_t () {vint64m1x7_t t;} /* { dg-error {unknown type name 'vint64m1x7_t'} } */ +void f_vuint64m1x7_t () {vuint64m1x7_t t;} /* { dg-error {unknown type name 'vuint64m1x7_t'} } */ +void f_vint64m1x8_t () {vint64m1x8_t t;} /* { dg-error {unknown type name 'vint64m1x8_t'} } */ +void f_vuint64m1x8_t () {vuint64m1x8_t t;} /* { dg-error {unknown type name 'vuint64m1x8_t'} } */ +void f_vint64m2x2_t () {vint64m2x2_t t;} /* { dg-error {unknown type name 'vint64m2x2_t'} } */ +void f_vuint64m2x2_t () {vuint64m2x2_t t;} /* { dg-error {unknown type name 'vuint64m2x2_t'} } */ +void f_vint64m2x3_t () {vint64m2x3_t t;} /* { dg-error {unknown type name 'vint64m2x3_t'} } */ +void f_vuint64m2x3_t () {vuint64m2x3_t t;} /* { dg-error {unknown type name 'vuint64m2x3_t'} } */ +void f_vint64m2x4_t () {vint64m2x4_t t;} /* { dg-error {unknown type name 'vint64m2x4_t'} } */ +void f_vuint64m2x4_t () {vuint64m2x4_t t;} /* { dg-error {unknown type name 'vuint64m2x4_t'} } */ +void f_vint64m4x2_t () {vint64m4x2_t t;} /* { dg-error {unknown type name 'vint64m4x2_t'} } */ +void f_vuint64m4x2_t () {vuint64m4x2_t t;} /* { dg-error {unknown type name 'vuint64m4x2_t'} } */ +void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} /* { dg-error {unknown type name 'vfloat32mf2x2_t'} } */ +void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} /* { dg-error {unknown type name 'vfloat32mf2x3_t'} } */ +void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} /* { dg-error {unknown type name 'vfloat32mf2x4_t'} } */ +void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;} /* { dg-error {unknown type name 'vfloat32mf2x5_t'} } */ +void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;} /* { dg-error {unknown type name 'vfloat32mf2x6_t'} } */ +void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;} /* { dg-error {unknown type name 'vfloat32mf2x7_t'} } */ +void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;} /* { dg-error {unknown type name 'vfloat32mf2x8_t'} } */ +void f_vfloat32m1x2_t () {vfloat32m1x2_t t;} +void f_vfloat32m1x3_t () {vfloat32m1x3_t t;} +void f_vfloat32m1x4_t () {vfloat32m1x4_t t;} +void f_vfloat32m1x5_t () {vfloat32m1x5_t t;} +void f_vfloat32m1x6_t () {vfloat32m1x6_t t;} +void f_vfloat32m1x7_t () {vfloat32m1x7_t t;} +void f_vfloat32m1x8_t () {vfloat32m1x8_t t;} +void f_vfloat32m2x2_t () {vfloat32m2x2_t t;} +void f_vfloat32m2x3_t () {vfloat32m2x3_t t;} +void f_vfloat32m2x4_t () {vfloat32m2x4_t t;} +void f_vfloat32m4x2_t () {vfloat32m4x2_t t;} +void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} /* { dg-error {unknown type name 'vfloat64m1x2_t'} } */ +void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} /* { dg-error {unknown type name 'vfloat64m1x3_t'} } */ +void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} /* { dg-error {unknown type name 'vfloat64m1x4_t'} } */ +void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} /* { dg-error {unknown type name 'vfloat64m1x5_t'} } */ +void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} /* { dg-error {unknown type name 'vfloat64m1x6_t'} } */ +void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} /* { dg-error {unknown type name 'vfloat64m1x7_t'} } */ +void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} /* { dg-error {unknown type name 'vfloat64m1x8_t'} } */ +void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} /* { dg-error {unknown type name 'vfloat64m2x2_t'} } */ +void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} /* { dg-error {unknown type name 'vfloat64m2x3_t'} } */ +void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} /* { dg-error {unknown type name 'vfloat64m2x4_t'} } */ +void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} /* { dg-error {unknown type name 'vfloat64m4x2_t'} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-15.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-15.c new file mode 100644 index 00000000000..2a615f80816 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-15.c @@ -0,0 +1,206 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc_zve32f_zvl64b -mabi=ilp32d" } */ + +#include "riscv_vector.h" + +void f_vint8mf8x2_t () {vint8mf8x2_t t;} +void f_vuint8mf8x2_t () {vuint8mf8x2_t t;} +void f_vint8mf8x3_t () {vint8mf8x3_t t;} +void f_vuint8mf8x3_t () {vuint8mf8x3_t t;} +void f_vint8mf8x4_t () {vint8mf8x4_t t;} +void f_vuint8mf8x4_t () {vuint8mf8x4_t t;} +void f_vint8mf8x5_t () {vint8mf8x5_t t;} +void f_vuint8mf8x5_t () {vuint8mf8x5_t t;} +void f_vint8mf8x6_t () {vint8mf8x6_t t;} +void f_vuint8mf8x6_t () {vuint8mf8x6_t t;} +void f_vint8mf8x7_t () {vint8mf8x7_t t;} +void f_vuint8mf8x7_t () {vuint8mf8x7_t t;} +void f_vint8mf8x8_t () {vint8mf8x8_t t;} +void f_vuint8mf8x8_t () {vuint8mf8x8_t t;} +void f_vint8mf4x2_t () {vint8mf4x2_t t;} +void f_vuint8mf4x2_t () {vuint8mf4x2_t t;} +void f_vint8mf4x3_t () {vint8mf4x3_t t;} +void f_vuint8mf4x3_t () {vuint8mf4x3_t t;} +void f_vint8mf4x4_t () {vint8mf4x4_t t;} +void f_vuint8mf4x4_t () {vuint8mf4x4_t t;} +void f_vint8mf4x5_t () {vint8mf4x5_t t;} +void f_vuint8mf4x5_t () {vuint8mf4x5_t t;} +void f_vint8mf4x6_t () {vint8mf4x6_t t;} +void f_vuint8mf4x6_t () {vuint8mf4x6_t t;} +void f_vint8mf4x7_t () {vint8mf4x7_t t;} +void f_vuint8mf4x7_t () {vuint8mf4x7_t t;} +void f_vint8mf4x8_t () {vint8mf4x8_t t;} +void f_vuint8mf4x8_t () {vuint8mf4x8_t t;} +void f_vint8mf2x2_t () {vint8mf2x2_t t;} +void f_vuint8mf2x2_t () {vuint8mf2x2_t t;} +void f_vint8mf2x3_t () {vint8mf2x3_t t;} +void f_vuint8mf2x3_t () {vuint8mf2x3_t t;} +void f_vint8mf2x4_t () {vint8mf2x4_t t;} +void f_vuint8mf2x4_t () {vuint8mf2x4_t t;} +void f_vint8mf2x5_t () {vint8mf2x5_t t;} +void f_vuint8mf2x5_t () {vuint8mf2x5_t t;} +void f_vint8mf2x6_t () {vint8mf2x6_t t;} +void f_vuint8mf2x6_t () {vuint8mf2x6_t t;} +void f_vint8mf2x7_t () {vint8mf2x7_t t;} +void f_vuint8mf2x7_t () {vuint8mf2x7_t t;} +void f_vint8mf2x8_t () {vint8mf2x8_t t;} +void f_vuint8mf2x8_t () {vuint8mf2x8_t t;} +void f_vint8m1x2_t () {vint8m1x2_t t;} +void f_vuint8m1x2_t () {vuint8m1x2_t t;} +void f_vint8m1x3_t () {vint8m1x3_t t;} +void f_vuint8m1x3_t () {vuint8m1x3_t t;} +void f_vint8m1x4_t () {vint8m1x4_t t;} +void f_vuint8m1x4_t () {vuint8m1x4_t t;} +void f_vint8m1x5_t () {vint8m1x5_t t;} +void f_vuint8m1x5_t () {vuint8m1x5_t t;} +void f_vint8m1x6_t () {vint8m1x6_t t;} +void f_vuint8m1x6_t () {vuint8m1x6_t t;} +void f_vint8m1x7_t () {vint8m1x7_t t;} +void f_vuint8m1x7_t () {vuint8m1x7_t t;} +void f_vint8m1x8_t () {vint8m1x8_t t;} +void f_vuint8m1x8_t () {vuint8m1x8_t t;} +void f_vint8m2x2_t () {vint8m2x2_t t;} +void f_vuint8m2x2_t () {vuint8m2x2_t t;} +void f_vint8m2x3_t () {vint8m2x3_t t;} +void f_vuint8m2x3_t () {vuint8m2x3_t t;} +void f_vint8m2x4_t () {vint8m2x4_t t;} +void f_vuint8m2x4_t () {vuint8m2x4_t t;} +void f_vint8m4x2_t () {vint8m4x2_t t;} +void f_vuint8m4x2_t () {vuint8m4x2_t t;} +void f_vint16mf4x2_t () {vint16mf4x2_t t;} +void f_vuint16mf4x2_t () {vuint16mf4x2_t t;} +void f_vint16mf4x3_t () {vint16mf4x3_t t;} +void f_vuint16mf4x3_t () {vuint16mf4x3_t t;} +void f_vint16mf4x4_t () {vint16mf4x4_t t;} +void f_vuint16mf4x4_t () {vuint16mf4x4_t t;} +void f_vint16mf4x5_t () {vint16mf4x5_t t;} +void f_vuint16mf4x5_t () {vuint16mf4x5_t t;} +void f_vint16mf4x6_t () {vint16mf4x6_t t;} +void f_vuint16mf4x6_t () {vuint16mf4x6_t t;} +void f_vint16mf4x7_t () {vint16mf4x7_t t;} +void f_vuint16mf4x7_t () {vuint16mf4x7_t t;} +void f_vint16mf4x8_t () {vint16mf4x8_t t;} +void f_vuint16mf4x8_t () {vuint16mf4x8_t t;} +void f_vint16mf2x2_t () {vint16mf2x2_t t;} +void f_vuint16mf2x2_t () {vuint16mf2x2_t t;} +void f_vint16mf2x3_t () {vint16mf2x3_t t;} +void f_vuint16mf2x3_t () {vuint16mf2x3_t t;} +void f_vint16mf2x4_t () {vint16mf2x4_t t;} +void f_vuint16mf2x4_t () {vuint16mf2x4_t t;} +void f_vint16mf2x5_t () {vint16mf2x5_t t;} +void f_vuint16mf2x5_t () {vuint16mf2x5_t t;} +void f_vint16mf2x6_t () {vint16mf2x6_t t;} +void f_vuint16mf2x6_t () {vuint16mf2x6_t t;} +void f_vint16mf2x7_t () {vint16mf2x7_t t;} +void f_vuint16mf2x7_t () {vuint16mf2x7_t t;} +void f_vint16mf2x8_t () {vint16mf2x8_t t;} +void f_vuint16mf2x8_t () {vuint16mf2x8_t t;} +void f_vint16m1x2_t () {vint16m1x2_t t;} +void f_vuint16m1x2_t () {vuint16m1x2_t t;} +void f_vint16m1x3_t () {vint16m1x3_t t;} +void f_vuint16m1x3_t () {vuint16m1x3_t t;} +void f_vint16m1x4_t () {vint16m1x4_t t;} +void f_vuint16m1x4_t () {vuint16m1x4_t t;} +void f_vint16m1x5_t () {vint16m1x5_t t;} +void f_vuint16m1x5_t () {vuint16m1x5_t t;} +void f_vint16m1x6_t () {vint16m1x6_t t;} +void f_vuint16m1x6_t () {vuint16m1x6_t t;} +void f_vint16m1x7_t () {vint16m1x7_t t;} +void f_vuint16m1x7_t () {vuint16m1x7_t t;} +void f_vint16m1x8_t () {vint16m1x8_t t;} +void f_vuint16m1x8_t () {vuint16m1x8_t t;} +void f_vint16m2x2_t () {vint16m2x2_t t;} +void f_vuint16m2x2_t () {vuint16m2x2_t t;} +void f_vint16m2x3_t () {vint16m2x3_t t;} +void f_vuint16m2x3_t () {vuint16m2x3_t t;} +void f_vint16m2x4_t () {vint16m2x4_t t;} +void f_vuint16m2x4_t () {vuint16m2x4_t t;} +void f_vint16m4x2_t () {vint16m4x2_t t;} +void f_vuint16m4x2_t () {vuint16m4x2_t t;} +void f_vint32mf2x2_t () {vint32mf2x2_t t;} +void f_vuint32mf2x2_t () {vuint32mf2x2_t t;} +void f_vint32mf2x3_t () {vint32mf2x3_t t;} +void f_vuint32mf2x3_t () {vuint32mf2x3_t t;} +void f_vint32mf2x4_t () {vint32mf2x4_t t;} +void f_vuint32mf2x4_t () {vuint32mf2x4_t t;} +void f_vint32mf2x5_t () {vint32mf2x5_t t;} +void f_vuint32mf2x5_t () {vuint32mf2x5_t t;} +void f_vint32mf2x6_t () {vint32mf2x6_t t;} +void f_vuint32mf2x6_t () {vuint32mf2x6_t t;} +void f_vint32mf2x7_t () {vint32mf2x7_t t;} +void f_vuint32mf2x7_t () {vuint32mf2x7_t t;} +void f_vint32mf2x8_t () {vint32mf2x8_t t;} +void f_vuint32mf2x8_t () {vuint32mf2x8_t t;} +void f_vint32m1x2_t () {vint32m1x2_t t;} +void f_vuint32m1x2_t () {vuint32m1x2_t t;} +void f_vint32m1x3_t () {vint32m1x3_t t;} +void f_vuint32m1x3_t () {vuint32m1x3_t t;} +void f_vint32m1x4_t () {vint32m1x4_t t;} +void f_vuint32m1x4_t () {vuint32m1x4_t t;} +void f_vint32m1x5_t () {vint32m1x5_t t;} +void f_vuint32m1x5_t () {vuint32m1x5_t t;} +void f_vint32m1x6_t () {vint32m1x6_t t;} +void f_vuint32m1x6_t () {vuint32m1x6_t t;} +void f_vint32m1x7_t () {vint32m1x7_t t;} +void f_vuint32m1x7_t () {vuint32m1x7_t t;} +void f_vint32m1x8_t () {vint32m1x8_t t;} +void f_vuint32m1x8_t () {vuint32m1x8_t t;} +void f_vint32m2x2_t () {vint32m2x2_t t;} +void f_vuint32m2x2_t () {vuint32m2x2_t t;} +void f_vint32m2x3_t () {vint32m2x3_t t;} +void f_vuint32m2x3_t () {vuint32m2x3_t t;} +void f_vint32m2x4_t () {vint32m2x4_t t;} +void f_vuint32m2x4_t () {vuint32m2x4_t t;} +void f_vint32m4x2_t () {vint32m4x2_t t;} +void f_vuint32m4x2_t () {vuint32m4x2_t t;} +void f_vint64m1x2_t () {vint64m1x2_t t;} /* { dg-error {unknown type name 'vint64m1x2_t'} } */ +void f_vuint64m1x2_t () {vuint64m1x2_t t;} /* { dg-error {unknown type name 'vuint64m1x2_t'} } */ +void f_vint64m1x3_t () {vint64m1x3_t t;} /* { dg-error {unknown type name 'vint64m1x3_t'} } */ +void f_vuint64m1x3_t () {vuint64m1x3_t t;} /* { dg-error {unknown type name 'vuint64m1x3_t'} } */ +void f_vint64m1x4_t () {vint64m1x4_t t;} /* { dg-error {unknown type name 'vint64m1x4_t'} } */ +void f_vuint64m1x4_t () {vuint64m1x4_t t;} /* { dg-error {unknown type name 'vuint64m1x4_t'} } */ +void f_vint64m1x5_t () {vint64m1x5_t t;} /* { dg-error {unknown type name 'vint64m1x5_t'} } */ +void f_vuint64m1x5_t () {vuint64m1x5_t t;} /* { dg-error {unknown type name 'vuint64m1x5_t'} } */ +void f_vint64m1x6_t () {vint64m1x6_t t;} /* { dg-error {unknown type name 'vint64m1x6_t'} } */ +void f_vuint64m1x6_t () {vuint64m1x6_t t;} /* { dg-error {unknown type name 'vuint64m1x6_t'} } */ +void f_vint64m1x7_t () {vint64m1x7_t t;} /* { dg-error {unknown type name 'vint64m1x7_t'} } */ +void f_vuint64m1x7_t () {vuint64m1x7_t t;} /* { dg-error {unknown type name 'vuint64m1x7_t'} } */ +void f_vint64m1x8_t () {vint64m1x8_t t;} /* { dg-error {unknown type name 'vint64m1x8_t'} } */ +void f_vuint64m1x8_t () {vuint64m1x8_t t;} /* { dg-error {unknown type name 'vuint64m1x8_t'} } */ +void f_vint64m2x2_t () {vint64m2x2_t t;} /* { dg-error {unknown type name 'vint64m2x2_t'} } */ +void f_vuint64m2x2_t () {vuint64m2x2_t t;} /* { dg-error {unknown type name 'vuint64m2x2_t'} } */ +void f_vint64m2x3_t () {vint64m2x3_t t;} /* { dg-error {unknown type name 'vint64m2x3_t'} } */ +void f_vuint64m2x3_t () {vuint64m2x3_t t;} /* { dg-error {unknown type name 'vuint64m2x3_t'} } */ +void f_vint64m2x4_t () {vint64m2x4_t t;} /* { dg-error {unknown type name 'vint64m2x4_t'} } */ +void f_vuint64m2x4_t () {vuint64m2x4_t t;} /* { dg-error {unknown type name 'vuint64m2x4_t'} } */ +void f_vint64m4x2_t () {vint64m4x2_t t;} /* { dg-error {unknown type name 'vint64m4x2_t'} } */ +void f_vuint64m4x2_t () {vuint64m4x2_t t;} /* { dg-error {unknown type name 'vuint64m4x2_t'} } */ +void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} +void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} +void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} +void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;} +void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;} +void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;} +void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;} +void f_vfloat32m1x2_t () {vfloat32m1x2_t t;} +void f_vfloat32m1x3_t () {vfloat32m1x3_t t;} +void f_vfloat32m1x4_t () {vfloat32m1x4_t t;} +void f_vfloat32m1x5_t () {vfloat32m1x5_t t;} +void f_vfloat32m1x6_t () {vfloat32m1x6_t t;} +void f_vfloat32m1x7_t () {vfloat32m1x7_t t;} +void f_vfloat32m1x8_t () {vfloat32m1x8_t t;} +void f_vfloat32m2x2_t () {vfloat32m2x2_t t;} +void f_vfloat32m2x3_t () {vfloat32m2x3_t t;} +void f_vfloat32m2x4_t () {vfloat32m2x4_t t;} +void f_vfloat32m4x2_t () {vfloat32m4x2_t t;} +void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} /* { dg-error {unknown type name 'vfloat64m1x2_t'} } */ +void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} /* { dg-error {unknown type name 'vfloat64m1x3_t'} } */ +void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} /* { dg-error {unknown type name 'vfloat64m1x4_t'} } */ +void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} /* { dg-error {unknown type name 'vfloat64m1x5_t'} } */ +void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} /* { dg-error {unknown type name 'vfloat64m1x6_t'} } */ +void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} /* { dg-error {unknown type name 'vfloat64m1x7_t'} } */ +void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} /* { dg-error {unknown type name 'vfloat64m1x8_t'} } */ +void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} /* { dg-error {unknown type name 'vfloat64m2x2_t'} } */ +void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} /* { dg-error {unknown type name 'vfloat64m2x3_t'} } */ +void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} /* { dg-error {unknown type name 'vfloat64m2x4_t'} } */ +void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} /* { dg-error {unknown type name 'vfloat64m4x2_t'} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c new file mode 100644 index 00000000000..2172a5c7c79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-7.c @@ -0,0 +1,204 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */ + +void f_vint8mf8x2_t () {vint8mf8x2_t t;} /* { dg-error {unknown type name 'vint8mf8x2_t'} } */ +void f_vuint8mf8x2_t () {vuint8mf8x2_t t;} /* { dg-error {unknown type name 'vuint8mf8x2_t'} } */ +void f_vint8mf8x3_t () {vint8mf8x3_t t;} /* { dg-error {unknown type name 'vint8mf8x3_t'} } */ +void f_vuint8mf8x3_t () {vuint8mf8x3_t t;} /* { dg-error {unknown type name 'vuint8mf8x3_t'} } */ +void f_vint8mf8x4_t () {vint8mf8x4_t t;} /* { dg-error {unknown type name 'vint8mf8x4_t'} } */ +void f_vuint8mf8x4_t () {vuint8mf8x4_t t;} /* { dg-error {unknown type name 'vuint8mf8x4_t'} } */ +void f_vint8mf8x5_t () {vint8mf8x5_t t;} /* { dg-error {unknown type name 'vint8mf8x5_t'} } */ +void f_vuint8mf8x5_t () {vuint8mf8x5_t t;} /* { dg-error {unknown type name 'vuint8mf8x5_t'} } */ +void f_vint8mf8x6_t () {vint8mf8x6_t t;} /* { dg-error {unknown type name 'vint8mf8x6_t'} } */ +void f_vuint8mf8x6_t () {vuint8mf8x6_t t;} /* { dg-error {unknown type name 'vuint8mf8x6_t'} } */ +void f_vint8mf8x7_t () {vint8mf8x7_t t;} /* { dg-error {unknown type name 'vint8mf8x7_t'} } */ +void f_vuint8mf8x7_t () {vuint8mf8x7_t t;} /* { dg-error {unknown type name 'vuint8mf8x7_t'} } */ +void f_vint8mf8x8_t () {vint8mf8x8_t t;} /* { dg-error {unknown type name 'vint8mf8x8_t'} } */ +void f_vuint8mf8x8_t () {vuint8mf8x8_t t;} /* { dg-error {unknown type name 'vuint8mf8x8_t'} } */ +void f_vint8mf4x2_t () {vint8mf4x2_t t;} /* { dg-error {unknown type name 'vint8mf4x2_t'} } */ +void f_vuint8mf4x2_t () {vuint8mf4x2_t t;} /* { dg-error {unknown type name 'vuint8mf4x2_t'} } */ +void f_vint8mf4x3_t () {vint8mf4x3_t t;} /* { dg-error {unknown type name 'vint8mf4x3_t'} } */ +void f_vuint8mf4x3_t () {vuint8mf4x3_t t;} /* { dg-error {unknown type name 'vuint8mf4x3_t'} } */ +void f_vint8mf4x4_t () {vint8mf4x4_t t;} /* { dg-error {unknown type name 'vint8mf4x4_t'} } */ +void f_vuint8mf4x4_t () {vuint8mf4x4_t t;} /* { dg-error {unknown type name 'vuint8mf4x4_t'} } */ +void f_vint8mf4x5_t () {vint8mf4x5_t t;} /* { dg-error {unknown type name 'vint8mf4x5_t'} } */ +void f_vuint8mf4x5_t () {vuint8mf4x5_t t;} /* { dg-error {unknown type name 'vuint8mf4x5_t'} } */ +void f_vint8mf4x6_t () {vint8mf4x6_t t;} /* { dg-error {unknown type name 'vint8mf4x6_t'} } */ +void f_vuint8mf4x6_t () {vuint8mf4x6_t t;} /* { dg-error {unknown type name 'vuint8mf4x6_t'} } */ +void f_vint8mf4x7_t () {vint8mf4x7_t t;} /* { dg-error {unknown type name 'vint8mf4x7_t'} } */ +void f_vuint8mf4x7_t () {vuint8mf4x7_t t;} /* { dg-error {unknown type name 'vuint8mf4x7_t'} } */ +void f_vint8mf4x8_t () {vint8mf4x8_t t;} /* { dg-error {unknown type name 'vint8mf4x8_t'} } */ +void f_vuint8mf4x8_t () {vuint8mf4x8_t t;} /* { dg-error {unknown type name 'vuint8mf4x8_t'} } */ +void f_vint8mf2x2_t () {vint8mf2x2_t t;} /* { dg-error {unknown type name 'vint8mf2x2_t'} } */ +void f_vuint8mf2x2_t () {vuint8mf2x2_t t;} /* { dg-error {unknown type name 'vuint8mf2x2_t'} } */ +void f_vint8mf2x3_t () {vint8mf2x3_t t;} /* { dg-error {unknown type name 'vint8mf2x3_t'} } */ +void f_vuint8mf2x3_t () {vuint8mf2x3_t t;} /* { dg-error {unknown type name 'vuint8mf2x3_t'} } */ +void f_vint8mf2x4_t () {vint8mf2x4_t t;} /* { dg-error {unknown type name 'vint8mf2x4_t'} } */ +void f_vuint8mf2x4_t () {vuint8mf2x4_t t;} /* { dg-error {unknown type name 'vuint8mf2x4_t'} } */ +void f_vint8mf2x5_t () {vint8mf2x5_t t;} /* { dg-error {unknown type name 'vint8mf2x5_t'} } */ +void f_vuint8mf2x5_t () {vuint8mf2x5_t t;} /* { dg-error {unknown type name 'vuint8mf2x5_t'} } */ +void f_vint8mf2x6_t () {vint8mf2x6_t t;} /* { dg-error {unknown type name 'vint8mf2x6_t'} } */ +void f_vuint8mf2x6_t () {vuint8mf2x6_t t;} /* { dg-error {unknown type name 'vuint8mf2x6_t'} } */ +void f_vint8mf2x7_t () {vint8mf2x7_t t;} /* { dg-error {unknown type name 'vint8mf2x7_t'} } */ +void f_vuint8mf2x7_t () {vuint8mf2x7_t t;} /* { dg-error {unknown type name 'vuint8mf2x7_t'} } */ +void f_vint8mf2x8_t () {vint8mf2x8_t t;} /* { dg-error {unknown type name 'vint8mf2x8_t'} } */ +void f_vuint8mf2x8_t () {vuint8mf2x8_t t;} /* { dg-error {unknown type name 'vuint8mf2x8_t'} } */ +void f_vint8m1x2_t () {vint8m1x2_t t;} /* { dg-error {unknown type name 'vint8m1x2_t'} } */ +void f_vuint8m1x2_t () {vuint8m1x2_t t;} /* { dg-error {unknown type name 'vuint8m1x2_t'} } */ +void f_vint8m1x3_t () {vint8m1x3_t t;} /* { dg-error {unknown type name 'vint8m1x3_t'} } */ +void f_vuint8m1x3_t () {vuint8m1x3_t t;} /* { dg-error {unknown type name 'vuint8m1x3_t'} } */ +void f_vint8m1x4_t () {vint8m1x4_t t;} /* { dg-error {unknown type name 'vint8m1x4_t'} } */ +void f_vuint8m1x4_t () {vuint8m1x4_t t;} /* { dg-error {unknown type name 'vuint8m1x4_t'} } */ +void f_vint8m1x5_t () {vint8m1x5_t t;} /* { dg-error {unknown type name 'vint8m1x5_t'} } */ +void f_vuint8m1x5_t () {vuint8m1x5_t t;} /* { dg-error {unknown type name 'vuint8m1x5_t'} } */ +void f_vint8m1x6_t () {vint8m1x6_t t;} /* { dg-error {unknown type name 'vint8m1x6_t'} } */ +void f_vuint8m1x6_t () {vuint8m1x6_t t;} /* { dg-error {unknown type name 'vuint8m1x6_t'} } */ +void f_vint8m1x7_t () {vint8m1x7_t t;} /* { dg-error {unknown type name 'vint8m1x7_t'} } */ +void f_vuint8m1x7_t () {vuint8m1x7_t t;} /* { dg-error {unknown type name 'vuint8m1x7_t'} } */ +void f_vint8m1x8_t () {vint8m1x8_t t;} /* { dg-error {unknown type name 'vint8m1x8_t'} } */ +void f_vuint8m1x8_t () {vuint8m1x8_t t;} /* { dg-error {unknown type name 'vuint8m1x8_t'} } */ +void f_vint8m2x2_t () {vint8m2x2_t t;} /* { dg-error {unknown type name 'vint8m2x2_t'} } */ +void f_vuint8m2x2_t () {vuint8m2x2_t t;} /* { dg-error {unknown type name 'vuint8m2x2_t'} } */ +void f_vint8m2x3_t () {vint8m2x3_t t;} /* { dg-error {unknown type name 'vint8m2x3_t'} } */ +void f_vuint8m2x3_t () {vuint8m2x3_t t;} /* { dg-error {unknown type name 'vuint8m2x3_t'} } */ +void f_vint8m2x4_t () {vint8m2x4_t t;} /* { dg-error {unknown type name 'vint8m2x4_t'} } */ +void f_vuint8m2x4_t () {vuint8m2x4_t t;} /* { dg-error {unknown type name 'vuint8m2x4_t'} } */ +void f_vint8m4x2_t () {vint8m4x2_t t;} /* { dg-error {unknown type name 'vint8m4x2_t'} } */ +void f_vuint8m4x2_t () {vuint8m4x2_t t;} /* { dg-error {unknown type name 'vuint8m4x2_t'} } */ +void f_vint16mf4x2_t () {vint16mf4x2_t t;} /* { dg-error {unknown type name 'vint16mf4x2_t'} } */ +void f_vuint16mf4x2_t () {vuint16mf4x2_t t;} /* { dg-error {unknown type name 'vuint16mf4x2_t'} } */ +void f_vint16mf4x3_t () {vint16mf4x3_t t;} /* { dg-error {unknown type name 'vint16mf4x3_t'} } */ +void f_vuint16mf4x3_t () {vuint16mf4x3_t t;} /* { dg-error {unknown type name 'vuint16mf4x3_t'} } */ +void f_vint16mf4x4_t () {vint16mf4x4_t t;} /* { dg-error {unknown type name 'vint16mf4x4_t'} } */ +void f_vuint16mf4x4_t () {vuint16mf4x4_t t;} /* { dg-error {unknown type name 'vuint16mf4x4_t'} } */ +void f_vint16mf4x5_t () {vint16mf4x5_t t;} /* { dg-error {unknown type name 'vint16mf4x5_t'} } */ +void f_vuint16mf4x5_t () {vuint16mf4x5_t t;} /* { dg-error {unknown type name 'vuint16mf4x5_t'} } */ +void f_vint16mf4x6_t () {vint16mf4x6_t t;} /* { dg-error {unknown type name 'vint16mf4x6_t'} } */ +void f_vuint16mf4x6_t () {vuint16mf4x6_t t;} /* { dg-error {unknown type name 'vuint16mf4x6_t'} } */ +void f_vint16mf4x7_t () {vint16mf4x7_t t;} /* { dg-error {unknown type name 'vint16mf4x7_t'} } */ +void f_vuint16mf4x7_t () {vuint16mf4x7_t t;} /* { dg-error {unknown type name 'vuint16mf4x7_t'} } */ +void f_vint16mf4x8_t () {vint16mf4x8_t t;} /* { dg-error {unknown type name 'vint16mf4x8_t'} } */ +void f_vuint16mf4x8_t () {vuint16mf4x8_t t;} /* { dg-error {unknown type name 'vuint16mf4x8_t'} } */ +void f_vint16mf2x2_t () {vint16mf2x2_t t;} /* { dg-error {unknown type name 'vint16mf2x2_t'} } */ +void f_vuint16mf2x2_t () {vuint16mf2x2_t t;} /* { dg-error {unknown type name 'vuint16mf2x2_t'} } */ +void f_vint16mf2x3_t () {vint16mf2x3_t t;} /* { dg-error {unknown type name 'vint16mf2x3_t'} } */ +void f_vuint16mf2x3_t () {vuint16mf2x3_t t;} /* { dg-error {unknown type name 'vuint16mf2x3_t'} } */ +void f_vint16mf2x4_t () {vint16mf2x4_t t;} /* { dg-error {unknown type name 'vint16mf2x4_t'} } */ +void f_vuint16mf2x4_t () {vuint16mf2x4_t t;} /* { dg-error {unknown type name 'vuint16mf2x4_t'} } */ +void f_vint16mf2x5_t () {vint16mf2x5_t t;} /* { dg-error {unknown type name 'vint16mf2x5_t'} } */ +void f_vuint16mf2x5_t () {vuint16mf2x5_t t;} /* { dg-error {unknown type name 'vuint16mf2x5_t'} } */ +void f_vint16mf2x6_t () {vint16mf2x6_t t;} /* { dg-error {unknown type name 'vint16mf2x6_t'} } */ +void f_vuint16mf2x6_t () {vuint16mf2x6_t t;} /* { dg-error {unknown type name 'vuint16mf2x6_t'} } */ +void f_vint16mf2x7_t () {vint16mf2x7_t t;} /* { dg-error {unknown type name 'vint16mf2x7_t'} } */ +void f_vuint16mf2x7_t () {vuint16mf2x7_t t;} /* { dg-error {unknown type name 'vuint16mf2x7_t'} } */ +void f_vint16mf2x8_t () {vint16mf2x8_t t;} /* { dg-error {unknown type name 'vint16mf2x8_t'} } */ +void f_vuint16mf2x8_t () {vuint16mf2x8_t t;} /* { dg-error {unknown type name 'vuint16mf2x8_t'} } */ +void f_vint16m1x2_t () {vint16m1x2_t t;} /* { dg-error {unknown type name 'vint16m1x2_t'} } */ +void f_vuint16m1x2_t () {vuint16m1x2_t t;} /* { dg-error {unknown type name 'vuint16m1x2_t'} } */ +void f_vint16m1x3_t () {vint16m1x3_t t;} /* { dg-error {unknown type name 'vint16m1x3_t'} } */ +void f_vuint16m1x3_t () {vuint16m1x3_t t;} /* { dg-error {unknown type name 'vuint16m1x3_t'} } */ +void f_vint16m1x4_t () {vint16m1x4_t t;} /* { dg-error {unknown type name 'vint16m1x4_t'} } */ +void f_vuint16m1x4_t () {vuint16m1x4_t t;} /* { dg-error {unknown type name 'vuint16m1x4_t'} } */ +void f_vint16m1x5_t () {vint16m1x5_t t;} /* { dg-error {unknown type name 'vint16m1x5_t'} } */ +void f_vuint16m1x5_t () {vuint16m1x5_t t;} /* { dg-error {unknown type name 'vuint16m1x5_t'} } */ +void f_vint16m1x6_t () {vint16m1x6_t t;} /* { dg-error {unknown type name 'vint16m1x6_t'} } */ +void f_vuint16m1x6_t () {vuint16m1x6_t t;} /* { dg-error {unknown type name 'vuint16m1x6_t'} } */ +void f_vint16m1x7_t () {vint16m1x7_t t;} /* { dg-error {unknown type name 'vint16m1x7_t'} } */ +void f_vuint16m1x7_t () {vuint16m1x7_t t;} /* { dg-error {unknown type name 'vuint16m1x7_t'} } */ +void f_vint16m1x8_t () {vint16m1x8_t t;} /* { dg-error {unknown type name 'vint16m1x8_t'} } */ +void f_vuint16m1x8_t () {vuint16m1x8_t t;} /* { dg-error {unknown type name 'vuint16m1x8_t'} } */ +void f_vint16m2x2_t () {vint16m2x2_t t;} /* { dg-error {unknown type name 'vint16m2x2_t'} } */ +void f_vuint16m2x2_t () {vuint16m2x2_t t;} /* { dg-error {unknown type name 'vuint16m2x2_t'} } */ +void f_vint16m2x3_t () {vint16m2x3_t t;} /* { dg-error {unknown type name 'vint16m2x3_t'} } */ +void f_vuint16m2x3_t () {vuint16m2x3_t t;} /* { dg-error {unknown type name 'vuint16m2x3_t'} } */ +void f_vint16m2x4_t () {vint16m2x4_t t;} /* { dg-error {unknown type name 'vint16m2x4_t'} } */ +void f_vuint16m2x4_t () {vuint16m2x4_t t;} /* { dg-error {unknown type name 'vuint16m2x4_t'} } */ +void f_vint16m4x2_t () {vint16m4x2_t t;} /* { dg-error {unknown type name 'vint16m4x2_t'} } */ +void f_vuint16m4x2_t () {vuint16m4x2_t t;} /* { dg-error {unknown type name 'vuint16m4x2_t'} } */ +void f_vint32mf2x2_t () {vint32mf2x2_t t;} /* { dg-error {unknown type name 'vint32mf2x2_t'} } */ +void f_vuint32mf2x2_t () {vuint32mf2x2_t t;} /* { dg-error {unknown type name 'vuint32mf2x2_t'} } */ +void f_vint32mf2x3_t () {vint32mf2x3_t t;} /* { dg-error {unknown type name 'vint32mf2x3_t'} } */ +void f_vuint32mf2x3_t () {vuint32mf2x3_t t;} /* { dg-error {unknown type name 'vuint32mf2x3_t'} } */ +void f_vint32mf2x4_t () {vint32mf2x4_t t;} /* { dg-error {unknown type name 'vint32mf2x4_t'} } */ +void f_vuint32mf2x4_t () {vuint32mf2x4_t t;} /* { dg-error {unknown type name 'vuint32mf2x4_t'} } */ +void f_vint32mf2x5_t () {vint32mf2x5_t t;} /* { dg-error {unknown type name 'vint32mf2x5_t'} } */ +void f_vuint32mf2x5_t () {vuint32mf2x5_t t;} /* { dg-error {unknown type name 'vuint32mf2x5_t'} } */ +void f_vint32mf2x6_t () {vint32mf2x6_t t;} /* { dg-error {unknown type name 'vint32mf2x6_t'} } */ +void f_vuint32mf2x6_t () {vuint32mf2x6_t t;} /* { dg-error {unknown type name 'vuint32mf2x6_t'} } */ +void f_vint32mf2x7_t () {vint32mf2x7_t t;} /* { dg-error {unknown type name 'vint32mf2x7_t'} } */ +void f_vuint32mf2x7_t () {vuint32mf2x7_t t;} /* { dg-error {unknown type name 'vuint32mf2x7_t'} } */ +void f_vint32mf2x8_t () {vint32mf2x8_t t;} /* { dg-error {unknown type name 'vint32mf2x8_t'} } */ +void f_vuint32mf2x8_t () {vuint32mf2x8_t t;} /* { dg-error {unknown type name 'vuint32mf2x8_t'} } */ +void f_vint32m1x2_t () {vint32m1x2_t t;} /* { dg-error {unknown type name 'vint32m1x2_t'} } */ +void f_vuint32m1x2_t () {vuint32m1x2_t t;} /* { dg-error {unknown type name 'vuint32m1x2_t'} } */ +void f_vint32m1x3_t () {vint32m1x3_t t;} /* { dg-error {unknown type name 'vint32m1x3_t'} } */ +void f_vuint32m1x3_t () {vuint32m1x3_t t;} /* { dg-error {unknown type name 'vuint32m1x3_t'} } */ +void f_vint32m1x4_t () {vint32m1x4_t t;} /* { dg-error {unknown type name 'vint32m1x4_t'} } */ +void f_vuint32m1x4_t () {vuint32m1x4_t t;} /* { dg-error {unknown type name 'vuint32m1x4_t'} } */ +void f_vint32m1x5_t () {vint32m1x5_t t;} /* { dg-error {unknown type name 'vint32m1x5_t'} } */ +void f_vuint32m1x5_t () {vuint32m1x5_t t;} /* { dg-error {unknown type name 'vuint32m1x5_t'} } */ +void f_vint32m1x6_t () {vint32m1x6_t t;} /* { dg-error {unknown type name 'vint32m1x6_t'} } */ +void f_vuint32m1x6_t () {vuint32m1x6_t t;} /* { dg-error {unknown type name 'vuint32m1x6_t'} } */ +void f_vint32m1x7_t () {vint32m1x7_t t;} /* { dg-error {unknown type name 'vint32m1x7_t'} } */ +void f_vuint32m1x7_t () {vuint32m1x7_t t;} /* { dg-error {unknown type name 'vuint32m1x7_t'} } */ +void f_vint32m1x8_t () {vint32m1x8_t t;} /* { dg-error {unknown type name 'vint32m1x8_t'} } */ +void f_vuint32m1x8_t () {vuint32m1x8_t t;} /* { dg-error {unknown type name 'vuint32m1x8_t'} } */ +void f_vint32m2x2_t () {vint32m2x2_t t;} /* { dg-error {unknown type name 'vint32m2x2_t'} } */ +void f_vuint32m2x2_t () {vuint32m2x2_t t;} /* { dg-error {unknown type name 'vuint32m2x2_t'} } */ +void f_vint32m2x3_t () {vint32m2x3_t t;} /* { dg-error {unknown type name 'vint32m2x3_t'} } */ +void f_vuint32m2x3_t () {vuint32m2x3_t t;} /* { dg-error {unknown type name 'vuint32m2x3_t'} } */ +void f_vint32m2x4_t () {vint32m2x4_t t;} /* { dg-error {unknown type name 'vint32m2x4_t'} } */ +void f_vuint32m2x4_t () {vuint32m2x4_t t;} /* { dg-error {unknown type name 'vuint32m2x4_t'} } */ +void f_vint32m4x2_t () {vint32m4x2_t t;} /* { dg-error {unknown type name 'vint32m4x2_t'} } */ +void f_vuint32m4x2_t () {vuint32m4x2_t t;} /* { dg-error {unknown type name 'vuint32m4x2_t'} } */ +void f_vint64m1x2_t () {vint64m1x2_t t;} /* { dg-error {unknown type name 'vint64m1x2_t'} } */ +void f_vuint64m1x2_t () {vuint64m1x2_t t;} /* { dg-error {unknown type name 'vuint64m1x2_t'} } */ +void f_vint64m1x3_t () {vint64m1x3_t t;} /* { dg-error {unknown type name 'vint64m1x3_t'} } */ +void f_vuint64m1x3_t () {vuint64m1x3_t t;} /* { dg-error {unknown type name 'vuint64m1x3_t'} } */ +void f_vint64m1x4_t () {vint64m1x4_t t;} /* { dg-error {unknown type name 'vint64m1x4_t'} } */ +void f_vuint64m1x4_t () {vuint64m1x4_t t;} /* { dg-error {unknown type name 'vuint64m1x4_t'} } */ +void f_vint64m1x5_t () {vint64m1x5_t t;} /* { dg-error {unknown type name 'vint64m1x5_t'} } */ +void f_vuint64m1x5_t () {vuint64m1x5_t t;} /* { dg-error {unknown type name 'vuint64m1x5_t'} } */ +void f_vint64m1x6_t () {vint64m1x6_t t;} /* { dg-error {unknown type name 'vint64m1x6_t'} } */ +void f_vuint64m1x6_t () {vuint64m1x6_t t;} /* { dg-error {unknown type name 'vuint64m1x6_t'} } */ +void f_vint64m1x7_t () {vint64m1x7_t t;} /* { dg-error {unknown type name 'vint64m1x7_t'} } */ +void f_vuint64m1x7_t () {vuint64m1x7_t t;} /* { dg-error {unknown type name 'vuint64m1x7_t'} } */ +void f_vint64m1x8_t () {vint64m1x8_t t;} /* { dg-error {unknown type name 'vint64m1x8_t'} } */ +void f_vuint64m1x8_t () {vuint64m1x8_t t;} /* { dg-error {unknown type name 'vuint64m1x8_t'} } */ +void f_vint64m2x2_t () {vint64m2x2_t t;} /* { dg-error {unknown type name 'vint64m2x2_t'} } */ +void f_vuint64m2x2_t () {vuint64m2x2_t t;} /* { dg-error {unknown type name 'vuint64m2x2_t'} } */ +void f_vint64m2x3_t () {vint64m2x3_t t;} /* { dg-error {unknown type name 'vint64m2x3_t'} } */ +void f_vuint64m2x3_t () {vuint64m2x3_t t;} /* { dg-error {unknown type name 'vuint64m2x3_t'} } */ +void f_vint64m2x4_t () {vint64m2x4_t t;} /* { dg-error {unknown type name 'vint64m2x4_t'} } */ +void f_vuint64m2x4_t () {vuint64m2x4_t t;} /* { dg-error {unknown type name 'vuint64m2x4_t'} } */ +void f_vint64m4x2_t () {vint64m4x2_t t;} /* { dg-error {unknown type name 'vint64m4x2_t'} } */ +void f_vuint64m4x2_t () {vuint64m4x2_t t;} /* { dg-error {unknown type name 'vuint64m4x2_t'} } */ +void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} /* { dg-error {unknown type name 'vfloat32mf2x2_t'} } */ +void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} /* { dg-error {unknown type name 'vfloat32mf2x3_t'} } */ +void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} /* { dg-error {unknown type name 'vfloat32mf2x4_t'} } */ +void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;} /* { dg-error {unknown type name 'vfloat32mf2x5_t'} } */ +void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;} /* { dg-error {unknown type name 'vfloat32mf2x6_t'} } */ +void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;} /* { dg-error {unknown type name 'vfloat32mf2x7_t'} } */ +void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;} /* { dg-error {unknown type name 'vfloat32mf2x8_t'} } */ +void f_vfloat32m1x2_t () {vfloat32m1x2_t t;} /* { dg-error {unknown type name 'vfloat32m1x2_t'} } */ +void f_vfloat32m1x3_t () {vfloat32m1x3_t t;} /* { dg-error {unknown type name 'vfloat32m1x3_t'} } */ +void f_vfloat32m1x4_t () {vfloat32m1x4_t t;} /* { dg-error {unknown type name 'vfloat32m1x4_t'} } */ +void f_vfloat32m1x5_t () {vfloat32m1x5_t t;} /* { dg-error {unknown type name 'vfloat32m1x5_t'} } */ +void f_vfloat32m1x6_t () {vfloat32m1x6_t t;} /* { dg-error {unknown type name 'vfloat32m1x6_t'} } */ +void f_vfloat32m1x7_t () {vfloat32m1x7_t t;} /* { dg-error {unknown type name 'vfloat32m1x7_t'} } */ +void f_vfloat32m1x8_t () {vfloat32m1x8_t t;} /* { dg-error {unknown type name 'vfloat32m1x8_t'} } */ +void f_vfloat32m2x2_t () {vfloat32m2x2_t t;} /* { dg-error {unknown type name 'vfloat32m2x2_t'} } */ +void f_vfloat32m2x3_t () {vfloat32m2x3_t t;} /* { dg-error {unknown type name 'vfloat32m2x3_t'} } */ +void f_vfloat32m2x4_t () {vfloat32m2x4_t t;} /* { dg-error {unknown type name 'vfloat32m2x4_t'} } */ +void f_vfloat32m4x2_t () {vfloat32m4x2_t t;} /* { dg-error {unknown type name 'vfloat32m4x2_t'} } */ +void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} /* { dg-error {unknown type name 'vfloat64m1x2_t'} } */ +void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} /* { dg-error {unknown type name 'vfloat64m1x3_t'} } */ +void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} /* { dg-error {unknown type name 'vfloat64m1x4_t'} } */ +void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} /* { dg-error {unknown type name 'vfloat64m1x5_t'} } */ +void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} /* { dg-error {unknown type name 'vfloat64m1x6_t'} } */ +void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} /* { dg-error {unknown type name 'vfloat64m1x7_t'} } */ +void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} /* { dg-error {unknown type name 'vfloat64m1x8_t'} } */ +void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} /* { dg-error {unknown type name 'vfloat64m2x2_t'} } */ +void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} /* { dg-error {unknown type name 'vfloat64m2x3_t'} } */ +void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} /* { dg-error {unknown type name 'vfloat64m2x4_t'} } */ +void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} /* { dg-error {unknown type name 'vfloat64m4x2_t'} } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-8.c new file mode 100644 index 00000000000..b666c4a1080 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-8.c @@ -0,0 +1,206 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */ + +#include "riscv_vector.h" + +void f_vint8mf8x2_t () {vint8mf8x2_t t;} +void f_vuint8mf8x2_t () {vuint8mf8x2_t t;} +void f_vint8mf8x3_t () {vint8mf8x3_t t;} +void f_vuint8mf8x3_t () {vuint8mf8x3_t t;} +void f_vint8mf8x4_t () {vint8mf8x4_t t;} +void f_vuint8mf8x4_t () {vuint8mf8x4_t t;} +void f_vint8mf8x5_t () {vint8mf8x5_t t;} +void f_vuint8mf8x5_t () {vuint8mf8x5_t t;} +void f_vint8mf8x6_t () {vint8mf8x6_t t;} +void f_vuint8mf8x6_t () {vuint8mf8x6_t t;} +void f_vint8mf8x7_t () {vint8mf8x7_t t;} +void f_vuint8mf8x7_t () {vuint8mf8x7_t t;} +void f_vint8mf8x8_t () {vint8mf8x8_t t;} +void f_vuint8mf8x8_t () {vuint8mf8x8_t t;} +void f_vint8mf4x2_t () {vint8mf4x2_t t;} +void f_vuint8mf4x2_t () {vuint8mf4x2_t t;} +void f_vint8mf4x3_t () {vint8mf4x3_t t;} +void f_vuint8mf4x3_t () {vuint8mf4x3_t t;} +void f_vint8mf4x4_t () {vint8mf4x4_t t;} +void f_vuint8mf4x4_t () {vuint8mf4x4_t t;} +void f_vint8mf4x5_t () {vint8mf4x5_t t;} +void f_vuint8mf4x5_t () {vuint8mf4x5_t t;} +void f_vint8mf4x6_t () {vint8mf4x6_t t;} +void f_vuint8mf4x6_t () {vuint8mf4x6_t t;} +void f_vint8mf4x7_t () {vint8mf4x7_t t;} +void f_vuint8mf4x7_t () {vuint8mf4x7_t t;} +void f_vint8mf4x8_t () {vint8mf4x8_t t;} +void f_vuint8mf4x8_t () {vuint8mf4x8_t t;} +void f_vint8mf2x2_t () {vint8mf2x2_t t;} +void f_vuint8mf2x2_t () {vuint8mf2x2_t t;} +void f_vint8mf2x3_t () {vint8mf2x3_t t;} +void f_vuint8mf2x3_t () {vuint8mf2x3_t t;} +void f_vint8mf2x4_t () {vint8mf2x4_t t;} +void f_vuint8mf2x4_t () {vuint8mf2x4_t t;} +void f_vint8mf2x5_t () {vint8mf2x5_t t;} +void f_vuint8mf2x5_t () {vuint8mf2x5_t t;} +void f_vint8mf2x6_t () {vint8mf2x6_t t;} +void f_vuint8mf2x6_t () {vuint8mf2x6_t t;} +void f_vint8mf2x7_t () {vint8mf2x7_t t;} +void f_vuint8mf2x7_t () {vuint8mf2x7_t t;} +void f_vint8mf2x8_t () {vint8mf2x8_t t;} +void f_vuint8mf2x8_t () {vuint8mf2x8_t t;} +void f_vint8m1x2_t () {vint8m1x2_t t;} +void f_vuint8m1x2_t () {vuint8m1x2_t t;} +void f_vint8m1x3_t () {vint8m1x3_t t;} +void f_vuint8m1x3_t () {vuint8m1x3_t t;} +void f_vint8m1x4_t () {vint8m1x4_t t;} +void f_vuint8m1x4_t () {vuint8m1x4_t t;} +void f_vint8m1x5_t () {vint8m1x5_t t;} +void f_vuint8m1x5_t () {vuint8m1x5_t t;} +void f_vint8m1x6_t () {vint8m1x6_t t;} +void f_vuint8m1x6_t () {vuint8m1x6_t t;} +void f_vint8m1x7_t () {vint8m1x7_t t;} +void f_vuint8m1x7_t () {vuint8m1x7_t t;} +void f_vint8m1x8_t () {vint8m1x8_t t;} +void f_vuint8m1x8_t () {vuint8m1x8_t t;} +void f_vint8m2x2_t () {vint8m2x2_t t;} +void f_vuint8m2x2_t () {vuint8m2x2_t t;} +void f_vint8m2x3_t () {vint8m2x3_t t;} +void f_vuint8m2x3_t () {vuint8m2x3_t t;} +void f_vint8m2x4_t () {vint8m2x4_t t;} +void f_vuint8m2x4_t () {vuint8m2x4_t t;} +void f_vint8m4x2_t () {vint8m4x2_t t;} +void f_vuint8m4x2_t () {vuint8m4x2_t t;} +void f_vint16mf4x2_t () {vint16mf4x2_t t;} +void f_vuint16mf4x2_t () {vuint16mf4x2_t t;} +void f_vint16mf4x3_t () {vint16mf4x3_t t;} +void f_vuint16mf4x3_t () {vuint16mf4x3_t t;} +void f_vint16mf4x4_t () {vint16mf4x4_t t;} +void f_vuint16mf4x4_t () {vuint16mf4x4_t t;} +void f_vint16mf4x5_t () {vint16mf4x5_t t;} +void f_vuint16mf4x5_t () {vuint16mf4x5_t t;} +void f_vint16mf4x6_t () {vint16mf4x6_t t;} +void f_vuint16mf4x6_t () {vuint16mf4x6_t t;} +void f_vint16mf4x7_t () {vint16mf4x7_t t;} +void f_vuint16mf4x7_t () {vuint16mf4x7_t t;} +void f_vint16mf4x8_t () {vint16mf4x8_t t;} +void f_vuint16mf4x8_t () {vuint16mf4x8_t t;} +void f_vint16mf2x2_t () {vint16mf2x2_t t;} +void f_vuint16mf2x2_t () {vuint16mf2x2_t t;} +void f_vint16mf2x3_t () {vint16mf2x3_t t;} +void f_vuint16mf2x3_t () {vuint16mf2x3_t t;} +void f_vint16mf2x4_t () {vint16mf2x4_t t;} +void f_vuint16mf2x4_t () {vuint16mf2x4_t t;} +void f_vint16mf2x5_t () {vint16mf2x5_t t;} +void f_vuint16mf2x5_t () {vuint16mf2x5_t t;} +void f_vint16mf2x6_t () {vint16mf2x6_t t;} +void f_vuint16mf2x6_t () {vuint16mf2x6_t t;} +void f_vint16mf2x7_t () {vint16mf2x7_t t;} +void f_vuint16mf2x7_t () {vuint16mf2x7_t t;} +void f_vint16mf2x8_t () {vint16mf2x8_t t;} +void f_vuint16mf2x8_t () {vuint16mf2x8_t t;} +void f_vint16m1x2_t () {vint16m1x2_t t;} +void f_vuint16m1x2_t () {vuint16m1x2_t t;} +void f_vint16m1x3_t () {vint16m1x3_t t;} +void f_vuint16m1x3_t () {vuint16m1x3_t t;} +void f_vint16m1x4_t () {vint16m1x4_t t;} +void f_vuint16m1x4_t () {vuint16m1x4_t t;} +void f_vint16m1x5_t () {vint16m1x5_t t;} +void f_vuint16m1x5_t () {vuint16m1x5_t t;} +void f_vint16m1x6_t () {vint16m1x6_t t;} +void f_vuint16m1x6_t () {vuint16m1x6_t t;} +void f_vint16m1x7_t () {vint16m1x7_t t;} +void f_vuint16m1x7_t () {vuint16m1x7_t t;} +void f_vint16m1x8_t () {vint16m1x8_t t;} +void f_vuint16m1x8_t () {vuint16m1x8_t t;} +void f_vint16m2x2_t () {vint16m2x2_t t;} +void f_vuint16m2x2_t () {vuint16m2x2_t t;} +void f_vint16m2x3_t () {vint16m2x3_t t;} +void f_vuint16m2x3_t () {vuint16m2x3_t t;} +void f_vint16m2x4_t () {vint16m2x4_t t;} +void f_vuint16m2x4_t () {vuint16m2x4_t t;} +void f_vint16m4x2_t () {vint16m4x2_t t;} +void f_vuint16m4x2_t () {vuint16m4x2_t t;} +void f_vint32mf2x2_t () {vint32mf2x2_t t;} +void f_vuint32mf2x2_t () {vuint32mf2x2_t t;} +void f_vint32mf2x3_t () {vint32mf2x3_t t;} +void f_vuint32mf2x3_t () {vuint32mf2x3_t t;} +void f_vint32mf2x4_t () {vint32mf2x4_t t;} +void f_vuint32mf2x4_t () {vuint32mf2x4_t t;} +void f_vint32mf2x5_t () {vint32mf2x5_t t;} +void f_vuint32mf2x5_t () {vuint32mf2x5_t t;} +void f_vint32mf2x6_t () {vint32mf2x6_t t;} +void f_vuint32mf2x6_t () {vuint32mf2x6_t t;} +void f_vint32mf2x7_t () {vint32mf2x7_t t;} +void f_vuint32mf2x7_t () {vuint32mf2x7_t t;} +void f_vint32mf2x8_t () {vint32mf2x8_t t;} +void f_vuint32mf2x8_t () {vuint32mf2x8_t t;} +void f_vint32m1x2_t () {vint32m1x2_t t;} +void f_vuint32m1x2_t () {vuint32m1x2_t t;} +void f_vint32m1x3_t () {vint32m1x3_t t;} +void f_vuint32m1x3_t () {vuint32m1x3_t t;} +void f_vint32m1x4_t () {vint32m1x4_t t;} +void f_vuint32m1x4_t () {vuint32m1x4_t t;} +void f_vint32m1x5_t () {vint32m1x5_t t;} +void f_vuint32m1x5_t () {vuint32m1x5_t t;} +void f_vint32m1x6_t () {vint32m1x6_t t;} +void f_vuint32m1x6_t () {vuint32m1x6_t t;} +void f_vint32m1x7_t () {vint32m1x7_t t;} +void f_vuint32m1x7_t () {vuint32m1x7_t t;} +void f_vint32m1x8_t () {vint32m1x8_t t;} +void f_vuint32m1x8_t () {vuint32m1x8_t t;} +void f_vint32m2x2_t () {vint32m2x2_t t;} +void f_vuint32m2x2_t () {vuint32m2x2_t t;} +void f_vint32m2x3_t () {vint32m2x3_t t;} +void f_vuint32m2x3_t () {vuint32m2x3_t t;} +void f_vint32m2x4_t () {vint32m2x4_t t;} +void f_vuint32m2x4_t () {vuint32m2x4_t t;} +void f_vint32m4x2_t () {vint32m4x2_t t;} +void f_vuint32m4x2_t () {vuint32m4x2_t t;} +void f_vint64m1x2_t () {vint64m1x2_t t;} +void f_vuint64m1x2_t () {vuint64m1x2_t t;} +void f_vint64m1x3_t () {vint64m1x3_t t;} +void f_vuint64m1x3_t () {vuint64m1x3_t t;} +void f_vint64m1x4_t () {vint64m1x4_t t;} +void f_vuint64m1x4_t () {vuint64m1x4_t t;} +void f_vint64m1x5_t () {vint64m1x5_t t;} +void f_vuint64m1x5_t () {vuint64m1x5_t t;} +void f_vint64m1x6_t () {vint64m1x6_t t;} +void f_vuint64m1x6_t () {vuint64m1x6_t t;} +void f_vint64m1x7_t () {vint64m1x7_t t;} +void f_vuint64m1x7_t () {vuint64m1x7_t t;} +void f_vint64m1x8_t () {vint64m1x8_t t;} +void f_vuint64m1x8_t () {vuint64m1x8_t t;} +void f_vint64m2x2_t () {vint64m2x2_t t;} +void f_vuint64m2x2_t () {vuint64m2x2_t t;} +void f_vint64m2x3_t () {vint64m2x3_t t;} +void f_vuint64m2x3_t () {vuint64m2x3_t t;} +void f_vint64m2x4_t () {vint64m2x4_t t;} +void f_vuint64m2x4_t () {vuint64m2x4_t t;} +void f_vint64m4x2_t () {vint64m4x2_t t;} +void f_vuint64m4x2_t () {vuint64m4x2_t t;} +void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} +void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} +void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} +void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;} +void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;} +void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;} +void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;} +void f_vfloat32m1x2_t () {vfloat32m1x2_t t;} +void f_vfloat32m1x3_t () {vfloat32m1x3_t t;} +void f_vfloat32m1x4_t () {vfloat32m1x4_t t;} +void f_vfloat32m1x5_t () {vfloat32m1x5_t t;} +void f_vfloat32m1x6_t () {vfloat32m1x6_t t;} +void f_vfloat32m1x7_t () {vfloat32m1x7_t t;} +void f_vfloat32m1x8_t () {vfloat32m1x8_t t;} +void f_vfloat32m2x2_t () {vfloat32m2x2_t t;} +void f_vfloat32m2x3_t () {vfloat32m2x3_t t;} +void f_vfloat32m2x4_t () {vfloat32m2x4_t t;} +void f_vfloat32m4x2_t () {vfloat32m4x2_t t;} +void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} +void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} +void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} +void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} +void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} +void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} +void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} +void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} +void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} +void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} +void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/user-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/user-9.c new file mode 100644 index 00000000000..98a7d391d4e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/user-9.c @@ -0,0 +1,206 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv32gc_zve64x -mabi=ilp32d" } */ + +#include "riscv_vector.h" + +void f_vint8mf8x2_t () {vint8mf8x2_t t;} +void f_vuint8mf8x2_t () {vuint8mf8x2_t t;} +void f_vint8mf8x3_t () {vint8mf8x3_t t;} +void f_vuint8mf8x3_t () {vuint8mf8x3_t t;} +void f_vint8mf8x4_t () {vint8mf8x4_t t;} +void f_vuint8mf8x4_t () {vuint8mf8x4_t t;} +void f_vint8mf8x5_t () {vint8mf8x5_t t;} +void f_vuint8mf8x5_t () {vuint8mf8x5_t t;} +void f_vint8mf8x6_t () {vint8mf8x6_t t;} +void f_vuint8mf8x6_t () {vuint8mf8x6_t t;} +void f_vint8mf8x7_t () {vint8mf8x7_t t;} +void f_vuint8mf8x7_t () {vuint8mf8x7_t t;} +void f_vint8mf8x8_t () {vint8mf8x8_t t;} +void f_vuint8mf8x8_t () {vuint8mf8x8_t t;} +void f_vint8mf4x2_t () {vint8mf4x2_t t;} +void f_vuint8mf4x2_t () {vuint8mf4x2_t t;} +void f_vint8mf4x3_t () {vint8mf4x3_t t;} +void f_vuint8mf4x3_t () {vuint8mf4x3_t t;} +void f_vint8mf4x4_t () {vint8mf4x4_t t;} +void f_vuint8mf4x4_t () {vuint8mf4x4_t t;} +void f_vint8mf4x5_t () {vint8mf4x5_t t;} +void f_vuint8mf4x5_t () {vuint8mf4x5_t t;} +void f_vint8mf4x6_t () {vint8mf4x6_t t;} +void f_vuint8mf4x6_t () {vuint8mf4x6_t t;} +void f_vint8mf4x7_t () {vint8mf4x7_t t;} +void f_vuint8mf4x7_t () {vuint8mf4x7_t t;} +void f_vint8mf4x8_t () {vint8mf4x8_t t;} +void f_vuint8mf4x8_t () {vuint8mf4x8_t t;} +void f_vint8mf2x2_t () {vint8mf2x2_t t;} +void f_vuint8mf2x2_t () {vuint8mf2x2_t t;} +void f_vint8mf2x3_t () {vint8mf2x3_t t;} +void f_vuint8mf2x3_t () {vuint8mf2x3_t t;} +void f_vint8mf2x4_t () {vint8mf2x4_t t;} +void f_vuint8mf2x4_t () {vuint8mf2x4_t t;} +void f_vint8mf2x5_t () {vint8mf2x5_t t;} +void f_vuint8mf2x5_t () {vuint8mf2x5_t t;} +void f_vint8mf2x6_t () {vint8mf2x6_t t;} +void f_vuint8mf2x6_t () {vuint8mf2x6_t t;} +void f_vint8mf2x7_t () {vint8mf2x7_t t;} +void f_vuint8mf2x7_t () {vuint8mf2x7_t t;} +void f_vint8mf2x8_t () {vint8mf2x8_t t;} +void f_vuint8mf2x8_t () {vuint8mf2x8_t t;} +void f_vint8m1x2_t () {vint8m1x2_t t;} +void f_vuint8m1x2_t () {vuint8m1x2_t t;} +void f_vint8m1x3_t () {vint8m1x3_t t;} +void f_vuint8m1x3_t () {vuint8m1x3_t t;} +void f_vint8m1x4_t () {vint8m1x4_t t;} +void f_vuint8m1x4_t () {vuint8m1x4_t t;} +void f_vint8m1x5_t () {vint8m1x5_t t;} +void f_vuint8m1x5_t () {vuint8m1x5_t t;} +void f_vint8m1x6_t () {vint8m1x6_t t;} +void f_vuint8m1x6_t () {vuint8m1x6_t t;} +void f_vint8m1x7_t () {vint8m1x7_t t;} +void f_vuint8m1x7_t () {vuint8m1x7_t t;} +void f_vint8m1x8_t () {vint8m1x8_t t;} +void f_vuint8m1x8_t () {vuint8m1x8_t t;} +void f_vint8m2x2_t () {vint8m2x2_t t;} +void f_vuint8m2x2_t () {vuint8m2x2_t t;} +void f_vint8m2x3_t () {vint8m2x3_t t;} +void f_vuint8m2x3_t () {vuint8m2x3_t t;} +void f_vint8m2x4_t () {vint8m2x4_t t;} +void f_vuint8m2x4_t () {vuint8m2x4_t t;} +void f_vint8m4x2_t () {vint8m4x2_t t;} +void f_vuint8m4x2_t () {vuint8m4x2_t t;} +void f_vint16mf4x2_t () {vint16mf4x2_t t;} +void f_vuint16mf4x2_t () {vuint16mf4x2_t t;} +void f_vint16mf4x3_t () {vint16mf4x3_t t;} +void f_vuint16mf4x3_t () {vuint16mf4x3_t t;} +void f_vint16mf4x4_t () {vint16mf4x4_t t;} +void f_vuint16mf4x4_t () {vuint16mf4x4_t t;} +void f_vint16mf4x5_t () {vint16mf4x5_t t;} +void f_vuint16mf4x5_t () {vuint16mf4x5_t t;} +void f_vint16mf4x6_t () {vint16mf4x6_t t;} +void f_vuint16mf4x6_t () {vuint16mf4x6_t t;} +void f_vint16mf4x7_t () {vint16mf4x7_t t;} +void f_vuint16mf4x7_t () {vuint16mf4x7_t t;} +void f_vint16mf4x8_t () {vint16mf4x8_t t;} +void f_vuint16mf4x8_t () {vuint16mf4x8_t t;} +void f_vint16mf2x2_t () {vint16mf2x2_t t;} +void f_vuint16mf2x2_t () {vuint16mf2x2_t t;} +void f_vint16mf2x3_t () {vint16mf2x3_t t;} +void f_vuint16mf2x3_t () {vuint16mf2x3_t t;} +void f_vint16mf2x4_t () {vint16mf2x4_t t;} +void f_vuint16mf2x4_t () {vuint16mf2x4_t t;} +void f_vint16mf2x5_t () {vint16mf2x5_t t;} +void f_vuint16mf2x5_t () {vuint16mf2x5_t t;} +void f_vint16mf2x6_t () {vint16mf2x6_t t;} +void f_vuint16mf2x6_t () {vuint16mf2x6_t t;} +void f_vint16mf2x7_t () {vint16mf2x7_t t;} +void f_vuint16mf2x7_t () {vuint16mf2x7_t t;} +void f_vint16mf2x8_t () {vint16mf2x8_t t;} +void f_vuint16mf2x8_t () {vuint16mf2x8_t t;} +void f_vint16m1x2_t () {vint16m1x2_t t;} +void f_vuint16m1x2_t () {vuint16m1x2_t t;} +void f_vint16m1x3_t () {vint16m1x3_t t;} +void f_vuint16m1x3_t () {vuint16m1x3_t t;} +void f_vint16m1x4_t () {vint16m1x4_t t;} +void f_vuint16m1x4_t () {vuint16m1x4_t t;} +void f_vint16m1x5_t () {vint16m1x5_t t;} +void f_vuint16m1x5_t () {vuint16m1x5_t t;} +void f_vint16m1x6_t () {vint16m1x6_t t;} +void f_vuint16m1x6_t () {vuint16m1x6_t t;} +void f_vint16m1x7_t () {vint16m1x7_t t;} +void f_vuint16m1x7_t () {vuint16m1x7_t t;} +void f_vint16m1x8_t () {vint16m1x8_t t;} +void f_vuint16m1x8_t () {vuint16m1x8_t t;} +void f_vint16m2x2_t () {vint16m2x2_t t;} +void f_vuint16m2x2_t () {vuint16m2x2_t t;} +void f_vint16m2x3_t () {vint16m2x3_t t;} +void f_vuint16m2x3_t () {vuint16m2x3_t t;} +void f_vint16m2x4_t () {vint16m2x4_t t;} +void f_vuint16m2x4_t () {vuint16m2x4_t t;} +void f_vint16m4x2_t () {vint16m4x2_t t;} +void f_vuint16m4x2_t () {vuint16m4x2_t t;} +void f_vint32mf2x2_t () {vint32mf2x2_t t;} +void f_vuint32mf2x2_t () {vuint32mf2x2_t t;} +void f_vint32mf2x3_t () {vint32mf2x3_t t;} +void f_vuint32mf2x3_t () {vuint32mf2x3_t t;} +void f_vint32mf2x4_t () {vint32mf2x4_t t;} +void f_vuint32mf2x4_t () {vuint32mf2x4_t t;} +void f_vint32mf2x5_t () {vint32mf2x5_t t;} +void f_vuint32mf2x5_t () {vuint32mf2x5_t t;} +void f_vint32mf2x6_t () {vint32mf2x6_t t;} +void f_vuint32mf2x6_t () {vuint32mf2x6_t t;} +void f_vint32mf2x7_t () {vint32mf2x7_t t;} +void f_vuint32mf2x7_t () {vuint32mf2x7_t t;} +void f_vint32mf2x8_t () {vint32mf2x8_t t;} +void f_vuint32mf2x8_t () {vuint32mf2x8_t t;} +void f_vint32m1x2_t () {vint32m1x2_t t;} +void f_vuint32m1x2_t () {vuint32m1x2_t t;} +void f_vint32m1x3_t () {vint32m1x3_t t;} +void f_vuint32m1x3_t () {vuint32m1x3_t t;} +void f_vint32m1x4_t () {vint32m1x4_t t;} +void f_vuint32m1x4_t () {vuint32m1x4_t t;} +void f_vint32m1x5_t () {vint32m1x5_t t;} +void f_vuint32m1x5_t () {vuint32m1x5_t t;} +void f_vint32m1x6_t () {vint32m1x6_t t;} +void f_vuint32m1x6_t () {vuint32m1x6_t t;} +void f_vint32m1x7_t () {vint32m1x7_t t;} +void f_vuint32m1x7_t () {vuint32m1x7_t t;} +void f_vint32m1x8_t () {vint32m1x8_t t;} +void f_vuint32m1x8_t () {vuint32m1x8_t t;} +void f_vint32m2x2_t () {vint32m2x2_t t;} +void f_vuint32m2x2_t () {vuint32m2x2_t t;} +void f_vint32m2x3_t () {vint32m2x3_t t;} +void f_vuint32m2x3_t () {vuint32m2x3_t t;} +void f_vint32m2x4_t () {vint32m2x4_t t;} +void f_vuint32m2x4_t () {vuint32m2x4_t t;} +void f_vint32m4x2_t () {vint32m4x2_t t;} +void f_vuint32m4x2_t () {vuint32m4x2_t t;} +void f_vint64m1x2_t () {vint64m1x2_t t;} +void f_vuint64m1x2_t () {vuint64m1x2_t t;} +void f_vint64m1x3_t () {vint64m1x3_t t;} +void f_vuint64m1x3_t () {vuint64m1x3_t t;} +void f_vint64m1x4_t () {vint64m1x4_t t;} +void f_vuint64m1x4_t () {vuint64m1x4_t t;} +void f_vint64m1x5_t () {vint64m1x5_t t;} +void f_vuint64m1x5_t () {vuint64m1x5_t t;} +void f_vint64m1x6_t () {vint64m1x6_t t;} +void f_vuint64m1x6_t () {vuint64m1x6_t t;} +void f_vint64m1x7_t () {vint64m1x7_t t;} +void f_vuint64m1x7_t () {vuint64m1x7_t t;} +void f_vint64m1x8_t () {vint64m1x8_t t;} +void f_vuint64m1x8_t () {vuint64m1x8_t t;} +void f_vint64m2x2_t () {vint64m2x2_t t;} +void f_vuint64m2x2_t () {vuint64m2x2_t t;} +void f_vint64m2x3_t () {vint64m2x3_t t;} +void f_vuint64m2x3_t () {vuint64m2x3_t t;} +void f_vint64m2x4_t () {vint64m2x4_t t;} +void f_vuint64m2x4_t () {vuint64m2x4_t t;} +void f_vint64m4x2_t () {vint64m4x2_t t;} +void f_vuint64m4x2_t () {vuint64m4x2_t t;} +void f_vfloat32mf2x2_t () {vfloat32mf2x2_t t;} /* { dg-error {unknown type name 'vfloat32mf2x2_t'} } */ +void f_vfloat32mf2x3_t () {vfloat32mf2x3_t t;} /* { dg-error {unknown type name 'vfloat32mf2x3_t'} } */ +void f_vfloat32mf2x4_t () {vfloat32mf2x4_t t;} /* { dg-error {unknown type name 'vfloat32mf2x4_t'} } */ +void f_vfloat32mf2x5_t () {vfloat32mf2x5_t t;} /* { dg-error {unknown type name 'vfloat32mf2x5_t'} } */ +void f_vfloat32mf2x6_t () {vfloat32mf2x6_t t;} /* { dg-error {unknown type name 'vfloat32mf2x6_t'} } */ +void f_vfloat32mf2x7_t () {vfloat32mf2x7_t t;} /* { dg-error {unknown type name 'vfloat32mf2x7_t'} } */ +void f_vfloat32mf2x8_t () {vfloat32mf2x8_t t;} /* { dg-error {unknown type name 'vfloat32mf2x8_t'} } */ +void f_vfloat32m1x2_t () {vfloat32m1x2_t t;} /* { dg-error {unknown type name 'vfloat32m1x2_t'} } */ +void f_vfloat32m1x3_t () {vfloat32m1x3_t t;} /* { dg-error {unknown type name 'vfloat32m1x3_t'} } */ +void f_vfloat32m1x4_t () {vfloat32m1x4_t t;} /* { dg-error {unknown type name 'vfloat32m1x4_t'} } */ +void f_vfloat32m1x5_t () {vfloat32m1x5_t t;} /* { dg-error {unknown type name 'vfloat32m1x5_t'} } */ +void f_vfloat32m1x6_t () {vfloat32m1x6_t t;} /* { dg-error {unknown type name 'vfloat32m1x6_t'} } */ +void f_vfloat32m1x7_t () {vfloat32m1x7_t t;} /* { dg-error {unknown type name 'vfloat32m1x7_t'} } */ +void f_vfloat32m1x8_t () {vfloat32m1x8_t t;} /* { dg-error {unknown type name 'vfloat32m1x8_t'} } */ +void f_vfloat32m2x2_t () {vfloat32m2x2_t t;} /* { dg-error {unknown type name 'vfloat32m2x2_t'} } */ +void f_vfloat32m2x3_t () {vfloat32m2x3_t t;} /* { dg-error {unknown type name 'vfloat32m2x3_t'} } */ +void f_vfloat32m2x4_t () {vfloat32m2x4_t t;} /* { dg-error {unknown type name 'vfloat32m2x4_t'} } */ +void f_vfloat32m4x2_t () {vfloat32m4x2_t t;} /* { dg-error {unknown type name 'vfloat32m4x2_t'} } */ +void f_vfloat64m1x2_t () {vfloat64m1x2_t t;} /* { dg-error {unknown type name 'vfloat64m1x2_t'} } */ +void f_vfloat64m1x3_t () {vfloat64m1x3_t t;} /* { dg-error {unknown type name 'vfloat64m1x3_t'} } */ +void f_vfloat64m1x4_t () {vfloat64m1x4_t t;} /* { dg-error {unknown type name 'vfloat64m1x4_t'} } */ +void f_vfloat64m1x5_t () {vfloat64m1x5_t t;} /* { dg-error {unknown type name 'vfloat64m1x5_t'} } */ +void f_vfloat64m1x6_t () {vfloat64m1x6_t t;} /* { dg-error {unknown type name 'vfloat64m1x6_t'} } */ +void f_vfloat64m1x7_t () {vfloat64m1x7_t t;} /* { dg-error {unknown type name 'vfloat64m1x7_t'} } */ +void f_vfloat64m1x8_t () {vfloat64m1x8_t t;} /* { dg-error {unknown type name 'vfloat64m1x8_t'} } */ +void f_vfloat64m2x2_t () {vfloat64m2x2_t t;} /* { dg-error {unknown type name 'vfloat64m2x2_t'} } */ +void f_vfloat64m2x3_t () {vfloat64m2x3_t t;} /* { dg-error {unknown type name 'vfloat64m2x3_t'} } */ +void f_vfloat64m2x4_t () {vfloat64m2x4_t t;} /* { dg-error {unknown type name 'vfloat64m2x4_t'} } */ +void f_vfloat64m4x2_t () {vfloat64m4x2_t t;} /* { dg-error {unknown type name 'vfloat64m4x2_t'} } */ -- 2.36.1