From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112b.google.com (mail-yw1-x112b.google.com [IPv6:2607:f8b0:4864:20::112b]) by sourceware.org (Postfix) with ESMTPS id D40A63858C2D for ; Mon, 17 Apr 2023 18:37:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D40A63858C2D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-yw1-x112b.google.com with SMTP id 00721157ae682-54fc337a650so176550527b3.4 for ; Mon, 17 Apr 2023 11:37:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681756623; x=1684348623; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TnFyMkovn1MwpJF5gBhM1rzNKKR2Jo31TJ2blUebek8=; b=nEoUq14KAS9pYU9ItdjkqB262o4JaoK2LQSbiskOT9JqInioRO0fS/6e4mNPBP9d1i vBjhr2uR0Vc28vccqW9giOwX8rObok6G7uSeX1kTH/ZBHUgleWlyQ631XB7eDou/sQEi ot0GlJxDNFOKU/b3Isq3FUWhDxAls2Ls2Azy93oxSLdhLbs7Wy7GF2PWXxVyMZgv+bRH PTeNlyQO3p/TgByK4Rx2aygsxrVhGe+I0rfDckOjT9EFQ9TdNIFTJ8Yvz6RlUAQWZ0ZI Tu6JldCBHFv1eD1yamH3gpJEJOYmvD+/GYx2VlnuSM2ghyPHzdNbKogUuH8flz5PDrRq 0ZVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681756623; x=1684348623; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TnFyMkovn1MwpJF5gBhM1rzNKKR2Jo31TJ2blUebek8=; b=OyeuLh00ktC/BtLZb8eXza2yTwshpHiglDKJUHCr931XGQ2DAP3yoxUsAkR1c4hHFi 0lXcdykPhys0ShWbtK/ztx3GAGUO2jIRRseHI22rhIgU/NEXW8I/1YM1uPIx1qsCD5Bw 2PVy2iCvgUhM9fUr3jBoBMw0Zk1MR7Mw/KbGhQKA1lMbUi5PtMYCmmKTG5FbvWOYDQep WtU/pbf6d9Kl2e8XfRvrqlrsyNWaxkCj2OFICbmr1SDLfxtLVVqaCvlcL6WrR0vFaoWd s7RtSrwpcwnEsLzFLXaZtHeZmXvLbroVOZlyN1UGG29NfWswMIC9lrd5KU/J4Z2Fc2ZS 1iGA== X-Gm-Message-State: AAQBX9c/+2lhDkwK1u4w4mugdbczn7vqOe8268a9Vr+Q7+alFfodRnR9 tbJkJ60I1L48HrMivn8Wka1aUWKZhk+sgsOZThQi2Q== X-Google-Smtp-Source: AKy350YwfKc6BVTp62AWg18StZ6IucXmfPB7qCW9HAw5AWiA/NlVS82lnL7pEpbMiKcwQd7V1sedxQ== X-Received: by 2002:a0d:eb04:0:b0:54f:6a20:5a19 with SMTP id u4-20020a0deb04000000b0054f6a205a19mr15452380ywe.34.1681756623069; Mon, 17 Apr 2023 11:37:03 -0700 (PDT) Received: from system76-pc.ba.rivosinc.com ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id 66-20020a810645000000b0054f6f65f258sm3278559ywg.16.2023.04.17.11.37.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 11:37:02 -0700 (PDT) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v4 01/10] RISC-V: Add new predicates and function prototypes Date: Mon, 17 Apr 2023 14:36:52 -0400 Message-Id: <20230417183701.2249183-2-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417183701.2249183-1-collison@rivosinc.com> References: <20230417183701.2249183-1-collison@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: 2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-protos.h (riscv_classify_vlmul_field): New external declaration. (riscv_vector_preferred_simd_mode): Ditto. (riscv_tuple_mode_p): Ditto. (riscv_vector_mask_mode_p): Ditto. (riscv_classify_nf): Ditto. (riscv_vlmul_regsize): Ditto. (riscv_vector_preferred_simd_mode): Ditto. (riscv_vector_get_mask_mode): Ditto. (emit_vlmax_vsetvl): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. * config/riscv/riscv-opts.h (riscv_vector_bits_enum): New enum. (riscv_vector_lmul_enum): Ditto. (vlmul_field_enum): Ditto. * config/riscv/riscv-v.cc (emit_vlmax_vsetvl): Remove static scope. * config/riscv/riscv.opt (riscv_vector_lmul): New option -mriscv_vector_lmul. * config/riscv/predicates.md (p_reg_or_const_csr_operand): New predicate. (vector_reg_or_const_dup_operand): Ditto. --- gcc/config/riscv/predicates.md | 13 +++++++++++ gcc/config/riscv/riscv-opts.h | 40 +++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv-protos.h | 14 ++++++++++++ gcc/config/riscv/riscv.opt | 20 +++++++++++++++++ 4 files changed, 87 insertions(+) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 8654dbc5943..b3f2d622c7b 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -264,6 +264,14 @@ }) ;; Predicates for the V extension. +(define_special_predicate "p_reg_or_const_csr_operand" + (match_code "reg, subreg, const_int") +{ + if (CONST_INT_P (op)) + return satisfies_constraint_K (op); + return GET_MODE (op) == Pmode; +}) + (define_special_predicate "vector_length_operand" (ior (match_operand 0 "pmode_register_operand") (match_operand 0 "const_csr_operand"))) @@ -291,6 +299,11 @@ (and (match_code "const_vector") (match_test "rtx_equal_p (op, riscv_vector::gen_scalar_move_mask (GET_MODE (op)))"))) +(define_predicate "vector_reg_or_const_dup_operand" + (ior (match_operand 0 "register_operand") + (match_test "const_vec_duplicate_p (op) + && !CONST_POLY_INT_P (CONST_VECTOR_ELT (op, 0))"))) + (define_predicate "vector_mask_operand" (ior (match_operand 0 "register_operand") (match_operand 0 "vector_all_trues_mask_operand"))) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index cf0cd669be4..70711310749 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -67,6 +67,46 @@ enum stack_protector_guard { SSP_GLOBAL /* global canary */ }; +/* RVV vector register sizes. */ +enum riscv_vector_bits_enum +{ + RVV_SCALABLE, + RVV_NOT_IMPLEMENTED = RVV_SCALABLE, + RVV_64 = 64, + RVV_128 = 128, + RVV_256 = 256, + RVV_512 = 512, + RVV_1024 = 1024, + RVV_2048 = 2048, + RVV_4096 = 4096, + RVV_8192 = 8192, + RVV_16384 = 16384, + RVV_32768 = 32768, + RVV_65536 = 65536 +}; + +/* vectorization factor. */ +enum riscv_vector_lmul_enum +{ + RVV_LMUL1 = 1, + RVV_LMUL2 = 2, + RVV_LMUL4 = 4, + RVV_LMUL8 = 8 +}; + +enum vlmul_field_enum +{ + VLMUL_FIELD_000, /* LMUL = 1. */ + VLMUL_FIELD_001, /* LMUL = 2. */ + VLMUL_FIELD_010, /* LMUL = 4. */ + VLMUL_FIELD_011, /* LMUL = 8. */ + VLMUL_FIELD_100, /* RESERVED. */ + VLMUL_FIELD_101, /* LMUL = 1/8. */ + VLMUL_FIELD_110, /* LMUL = 1/4. */ + VLMUL_FIELD_111, /* LMUL = 1/2. */ + MAX_VLMUL_FIELD +}; + #define MASK_ZICSR (1 << 0) #define MASK_ZIFENCEI (1 << 1) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 5244e8dcbf0..41f60f82a55 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -237,4 +237,18 @@ extern const char* th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); #endif +/* Routines implemented in riscv-v.cc. */ + +namespace riscv_vector { +extern unsigned int riscv_classify_vlmul_field (enum machine_mode m); +extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode, + unsigned vf); +extern bool riscv_tuple_mode_p (machine_mode); +extern bool riscv_vector_mask_mode_p (machine_mode); +extern int riscv_classify_nf (machine_mode); +extern int riscv_vlmul_regsize (machine_mode); +extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode); +extern rtx get_mask_policy_no_pred (); +extern rtx get_tail_policy_no_pred (); +} #endif /* ! GCC_RISCV_PROTOS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index ff1dd4ddd4f..4db3b2cac55 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -70,6 +70,26 @@ Enum(abi_type) String(lp64f) Value(ABI_LP64F) EnumValue Enum(abi_type) String(lp64d) Value(ABI_LP64D) +Enum +Name(riscv_vector_lmul) Type(enum riscv_vector_lmul_enum) +The possible vectorization factor: + +EnumValue +Enum(riscv_vector_lmul) String(1) Value(RVV_LMUL1) + +EnumValue +Enum(riscv_vector_lmul) String(2) Value(RVV_LMUL2) + +EnumValue +Enum(riscv_vector_lmul) String(4) Value(RVV_LMUL4) + +EnumValue +Enum(riscv_vector_lmul) String(8) Value(RVV_LMUL8) + +mriscv-vector-lmul= +Target RejectNegative Joined Enum(riscv_vector_lmul) Var(riscv_vector_lmul) Init(RVV_LMUL1) +-mriscv-vector-lmul= Set the vf using lmul in auto-vectorization. + mfdiv Target Mask(FDIV) Use hardware floating-point divide and square root instructions. -- 2.34.1