From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x1134.google.com (mail-yw1-x1134.google.com [IPv6:2607:f8b0:4864:20::1134]) by sourceware.org (Postfix) with ESMTPS id F17893858C3A for ; Mon, 17 Apr 2023 18:37:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F17893858C3A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-yw1-x1134.google.com with SMTP id 00721157ae682-552fb3c2bb7so19595497b3.10 for ; Mon, 17 Apr 2023 11:37:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681756624; x=1684348624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=EP+KbKdXGecqWIGIE2TLDrxuAoh/r9kHm5XI3rL4bU0=; b=Py3XPdxT6jmRp2GW5KockzSV9cc71Ryr2imBm8FOkQ6vXMI9hALIkZhkFTZj6zAHfE Gg4De9KE+VNThwQmn5MiWzW0h2JWcNup3r4Yg4Eb9kIMQUwpDIPrAtRWETIwZJsQSbMR yGrdiRDPP3t0UhDUML+Qw4FAkNjFdFeB7Y/PebQkKHPAOu3L32gvulVpBQH/Cq3qtEOS McRMx7yGWAFo4uIERIa5LkkDFAZAoIgOiMKl0zjnPM7o5Q+wVZMyXzXzlH+o0LAavP0/ doMNiGmDhQoqZKx4xmshixe7Or2q4kY5U4JMagkAjPahkRYqvXM/3AUD98dnxKGpFYAZ c0FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681756624; x=1684348624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EP+KbKdXGecqWIGIE2TLDrxuAoh/r9kHm5XI3rL4bU0=; b=Cdm68Dboib5WzQNalmI4MTCigfJeVlR3GQ2NqKhTxkdo3QVh1arb/+Vao1YntuPyO9 aC+tbO2hXHU8w2aiLi5f4B+xwsb+5TBhRP77n9hgNB94LkxgsdnBWFRLnN4Vp4HeNprj 2ryhoz/6U5dxp+ywkmUIZyAUgPdRffQrlvnrDPLpx+p7JEUnHIliN6jOtULKMxRDmf99 85CfHGpQzLw4ltefiBlidBVbPc3rVvBcFSXBdRLimBdp6wC2Io9oaMmySn6wtg1X0Uzu 8E8ECp6evchSGiQWyDpdHj8mHV4qCBMCq1GE0jS2pRlREoEEIGJN9B+LK+8cxWCbYwRk fbcA== X-Gm-Message-State: AAQBX9ckSWf+mw/LfupQ97dcgMhPpF8hMYfRztbMMawvnRpVIor3z3Hr ir3Kv2JEYPvdNO4WJUkBEX5d6DtREimd7Cj0BBh8Mw== X-Google-Smtp-Source: AKy350a4PCz0tilFjVgeItsX2x5NPWP503xd3EferPhQ7wp/XtBqfjr7YYG0gAYZV3MrTFdYkFHdsw== X-Received: by 2002:a0d:ca02:0:b0:54f:ae60:867e with SMTP id m2-20020a0dca02000000b0054fae60867emr16862024ywd.7.1681756624201; Mon, 17 Apr 2023 11:37:04 -0700 (PDT) Received: from system76-pc.ba.rivosinc.com ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id 66-20020a810645000000b0054f6f65f258sm3278559ywg.16.2023.04.17.11.37.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 11:37:03 -0700 (PDT) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v4 03/10] RISC-V:autovec: Add auto-vectorization support functions Date: Mon, 17 Apr 2023 14:36:54 -0400 Message-Id: <20230417183701.2249183-4-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417183701.2249183-1-collison@rivosinc.com> References: <20230417183701.2249183-1-collison@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: 2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-v.cc (riscv_classify_vlmul_field): New function. (riscv_vector_preferred_simd_mode): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. (riscv_tuple_mode_p): Ditto. (riscv_classify_nf): Ditto. (riscv_vlmul_regsize): Ditto. (riscv_vector_mask_mode_p): Ditto. (riscv_vector_get_mask_mode): Ditto. --- gcc/config/riscv/riscv-v.cc | 176 ++++++++++++++++++++++++++++++++++++ 1 file changed, 176 insertions(+) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 392f5d02e17..9df86419caa 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -39,9 +39,11 @@ #include "emit-rtl.h" #include "tm_p.h" #include "target.h" +#include "targhooks.h" #include "expr.h" #include "optabs.h" #include "tm-constrs.h" +#include "riscv-vector-builtins.h" #include "rtx-vector-builder.h" using namespace riscv_vector; @@ -118,6 +120,41 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval, && IN_RANGE (INTVAL (elt), minval, maxval)); } +/* Return the vlmul field for a specific machine mode. */ +unsigned int +riscv_classify_vlmul_field (enum machine_mode mode) +{ + /* Make the decision based on the mode's enum value rather than its + properties, so that we keep the correct classification regardless + of -mriscv-vector-bits. */ + switch (mode) + { + case E_VNx8BImode: + return VLMUL_FIELD_111; + + case E_VNx4BImode: + return VLMUL_FIELD_110; + + case E_VNx2BImode: + return VLMUL_FIELD_101; + + case E_VNx16BImode: + return VLMUL_FIELD_000; + + case E_VNx32BImode: + return VLMUL_FIELD_001; + + case E_VNx64BImode: + return VLMUL_FIELD_010; + + default: + break; + } + + /* we don't care about VLMUL for Mask. */ + return VLMUL_FIELD_000; +} + /* Emit a vlmax vsetvl instruction. This should only be used when optimization is disabled or after vsetvl insertion pass. */ void @@ -176,6 +213,64 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul) return ratio; } +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV. */ + +machine_mode +riscv_vector_preferred_simd_mode (scalar_mode mode, unsigned vf) +{ + if (!TARGET_VECTOR) + return word_mode; + + switch (mode) + { + case E_QImode: + return vf == 1 ? VNx8QImode + : vf == 2 ? VNx16QImode + : vf == 4 ? VNx32QImode + : VNx64QImode; + break; + case E_HImode: + return vf == 1 ? VNx4HImode + : vf == 2 ? VNx8HImode + : vf == 4 ? VNx16HImode + : VNx32HImode; + break; + case E_SImode: + return vf == 1 ? VNx2SImode + : vf == 2 ? VNx4SImode + : vf == 4 ? VNx8SImode + : VNx16SImode; + break; + case E_DImode: + if (riscv_vector_elen_flags != MASK_VECTOR_ELEN_32 + && riscv_vector_elen_flags != MASK_VECTOR_ELEN_FP_32) + return vf == 1 ? VNx1DImode + : vf == 2 ? VNx2DImode + : vf == 4 ? VNx4DImode + : VNx8DImode; + break; + case E_SFmode: + if (TARGET_HARD_FLOAT && riscv_vector_elen_flags != MASK_VECTOR_ELEN_32 + && riscv_vector_elen_flags != MASK_VECTOR_ELEN_64) + return vf == 1 ? VNx2SFmode + : vf == 2 ? VNx4SFmode + : vf == 4 ? VNx8SFmode + : VNx16SFmode; + break; + case E_DFmode: + if (TARGET_DOUBLE_FLOAT && TARGET_VECTOR_ELEN_FP_64) + return vf == 1 ? VNx1DFmode + : vf == 2 ? VNx2DFmode + : vf == 4 ? VNx4DFmode + : VNx8DFmode; + break; + default: + break; + } + + return word_mode; +} + /* Emit an RVV unmask && vl mov from SRC to DEST. */ static void emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len, @@ -421,6 +516,87 @@ get_avl_type_rtx (enum avl_type type) return gen_int_mode (type, Pmode); } +rtx +get_mask_policy_no_pred () +{ + return get_mask_policy_for_pred (PRED_TYPE_none); +} + +rtx +get_tail_policy_no_pred () +{ + return get_mask_policy_for_pred (PRED_TYPE_none); +} + +/* Return true if it is a RVV tuple mode. */ +bool +riscv_tuple_mode_p (machine_mode mode ATTRIBUTE_UNUSED) +{ + return false; +} + +/* Return nf for a machine mode. */ +int +riscv_classify_nf (machine_mode mode) +{ + switch (mode) + { + + default: + break; + } + + return 1; +} + +/* Return vlmul register size for a machine mode. */ +int +riscv_vlmul_regsize (machine_mode mode) +{ + if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) + return 1; + switch (riscv_classify_vlmul_field (mode)) + { + case VLMUL_FIELD_001: + return 2; + case VLMUL_FIELD_010: + return 4; + case VLMUL_FIELD_011: + return 8; + case VLMUL_FIELD_100: + gcc_unreachable (); + default: + return 1; + } +} + +/* Return true if it is a RVV mask mode. */ +bool +riscv_vector_mask_mode_p (machine_mode mode) +{ + return (mode == VNx1BImode || mode == VNx2BImode || mode == VNx4BImode + || mode == VNx8BImode || mode == VNx16BImode || mode == VNx32BImode + || mode == VNx64BImode); +} + +/* Implement TARGET_VECTORIZE_GET_MASK_MODE for RVV. */ + +opt_machine_mode +riscv_vector_get_mask_mode (machine_mode mode) +{ + machine_mode mask_mode; + int nf = 1; + if (riscv_tuple_mode_p (mode)) + nf = riscv_classify_nf (mode); + + FOR_EACH_MODE_IN_CLASS (mask_mode, MODE_VECTOR_BOOL) + if (GET_MODE_INNER (mask_mode) == BImode + && known_eq (GET_MODE_NUNITS (mask_mode) * nf, GET_MODE_NUNITS (mode)) + && riscv_vector_mask_mode_p (mask_mode)) + return mask_mode; + return default_get_mask_mode (mode); +} + /* Return the RVV vector mode that has NUNITS elements of mode INNER_MODE. This function is not only used by builtins, but also will be used by auto-vectorization in the future. */ -- 2.34.1