From: juzhe.zhong@rivai.ai
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com,
Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Subject: [PATCH] RISC-V: Fix bug reported by PR109535
Date: Wed, 19 Apr 2023 07:25:15 +0800 [thread overview]
Message-ID: <20230418232515.95891-1-juzhe.zhong@rivai.ai> (raw)
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Fix bug reported by google/highway who is using rvv intrinsic:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109535
PR 109535
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (count_regno_occurrences): New function.
(pass_vsetvl::cleanup_insns): Fix bug.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr109535.c: New test.
---
gcc/config/riscv/riscv-vsetvl.cc | 15 ++++++++++++++-
.../gcc.target/riscv/rvv/base/pr109535.c | 11 +++++++++++
2 files changed, 25 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr109535.c
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 1b66e3b9eeb..b570b003a1e 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1592,6 +1592,19 @@ backward_propagate_worthwhile_p (const basic_block cfg_bb,
return true;
}
+/* Count the number of REGNO in RINSN. */
+static int
+count_regno_occurrences (rtx_insn *rinsn, unsigned int regno)
+{
+ int count = 0;
+ extract_insn (rinsn);
+ for (int i = 0; i < recog_data.n_operands; i++)
+ if (REG_P (recog_data.operand[i])
+ && REGNO (recog_data.operand[i]) == regno)
+ count++;
+ return count;
+}
+
avl_info::avl_info (const avl_info &other)
{
m_value = other.get_value ();
@@ -3924,7 +3937,7 @@ pass_vsetvl::cleanup_insns (void) const
if (!has_vl_op (rinsn) || !REG_P (get_vl (rinsn)))
continue;
rtx avl = get_vl (rinsn);
- if (count_occurrences (PATTERN (rinsn), avl, 0) == 1)
+ if (count_regno_occurrences (rinsn, REGNO (avl)) == 1)
{
/* Get the list of uses for the new instruction. */
auto attempt = crtl->ssa->new_change_attempt ();
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr109535.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr109535.c
new file mode 100644
index 00000000000..7582fe9c392
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr109535.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
+
+#include "riscv_vector.h"
+
+void foo(void *in1, void *in2, void *in3, void *out, size_t vl) {
+ vint8m1_t a = __riscv_vle8_v_i8m1(in1, vl);
+ vint8m1_t b = __riscv_vadd_vx_i8m1 (a, vl, vl);
+ __riscv_vse8_v_i8m1(out, b, vl);
+}
+
--
2.36.1
next reply other threads:[~2023-04-18 23:25 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-18 23:25 juzhe.zhong [this message]
2023-04-19 0:18 ` Kito Cheng
2023-04-19 0:56 ` Jeff Law
2023-04-19 1:04 ` juzhe.zhong
2023-04-19 1:11 ` Jeff Law
2023-04-19 1:29 ` juzhe.zhong
2023-04-19 5:43 ` Jeff Law
2023-04-19 10:45 ` juzhe.zhong
2023-04-19 1:34 ` juzhe.zhong
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