From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id 742A33858D1E for ; Wed, 19 Apr 2023 09:18:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 742A33858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681895918; x=1713431918; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/ridiQagdSeqNuJd1+HJNgDvSAcLsbunUwcUh87EahU=; b=ecHM2ivtn5o0rtCZmD9jQxcNEN3pOfnxonY8yJXhF/GYbeJQmiVP87Zx 5ERbAn2oIyA5dtr8xZe90gNUx4xoKHkECC0/yx+u93ZxybDNxRU7Zcg8M 7pwPxJixfUH5J6AbX7VvokACoWq4lZvh8yHC8Oq3K57H6CLrdhmqwZGHX Qy5YyS9ABPrrhDgOdiRaIDViQ3EXRuH7hcU7Plk23Ogj5jFBizs94B2vs Qzym5zLyqHPz5pi+PvxPfoSUxqmOfM4SubFQPPx0Iy4u60XZpmut5jmev bXXzCJPPVwRs5XpQUHQwfuRusMJ7nZ4GNAqBDtfFNgbU03asmdaXpPVVT g==; X-IronPort-AV: E=McAfee;i="6600,9927,10684"; a="329573954" X-IronPort-AV: E=Sophos;i="5.99,208,1677571200"; d="scan'208";a="329573954" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2023 02:18:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10684"; a="1021127592" X-IronPort-AV: E=Sophos;i="5.99,208,1677571200"; d="scan'208";a="1021127592" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga005.fm.intel.com with ESMTP; 19 Apr 2023 02:18:23 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.46.88]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 775D210080D4; Wed, 19 Apr 2023 17:18:22 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, rguenther@suse.de, pan2.li@intel.com, richard.sandiford@arm.com, yanzhang.wang@intel.com Subject: [PATCH v3] RISC-V: Align IOR optimization MODE_CLASS condition to AND. Date: Wed, 19 Apr 2023 17:18:20 +0800 Message-Id: <20230419091820.3729443-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417145025.2291874-1-pan2.li@intel.com> References: <20230417145025.2291874-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch aligned the MODE_CLASS condition of the IOR to the AND. Then more MODE_CLASS besides SCALAR_INT can able to perform the optimization A | (~A) -> -1 similar to AND operator. For example as below sample code. vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t vl) { return __riscv_vmorn_mm_b32(v1, v1, vl); } Before this patch: vsetvli a5,zero,e8,mf4,ta,ma vlm.v v24,0(a1) vsetvli zero,a2,e8,mf4,ta,ma vmorn.mm v24,v24,v24 vsetvli a5,zero,e8,mf4,ta,ma vsm.v v24,0(a0) ret After this patch: vsetvli zero,a2,e8,mf4,ta,ma vmset.m v24 vsetvli a5,zero,e8,mf4,ta,ma vsm.v v24,0(a0) ret Or in RTL's perspective, from: (ior:VNx2BI (reg/v:VNx2BI 137 [ v1 ]) (not:VNx2BI (reg/v:VNx2BI 137 [ v1 ]))) to: (const_vector:VNx2BI repeat [ (const_int 1 [0x1]) ]) The similar optimization like VMANDN has enabled already. There should be no difference execpt the operator when compare the VMORN and VMANDN for such kind of optimization. The patch aligns the IOR MODE_CLASS condition of the simplification to the AND operator. gcc/ChangeLog: * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): Align IOR (A | (~A) -> -1) optimization MODE_CLASS condition to AND. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Update check condition. * gcc.target/riscv/simplify_ior_optimization.c: New test. Signed-off-by: Pan Li --- gcc/simplify-rtx.cc | 4 +- .../riscv/rvv/base/mask_insn_shortcut.c | 3 +- .../riscv/simplify_ior_optimization.c | 50 +++++++++++++++++++ 3 files changed, 53 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index c57ff3320ee..d4aeebc7a5f 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -3370,8 +3370,8 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1)) || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0))) && ! side_effects_p (op0) - && SCALAR_INT_MODE_P (mode)) - return constm1_rtx; + && GET_MODE_CLASS (mode) != MODE_CC) + return CONSTM1_RTX (mode); /* (ior A C) is C if all bits of A that might be nonzero are on in C. */ if (CONST_INT_P (op1) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c index 83cc4a1b5a5..57d0241675a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c @@ -233,9 +233,8 @@ vbool64_t test_shortcut_for_riscv_vmxnor_case_6(vbool64_t v1, size_t vl) { /* { dg-final { scan-assembler-not {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ /* { dg-final { scan-assembler-not {vmor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ /* { dg-final { scan-assembler-not {vmnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ -/* { dg-final { scan-assembler-times {vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */ /* { dg-final { scan-assembler-not {vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ /* { dg-final { scan-assembler-times {vmclr\.m\s+v[0-9]+} 14 } } */ -/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 7 } } */ +/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 14 } } */ /* { dg-final { scan-assembler-times {vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 14 } } */ /* { dg-final { scan-assembler-times {vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c new file mode 100644 index 00000000000..ec3bd0baf03 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */ + +#include + +uint8_t test_simplify_ior_scalar_case_0 (uint8_t a) +{ + return a | ~a; +} + +uint16_t test_simplify_ior_scalar_case_1 (uint16_t a) +{ + return a | ~a; +} + +uint32_t test_simplify_ior_scalar_case_2 (uint32_t a) +{ + return a | ~a; +} + +uint64_t test_simplify_ior_scalar_case_3 (uint64_t a) +{ + return a | ~a; +} + +int8_t test_simplify_ior_scalar_case_4 (int8_t a) +{ + return a | ~a; +} + +int16_t test_simplify_ior_scalar_case_5 (int16_t a) +{ + return a | ~a; +} + +int32_t test_simplify_ior_scalar_case_6 (int32_t a) +{ + return a | ~a; +} + +int64_t test_simplify_ior_scalar_case_7 (int64_t a) +{ + return a | ~a; +} + +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*-1} 6 } } */ +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*255} 1 } } */ +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*65536} 1 } } */ +/* { dg-final { scan-assembler-not {or\s+a[0-9]+} } } */ +/* { dg-final { scan-assembler-not {not\s+a[0-9]+} } } */ -- 2.34.1