From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id 73F02385701A for ; Wed, 26 Apr 2023 12:00:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 73F02385701A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682510413; x=1714046413; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=4vrWBs3UOByYnyEHJ0ZK36TlfNo2oFyc91DSGsUHJxA=; b=hTkppVlOzAiQMS00+Y/66tJfOTE6AZj01H3RzQBLiP92a4rS5HxInZgm Pa4y4kQRFc1UQkbjt6U/SULPwZlNGPel/bWfrB8D9kqZSa1UDcx1wcAli AXw0pPkalEPePxQ7rkH5hKPYOrt6wlatjuHEO5kjyQtf7mMu42ZIpZcqt 6sMXN1HEXxrg5d15tQRF1lEsWE7xJTWKXd1gHgVCe2FRdX3fe0J01yxbm 4XWGSW/jpXurB5FIwFUeVIeesw0BdQ5FYPU54y3E5Sa8+gsNoWZZr+oAN agp2RzL3KmY3ACWDuDiZ248cIN5XF16r65I0SypSnGhJFtEGv51f26hOJ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="375037781" X-IronPort-AV: E=Sophos;i="5.99,228,1677571200"; d="scan'208";a="375037781" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 05:00:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="644221185" X-IronPort-AV: E=Sophos;i="5.99,228,1677571200"; d="scan'208";a="644221185" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga003.jf.intel.com with ESMTP; 26 Apr 2023 05:00:09 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id DF5291005676; Wed, 26 Apr 2023 20:00:08 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, yanzhang.wang@intel.com, Pan Li Subject: [PATCH] RISC-V: Legitimise the const0_rtx for RVV load/store address Date: Wed, 26 Apr 2023 20:00:06 +0800 Message-Id: <20230426120006.2362465-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch try to legitimise the const0_rtx (aka zero register) as the base register for the RVV load/store instructions. For example: vint32m1_t test_vle32_v_i32m1_shortcut (size_t vl) { return __riscv_vle32_v_i32m1 ((int32_t *)0, vl); } Before this patch: li a5,0 vsetvli zero,a1,e32,m1,ta,ma vle32.v v24,0(a5) <- can propagate the const 0 to a5 here vs1r.v v24,0(a0) After this patch: vsetvli zero,a1,e32,m1,ta,ma vle32.v v24,0(zero) vs1r.v v24,0(a0) As above, this patch allow you to propagaate the const 0 (aka zero register) to the base register of the RVV Unit-Stride load in the combine pass. This may benefit the underlying RVV auto-vectorization. However, the indexed load failed to perform the optimization and it will be token care of in another PATCH. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_classify_address): Allow const0_rtx for the RVV load/store. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: New test. Signed-off-by: Pan Li Co-authored-by: Ju-Zhe Zhong --- gcc/config/riscv/riscv.cc | 17 ++- .../base/zero_base_load_store_optimization.c | 135 ++++++++++++++++++ 2 files changed, 150 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index ac8e4420896..a2d2dd0bb67 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1088,9 +1088,22 @@ riscv_classify_address (struct riscv_address_info *info, rtx x, && riscv_valid_lo_sum_p (info->symbol_type, mode, info->offset)); case CONST_INT: - /* RVV load/store disallow CONST_INT. */ + /* We only allow the const0_rtx for the RVV load/store. For example: + +----------------------------------------------------------+ + | li a5,0 | + | vsetvli zero,a1,e32,m1,ta,ma | + | vle32.v v24,0(a5) <- propagate the const 0 to a5 here. | + | vs1r.v v24,0(a0) | + +----------------------------------------------------------+ + It can be folded to: + +----------------------------------------------------------+ + | vsetvli zero,a1,e32,m1,ta,ma | + | vle32.v v24,0(zero) | + | vs1r.v v24,0(a0) | + +----------------------------------------------------------+ + This behavior will benefit the underlying RVV auto vectorization. */ if (riscv_v_ext_vector_mode_p (mode)) - return false; + return x == const0_rtx; /* Small-integer addresses don't occur very often, but they are legitimate if x0 is a valid base register. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c new file mode 100644 index 00000000000..4b30d3505c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c @@ -0,0 +1,135 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */ + +// #include +#include "riscv_vector.h" + +#define float32_t float + +// Unit-Stride Load/Store +vint32m1_t test_vle32_v_i32m1_shortcut (size_t vl) +{ + return __riscv_vle32_v_i32m1 ((int32_t *)0, vl); +} + +vuint32m1_t test_vle32_v_u32m1_shortcut (size_t vl) +{ + return __riscv_vle32_v_u32m1 ((int32_t *)0, vl); +} + +vfloat32m1_t test_vle32_v_f32m1_shortcut (size_t vl) +{ + return __riscv_vle32_v_f32m1 ((float32_t *)0, vl); +} + +void test_vse32_v_i32m1_shortcut (vint32m1_t val, size_t vl) +{ + __riscv_vse32_v_i32m1 ((int32_t *)0, val, vl); +} + +void test_vse32_v_u32m1_shortcut (vuint32m1_t val, size_t vl) +{ + __riscv_vse32_v_u32m1 ((uint32_t *)0, val, vl); +} + +void test_vse32_v_f32m1_shortcut (vfloat32m1_t val, size_t vl) +{ + __riscv_vse32_v_f32m1 ((float32_t *)0, val, vl); +} + +// Stride Load/Store +vint32m1_t test_vlse32_v_i32m1_shortcut (ptrdiff_t bstride, size_t vl) +{ + return __riscv_vlse32_v_i32m1 ((int32_t *)0, bstride, vl); +} + +vuint32m1_t test_vlse32_v_u32m1_shortcut (ptrdiff_t bstride, size_t vl) +{ + return __riscv_vlse32_v_u32m1 ((uint32_t *)0, bstride, vl); +} + +vfloat32m1_t test_vlse32_v_f32m1_shortcut (ptrdiff_t bstride, size_t vl) +{ + return __riscv_vlse32_v_f32m1 ((float32_t *)0, bstride, vl); +} + +void test_vsse32_v_i32m1_shortcut (ptrdiff_t bstride, vint32m1_t val, size_t vl) +{ + __riscv_vsse32_v_i32m1 ((int32_t *)0, bstride, val, vl); +} + +void test_vsse32_v_u32m1_shortcut (ptrdiff_t bstride, vuint32m1_t val, size_t vl) +{ + __riscv_vsse32_v_u32m1 ((uint32_t *)0, bstride, val, vl); +} + +void test_vsse32_v_f32m1_shortcut (ptrdiff_t bstride, vfloat32m1_t val,size_t vl) +{ + __riscv_vsse32_v_f32m1 ((float32_t *)0, bstride, val, vl); +} + +// Indexed-Unordered Load/Store +vint32m1_t test_vluxei32_v_i32m1_shortcut (vuint32m1_t bindex, size_t vl) +{ + return __riscv_vluxei32_v_i32m1 ((int32_t *)0, bindex, vl); +} + +vuint32m1_t test_vluxei32_v_u32m1_shortcut (vuint32m1_t bindex, size_t vl) +{ + return __riscv_vluxei32_v_u32m1 ((uint32_t *)0, bindex, vl); +} + +vfloat32m1_t test_vluxei32_v_f32m1_shortcut (vuint32m1_t bindex, size_t vl) +{ + return __riscv_vluxei32_v_f32m1 ((float32_t *)0, bindex, vl); +} + +void test_vsuxei32_v_i32m1_shortcut (vuint32m1_t bindex, vint32m1_t val, size_t vl) +{ + __riscv_vsuxei32_v_i32m1 ((int32_t *)0, bindex, val, vl); +} + +void test_vsuxei32_v_u32m1_shortcut (vuint32m1_t bindex, vuint32m1_t val, size_t vl) +{ + __riscv_vsuxei32_v_u32m1 ((uint32_t *)0, bindex, val, vl); +} + +void test_vsuxei32_v_f32m1_shortcut (vuint32m1_t bindex, vfloat32m1_t val, size_t vl) +{ + __riscv_vsuxei32_v_f32m1 ((float32_t *)0, bindex, val, vl); +} + +// Indexed-Ordered Load/Store +vint32m1_t test_vloxei32_v_i32m1_shortcut (vuint32m1_t bindex, size_t vl) +{ + return __riscv_vloxei32_v_i32m1 ((int32_t *)0, bindex, vl); +} + +vuint32m1_t test_vloxei32_v_u32m1_shortcut (vuint32m1_t bindex, size_t vl) +{ + return __riscv_vloxei32_v_u32m1 ((uint32_t *)0, bindex, vl); +} + +vfloat32m1_t test_vloxei32_v_f32m1_shortcut (vuint32m1_t bindex, size_t vl) +{ + return __riscv_vloxei32_v_f32m1 ((float32_t *)0, bindex, vl); +} + +void test_vsoxei32_v_i32m1_shortcut (vuint32m1_t bindex, vint32m1_t val, size_t vl) +{ + __riscv_vsoxei32_v_i32m1 ((int32_t *)0, bindex, val, vl); +} + +void test_vsoxei32_v_u32m1_shortcut (vuint32m1_t bindex, vuint32m1_t val, size_t vl) +{ + __riscv_vsoxei32_v_u32m1 ((uint32_t *)0, bindex, val, vl); +} + +void test_vsoxei32_v_f32m1_shortcut (vuint32m1_t bindex, vfloat32m1_t val, size_t vl) +{ + __riscv_vsoxei32_v_f32m1 ((float32_t *)0, bindex, val, vl); +} + +/* { dg-final { scan-assembler-times {v[ls]e[0-9]+\.v\s+v[0-9]+,\s*0\(zero\)} 6 } } */ +/* { dg-final { scan-assembler-times {v[ls]se[0-9]+\.v\s+v[0-9]+,\s*0\(zero\),\s*[ax][0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {li\s+[a-x][0-9]+,\s*0} 12 } } */ -- 2.34.1