From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 68A7F3858C53 for ; Wed, 26 Apr 2023 13:06:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 68A7F3858C53 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682514401; x=1714050401; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fPzsWfSIT6EKlJQz+UIvPG3O5/jUot7cOWoGbUxnGZw=; b=eN/NYVtj6AtNt34jJwZte8c+sdX8F95svrFPKZlU/hCxuwKfBWAqRZ2c pEeueTDrqrsyBxAKlTbf3yfmyEIa3I3M2UbuZ11dRYLQLTXFkK3AJbwET S4qsHOP+kxsEsmuf90UdknA8F9ts2MuYFuzeNsVeTx0obCXNy+jnw17zn JNVSBqqipKkodnr9CvZNfbvGtoBAeXI763NNvZIqo0TlZ/7pzomj1VHVz 65xhVYxp6K0BIB6bWynDYJ1BP1dDoyU7IU7SXip2erZFNHUmDwiUtM2rg HjHAOUs+/oiriYc7fS80pABYsq3mSVLSrWXfljbaU/3ySJyuG2PycSBog g==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="326700666" X-IronPort-AV: E=Sophos;i="5.99,228,1677571200"; d="scan'208";a="326700666" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 06:06:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="671335923" X-IronPort-AV: E=Sophos;i="5.99,228,1677571200"; d="scan'208";a="671335923" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga006.jf.intel.com with ESMTP; 26 Apr 2023 06:06:33 -0700 Received: from yanzhang-dev.sh.intel.com (yanzhang-dev.sh.intel.com [10.239.82.176]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 21B3E1020156; Wed, 26 Apr 2023 21:06:33 +0800 (CST) From: yanzhang.wang@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v2] RISC-V: ICE for vlmul_ext_v intrinsic API Date: Wed, 26 Apr 2023 21:06:02 +0800 Message-Id: <20230426130602.3335312-1-yanzhang.wang@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230426120503.3207041-1-yanzhang.wang@intel.com> References: <20230426120503.3207041-1-yanzhang.wang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Yanzhang Wang PR 109617 gcc/ChangeLog: * config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test. Signed-off-by: Yanzhang Wang Co-authored-by: Pan Li --- gcc/config/riscv/vector-iterators.md | 3 ++- .../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index a8e856161d3..033659930d1 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -189,6 +189,7 @@ (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") + (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") (VNx4SF "TARGET_VECTOR_ELEN_FP_32") @@ -220,7 +221,7 @@ (define_mode_iterator VLMULEXT32 [ (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN >= 128") - (VNx1HI "TARGET_MIN_VLEN < 128") + (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN >= 128") ]) (define_mode_iterator VLMULEXT64 [ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c new file mode 100644 index 00000000000..501d98c5897 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include + +vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) { + return __riscv_vlmul_ext_v_i16mf4_i16m8(op1); +} + +vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) { + return __riscv_vlmul_ext_v_i64m2_i64m8(op1); +} + +/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */ -- 2.39.2