From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1044.google.com (mail-pj1-x1044.google.com [IPv6:2607:f8b0:4864:20::1044]) by sourceware.org (Postfix) with ESMTPS id D9CDF3858C54 for ; Wed, 26 Apr 2023 21:22:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D9CDF3858C54 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pj1-x1044.google.com with SMTP id 98e67ed59e1d1-24b725d6898so3942790a91.2 for ; Wed, 26 Apr 2023 14:22:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682544165; x=1685136165; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PUpi3XLqygHwGoAzOPbus/V1wIO0wMVzB2NUmUUJZ9E=; b=Nsk/KFeHjEU4hHrIfSm+Z2NaX/SgobP3dm/W5MGFrkSud9xBpwYEfGSt7CBZCGZ0JH nDWA1WDNHZrD8iZurwUt0ahgtKsHxgAULkvnRK5+fhMO19CCU4sysUbvff+BErOEBVZQ INZlEFHE5nAJBEAqNUpuAEi62SvK+7fnHoqwyXwNcAXyixsWygZedvmJDlR27jk6xKqu keQR6inW1j8hLpckyGcA3e5i9spe3HOHgVoLcIcqQjzFa5Tu6ZnfT4yW+qlXkMqEIWrK ZnByUY21M/25tm0L3kmUQUWukf+wQ9z9LRrGIChMaz/s+tkaP5t/CejTUdD6M5tagZ2U ahyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682544165; x=1685136165; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PUpi3XLqygHwGoAzOPbus/V1wIO0wMVzB2NUmUUJZ9E=; b=Tiwa4Jc4n9pubYVmNBmRNPzVCKhHUn2/2dt4bRG/AewysSUUeSQs8vS/UXJ6c3971H uMePD3ZnNFS7hZZwKObmxbuGGlvoOYup82kAyL2EK9TtmIZn7YWDtawc8hBcD4ZDm89T hcHCN7rP7hNWhQuWy0Iz78ma2WHHpTpU5RW7yO8SycQ68IMclOAy9vdIxeWJRXxwJU+n VvXuGl/I7ekutHNtPLf82/aYXDdcmG6EoE7HXuOkoTePovUNy9T4OMtrE/HgT0wv5/MS JSAeoccMJMRer8kWW2UrffHnEGJssFbCY1/3qU84GZ+OFz0/Em3HPQE/eEppQo5FJL9u Uoxg== X-Gm-Message-State: AAQBX9e2WlajSbQEXV59gR1kslfjS009jncu8RWfTJUgxZ3LrpSVCuKL 2VOQsZlxAMnwR19hutp1M8dNQkCL5P7ZEHIFeX42tDFTmfQ= X-Google-Smtp-Source: AKy350Z0BLbIhZ/OQXcl0LT7+fkNW4UAAkfnp07oVYbcH5ceAAg+qusWbfS0FB0Di3y+YYLNQALPMA== X-Received: by 2002:a17:90a:46cb:b0:23b:4388:7d8a with SMTP id x11-20020a17090a46cb00b0023b43887d8amr21315933pjg.21.1682544165563; Wed, 26 Apr 2023 14:22:45 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id r7-20020a635147000000b00519c3475f21sm8778466pgl.46.2023.04.26.14.22.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Apr 2023 14:22:45 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rep.dot.nop@gmail.com, jeffreyalaw@gmail.com, schwab@linux-m68k.org, Patrick O'Neill Subject: [PATCH v2] RISC-V: Fix sync.md and riscv.cc whitespace errors Date: Wed, 26 Apr 2023 14:21:06 -0700 Message-Id: <20230426212106.1134636-1-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230426205349.1131469-1-patrick@rivosinc.com> References: <20230426205349.1131469-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,MEDICAL_SUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch fixes whitespace errors introduced with https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html 2023-04-26 Patrick O'Neill gcc/ChangeLog: * config/riscv/riscv.cc: Fix whitespace. * config/riscv/sync.md: Fix whitespace. Signed-off-by: Patrick O'Neill --- Patch was checked with contrib/check_GNU_style.py Whitespace changes in this patch are 2 flavors: * Add space between function name and () * 2 spaces between end of comment and */ --- v2 Changelog: * Ignored checker warning for space before [] in rtl --- gcc/config/riscv/riscv.cc | 6 +++--- gcc/config/riscv/sync.md | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 0f890469d7a..1529855a2b4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7193,7 +7193,7 @@ riscv_subword_address (rtx mem, rtx *aligned_mem, rtx *shift, rtx *mask, emit_move_insn (*mask, gen_rtx_ASHIFT (SImode, *mask, gen_lowpart (QImode, *shift))); - emit_move_insn (*not_mask, gen_rtx_NOT(SImode, *mask)); + emit_move_insn (*not_mask, gen_rtx_NOT (SImode, *mask)); } /* Leftshift a subword within an SImode register. */ @@ -7206,8 +7206,8 @@ riscv_lshift_subword (machine_mode mode, rtx value, rtx shift, emit_move_insn (value_reg, simplify_gen_subreg (SImode, value, mode, 0)); - emit_move_insn(*shifted_value, gen_rtx_ASHIFT (SImode, value_reg, - gen_lowpart (QImode, shift))); + emit_move_insn (*shifted_value, gen_rtx_ASHIFT (SImode, value_reg, + gen_lowpart (QImode, shift))); } /* Initialize the GCC target structure. */ diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 83be6431cb6..19274528262 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -128,10 +128,10 @@ { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_fetch_strong_nand to implement a LR/SC version of the - operation. */ + operation. */ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining - is disabled */ + is disabled. */ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; @@ -193,10 +193,10 @@ { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_fetch_strong_ to implement a LR/SC version of the - operation. */ + operation. */ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining - is disabled */ + is disabled. */ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; @@ -367,7 +367,7 @@ { rtx difference = gen_rtx_MINUS (SImode, val, exp); compare = gen_reg_rtx (SImode); - emit_move_insn (compare, difference); + emit_move_insn (compare, difference); } if (word_mode != SImode) @@ -393,10 +393,10 @@ { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_cas_strong to implement a LR/SC version of the - operation. */ + operation. */ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining - is disabled */ + is disabled. */ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; @@ -461,7 +461,7 @@ "TARGET_ATOMIC" { /* We have no QImode atomics, so use the address LSBs to form a mask, - then use an aligned SImode atomic. */ + then use an aligned SImode atomic. */ rtx result = operands[0]; rtx mem = operands[1]; rtx model = operands[2]; -- 2.34.1