From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x1134.google.com (mail-yw1-x1134.google.com [IPv6:2607:f8b0:4864:20::1134]) by sourceware.org (Postfix) with ESMTPS id BD3793858D3C for ; Wed, 26 Apr 2023 21:45:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BD3793858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-yw1-x1134.google.com with SMTP id 00721157ae682-54fb8a8a597so92003457b3.0 for ; Wed, 26 Apr 2023 14:45:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682545515; x=1685137515; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=pvD1puHkF9Z4Sb3pqRcH4BY47cxK5UF5AbvCXU4+PjU=; b=3CjbSH1K/piwC6Zq2aD4DtgVwDCevyIzXFS/CZWC2wsReBwevEevgAXMIyyS3eF/tb oGXqb3Qeum0GUvv2bqCKsZb97WRSqt7EJyCR7PPX3xOa1ZGlyWwRRBSZNDYfTw1KNhyD viGRl5V//d3wtz2WDAkBxRVoF/EvAi3kwTzUE4mgVuCNp9eQcJLvBol9Z/xPCXNHrVHA Jmht6b/SE5V5eFZPvUqIOofLlu25imra7vYsBp94O4pP+8kg+qwz8n62EqlFtctMGz2U EL0acS14Tx5m9Q49SQTRccrvG0C4FQNoq5W0zC5O+Z9r2dm+oTrGDcmMirqJN6UfOqQP o8UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682545515; x=1685137515; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=pvD1puHkF9Z4Sb3pqRcH4BY47cxK5UF5AbvCXU4+PjU=; b=ixja2wJcJZEcUlpWnop8ina/gHUHww9j1kz1hWE94fjaIbexZWjIbg9FxBHzDqZlDM imJwHReVL7g+FKDL5tMKz1w8vC4sFjJ6pQdXB+DrnHdJlMfh/HUfyj1FlVw2c61sCTli cmqhcFN8HdpmZOYZEN+ZXr4CekyZuN2GPFcFDyeWU3siOX8fLV1FKS4utXJtYyRWneMj ruu5Dhtp30a6Z75uIS6ewFLAT/iRvG2lYR/urJILvnT3K9/+RROMAE9UwnVWao3bVNc1 OHi8LTb2iLwoaXE/bo5ZdH/efmIK1oDJBNERdJH4OU8KyZllEKJC4bG+NQ5JK51tWDnQ u3/g== X-Gm-Message-State: AAQBX9eFzqycTLUN9jty3kcimyQLORK2eJGfzsO1F2ybzYABkVP9JZ1z Yh1weQPTtejcVEzpBZbXa4GvojLo/h28gru51FI= X-Google-Smtp-Source: AKy350bHWiqHwIod++Ux+JaxF7qers0hPrdVBfqDbqkBJlxupGhBha3jLQIKsEn+dx1pYloPD52JVQ== X-Received: by 2002:a0d:c9c2:0:b0:555:be69:a805 with SMTP id l185-20020a0dc9c2000000b00555be69a805mr13574563ywd.51.1682545514811; Wed, 26 Apr 2023 14:45:14 -0700 (PDT) Received: from system76-pc.ba.rivosinc.com ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id n12-20020a0dcb0c000000b00552e32354f8sm4469824ywd.32.2023.04.26.14.45.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Apr 2023 14:45:14 -0700 (PDT) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v5 00/10] RISC-V: autovec: Add autovec support Date: Wed, 26 Apr 2023 17:45:04 -0400 Message-Id: <20230426214514.3355280-1-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This series of patches adds foundational support for RISC-V auto-vectorization support. These patches are based on the current upstream rvv vector intrinsic support and is not a new implementation. Most of the implementation consists of adding the new vector cost model, the autovectorization patterns themselves and target hooks. This implementation only provides support for integer addition and subtraction as a proof of concept. This patch set should not be construed to be feature complete. Based on conversations with the community these patches are intended to lay the groundwork for feature completion and collaboration within the RISC-V community. These patches are largely based off the work of Juzhe Zhong (juzhe.zhong@rivai.ai) of RiVAI. More specifically the rvv-next branch at: https://github.com/riscv-collab/riscv-gcc.git is the foundation of this patch set. As discussed on this list, if these patches are approved they will be merged into a "auto-vectorization" branch once gcc-13 branches for release. There are two known issues related to crashes (assert failures) associated with tree vectorization; one of which I have sent a patch for and have received feedback. Changes in v5: - Incorporated upstream comments large to delete unnecessary code Changes in v4: - Added support for binary integer operations and test cases - Fixed bug to support 8-bit integer vectorization - Fixed several assert errors related to non-multiple of two vector modes Changes in v3: - Removed the cost model and cost hooks based on feedback from Richard Biener - Used RVV_VUNDEF macro to fix failing patterns Changes in v2 - Updated ChangeLog entry to include RiVAI contributions - Fixed ChangeLog email formatting - Fixed gnu formatting issues in the code Kevin Lee (2): This patch adds a guard for VNx1 vectors that are present in ports like riscv. This patch supports 8 bit auto-vectorization in riscv. Michael Collison (8): RISC-V: Add new predicates and function prototypes RISC-V: autovec: Export policy functions to global scope RISC-V:autovec: Add auto-vectorization support functions RISC-V:autovec: Add target vectorization hooks RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store RISC-V:autovec: Add autovectorization tests for add & sub vect: Verify that GET_MODE_NUNITS is a multiple of 2. RISC-V:autovec: Add autovectorization tests for binary integer gcc/config/riscv/predicates.md | 13 ++ gcc/config/riscv/riscv-opts.h | 29 ++++ gcc/config/riscv/riscv-protos.h | 9 ++ gcc/config/riscv/riscv-v.cc | 79 +++++++++++ gcc/config/riscv/riscv-vector-builtins.cc | 4 +- gcc/config/riscv/riscv-vector-builtins.h | 3 + gcc/config/riscv/riscv.cc | 130 ++++++++++++++++++ gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/vector-auto.md | 74 ++++++++++ gcc/config/riscv/vector.md | 4 +- .../riscv/rvv/autovec/loop-add-rv32.c | 25 ++++ .../gcc.target/riscv/rvv/autovec/loop-add.c | 25 ++++ .../riscv/rvv/autovec/loop-and-rv32.c | 25 ++++ .../gcc.target/riscv/rvv/autovec/loop-and.c | 25 ++++ .../riscv/rvv/autovec/loop-div-rv32.c | 27 ++++ .../gcc.target/riscv/rvv/autovec/loop-div.c | 27 ++++ .../riscv/rvv/autovec/loop-max-rv32.c | 26 ++++ .../gcc.target/riscv/rvv/autovec/loop-max.c | 26 ++++ .../riscv/rvv/autovec/loop-min-rv32.c | 26 ++++ .../gcc.target/riscv/rvv/autovec/loop-min.c | 26 ++++ .../riscv/rvv/autovec/loop-mod-rv32.c | 27 ++++ .../gcc.target/riscv/rvv/autovec/loop-mod.c | 27 ++++ .../riscv/rvv/autovec/loop-mul-rv32.c | 25 ++++ .../gcc.target/riscv/rvv/autovec/loop-mul.c | 25 ++++ .../riscv/rvv/autovec/loop-or-rv32.c | 25 ++++ .../gcc.target/riscv/rvv/autovec/loop-or.c | 25 ++++ .../riscv/rvv/autovec/loop-sub-rv32.c | 25 ++++ .../gcc.target/riscv/rvv/autovec/loop-sub.c | 25 ++++ .../riscv/rvv/autovec/loop-xor-rv32.c | 25 ++++ .../gcc.target/riscv/rvv/autovec/loop-xor.c | 25 ++++ gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 3 + gcc/tree-vect-data-refs.cc | 2 + gcc/tree-vect-slp.cc | 7 +- 33 files changed, 864 insertions(+), 6 deletions(-) create mode 100644 gcc/config/riscv/vector-auto.md create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c -- 2.34.1