From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112b.google.com (mail-yw1-x112b.google.com [IPv6:2607:f8b0:4864:20::112b]) by sourceware.org (Postfix) with ESMTPS id ECD003858439 for ; Wed, 26 Apr 2023 21:45:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org ECD003858439 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-yw1-x112b.google.com with SMTP id 00721157ae682-54f8d59a8a9so93420467b3.0 for ; Wed, 26 Apr 2023 14:45:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682545521; x=1685137521; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VyHAD8E0OPizmeHn+X5YAKG8FvFcvnfSwyDlkCWAN4U=; b=cJaR9Np2KQyzix8Cy3vcSWg3Q6L2DuE+5iVaUib5ytbmAY8qMsfoC4JzppmTLwBSiS BLfDBQJTaYL4QKHakXKce0gk5yjFvac1qnmVuhM1r9WKRBun2DDwePDvMXsRAMjyBRj6 WLf3GKR9x8hYPp/yT7SFP9E8ZSF8VdJZv2KWM14lrKb8H9y3CSvcQpTE5jGqAIqwTwIp /6e0RJ1BHESMXJuejR6kyR48HGDKOEvK2tG9QANHLavuYZCkYLGWqjpMdpqKmt7Le3fS cT4SIDz+JfO88Gt4ZBWdmzw8tfXYHgAAJFoyYXArgMsRHc8qWp1WSR50icw+dm9sQ3Jf lnWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682545521; x=1685137521; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VyHAD8E0OPizmeHn+X5YAKG8FvFcvnfSwyDlkCWAN4U=; b=VBB22wVAwrYEQau7i3y0os2qJgJ2MP8tJ9r3GEJleEKCbT5kjaKBTAD6r8jf4pl/V3 Jw+CXnGA4Wz5EkkMOYTvsCbu0Vs/pjD6Qr8DzVemSv/oBgM9yvvrZmsNH42QMFzEgN4R o2ln2Xc8tLdhI1WHgB2rMnNMJiL8lwdY4ETARne9//xn9URLh/GhwFBlWF48I9uGyOR0 aVkhEmCR9DDnmSZJHWuipT4VzgiSjzOnlFm9cQD0EXUwowoOUiEzz7nQGsb4SP6uDatw gkG9HpNONpTM6one9QcvMTUFVtmspLycUNEyNQ+3U0Xu7me/mZemw7vnAM+E5OKvdOKO zUwQ== X-Gm-Message-State: AAQBX9d99HLd+g65F7UvpWIg2+btKpNZr6Q7GFCjBTYet7YPiNiGZBAi PbPrexP99n9aqNYQZx0udy9OtxRDfwpabTBTwl0= X-Google-Smtp-Source: AKy350aDVd4T4nzxT7mMy7jdGDi47Hzg+wozlfY6DJLMcDwpnpNmZAuVejigw2qE9P3VxVRhEKSwAw== X-Received: by 2002:a0d:fc46:0:b0:54f:b133:b2d with SMTP id m67-20020a0dfc46000000b0054fb1330b2dmr15270570ywf.26.1682545520959; Wed, 26 Apr 2023 14:45:20 -0700 (PDT) Received: from system76-pc.ba.rivosinc.com ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id n12-20020a0dcb0c000000b00552e32354f8sm4469824ywd.32.2023.04.26.14.45.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Apr 2023 14:45:20 -0700 (PDT) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v5 10/10] RISC-V: autovec: This patch supports 8 bit auto-vectorization in riscv. Date: Wed, 26 Apr 2023 17:45:14 -0400 Message-Id: <20230426214514.3355280-11-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230426214514.3355280-1-collison@rivosinc.com> References: <20230426214514.3355280-1-collison@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Kevin Lee 2023-04-14 Kevin Lee gcc/testsuite/ChangeLog: * config/riscv/riscv.cc (riscv_autovectorize_vector_modes): Add new vector mode * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit type * gcc.target/riscv/rvv/autovec/loop-add.c: Ditto * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-and.c: Ditto * gcc.target/riscv/rvv/autovec/loop-div-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-div.c: Ditto * gcc.target/riscv/rvv/autovec/loop-max-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-max.c: Ditto * gcc.target/riscv/rvv/autovec/loop-min-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-min.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mod-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mod.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mul-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mul.c: Ditto * gcc.target/riscv/rvv/autovec/loop-or-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-or.c: Ditto * gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-sub.c: Ditto * gcc.target/riscv/rvv/autovec/loop-xor-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-xor.c: Ditto --- gcc/config/riscv/riscv.cc | 1 + .../gcc.target/riscv/rvv/autovec/loop-add-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c | 5 +++-- .../gcc.target/riscv/rvv/autovec/loop-and-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c | 5 +++-- .../gcc.target/riscv/rvv/autovec/loop-div-rv32.c | 8 +++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/loop-max-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-min-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-mod-rv32.c | 8 +++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/loop-mul-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c | 5 +++-- .../gcc.target/riscv/rvv/autovec/loop-sub-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c | 5 +++-- .../gcc.target/riscv/rvv/autovec/loop-xor-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c | 5 +++-- 21 files changed, 73 insertions(+), 48 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 77209b161f6..f293414acd1 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7143,6 +7143,7 @@ riscv_autovectorize_vector_modes (vector_modes *modes, bool) modes->safe_push (VNx8QImode); modes->safe_push (VNx4QImode); modes->safe_push (VNx2QImode); + modes->safe_push (VNx1QImode); } return 0; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c index bdc3b6892e9..76f5a3a3ff5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] + b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c index d7f992c7d27..3d1e10bf4e1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c @@ -10,8 +10,9 @@ dst[i] = a[i] + b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c index eb1ac5b44fd..a4c7abfb0ad 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] & b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c index ff0cc2a5df7..a795e0968a9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c @@ -10,8 +10,9 @@ dst[i] = a[i] & b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c index 21960f265b7..c734bb9c5f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] / b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c index bd675b4f6f0..9f57cd91054 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c @@ -10,8 +10,9 @@ dst[i] = a[i] / b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c index 751ee9ecaa3..bd825c3dfaa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c index f4dbf3f04fc..729fbe0bc76 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c @@ -10,8 +10,9 @@ dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c index e51cf590577..808c2879d86 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c index 304f939f6f9..c81ba64223f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c @@ -10,8 +10,9 @@ dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c index 7c497f6e4cc..9ce4f82b3a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] % b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c index 7508f4a50d1..46fbff22266 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c @@ -10,8 +10,9 @@ dst[i] = a[i] % b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c index fd6dcbf9c53..336af62359e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] * b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c index 9fce40890ef..12a17d0da00 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c @@ -10,8 +10,9 @@ dst[i] = a[i] * b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c index 305d106abd9..b272d893114 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] | b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c index 501017bc790..52243be3712 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c @@ -10,8 +10,9 @@ dst[i] = a[i] | b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c index 7d0a40ec539..6fdce0f7881 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] - b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c index c8900884f83..73369745afc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c @@ -10,8 +10,9 @@ dst[i] = a[i] - b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c index 6a9ffdb11d5..bd43e60cceb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] ^ b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c index c9d7d7f8a75..cb3adde80c9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c @@ -10,8 +10,9 @@ dst[i] = a[i] ^ b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */ -- 2.34.1