From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112d.google.com (mail-yw1-x112d.google.com [IPv6:2607:f8b0:4864:20::112d]) by sourceware.org (Postfix) with ESMTPS id ECC5F3858C54 for ; Wed, 26 Apr 2023 21:45:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org ECC5F3858C54 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-yw1-x112d.google.com with SMTP id 00721157ae682-54fc94476e2so92399837b3.1 for ; Wed, 26 Apr 2023 14:45:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682545515; x=1685137515; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8iSQfI8EHNuxf2CZCg15Wa/WSxzPujIoch4WUA35/Ck=; b=QBCfWH6ixXzOx7kkVFU4KNe+ftWCohvgU2WpfUOP8JEu3jRPi/fnGVr9+Mrm0akUpd WTybRp3qUU7DkhGCHnLVFDFl9ShfW1P968LyXT27YYL1JrL7BumaR8IJluC/J7BBFcg7 /jmUkKlzd2KAIa5Ebm4KdKXEK4gcRsuUHOTGCCtbNlk3KSBbojgVM4qQbTKWrfkNxKIr ohfrfdsCnIummmMNtAb5YZ8SznqwxLFRaHRoOtO0cEDadfk1hmgzcIeC8tR8T4zU+WcY BsnTnXqOwR8cdoZ7i6wUDOXM/3hlUYhd0GlfU10VQtCBrjpuh5bDgCRjY2Qd0qkkdv58 7ifg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682545515; x=1685137515; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8iSQfI8EHNuxf2CZCg15Wa/WSxzPujIoch4WUA35/Ck=; b=KFMc/dy+QFNXQhdWKFZQFAJooFoXnWYaICZefo/NfPkXJseRH2agxbQ+OJulMF6keG 6/foYib3kiCDecirGPW44/xq1rC6OLETQCgjfRGmkrVWhvdtrZEeWfWvYEUJjfcIBsdN KjYvL4nIM6k/B8hF5mX6V4MMPRVnpJYgk+kT/Tymz0H2xnEtG12im9Q5ApvmPZle3Jz7 uz4NTw1ynFoiHt2Hrk5C674Pz/SIi8Hi8UEW+AHgqOjdsPBj+fyRWxzdWeM3QRWjTEnk YEqDSMhfLXuGB55ky7GOlS91x1LxFMJbozSNRuaOCoF87Is3x6uj1+iVojfJuIoY+xH9 dyag== X-Gm-Message-State: AAQBX9ffoDuwHwbTcc4KKzUKoufo0t4Cje8LMjUTaGTCEcUjQb4YDBj9 FYg/sxE/ZNiauYJxzwfbMXkptz3PZkoLIQll4CI= X-Google-Smtp-Source: AKy350bnLIHqHBxj6qiFjLnrc65uxePwN/ey1ZXmteK/tvr5pR6ojbCIvZVvN9VF2rJLV0ZAkYJzog== X-Received: by 2002:a81:9245:0:b0:54f:e085:58d9 with SMTP id j66-20020a819245000000b0054fe08558d9mr14094645ywg.46.1682545515199; Wed, 26 Apr 2023 14:45:15 -0700 (PDT) Received: from system76-pc.ba.rivosinc.com ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id n12-20020a0dcb0c000000b00552e32354f8sm4469824ywd.32.2023.04.26.14.45.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Apr 2023 14:45:15 -0700 (PDT) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v5 01/10] RISC-V: autovec: Add new predicates and function prototypes Date: Wed, 26 Apr 2023 17:45:05 -0400 Message-Id: <20230426214514.3355280-2-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230426214514.3355280-1-collison@rivosinc.com> References: <20230426214514.3355280-1-collison@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: 2023-04-24 Michael Collison Juzhe Zhong * config/riscv/riscv-protos.h (riscv_vector_preferred_simd_mode): New. (riscv_vector_mask_mode_p): Ditto. (riscv_vector_get_mask_mode): Ditto. (emit_vlmax_vsetvl): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. (vlmul_field_enum): Ditto. * config/riscv/riscv-v.cc (emit_vlmax_vsetvl): Remove static scope. * config/riscv/predicates.md (p_reg_or_const_csr_operand): New predicate. (vector_reg_or_const_dup_operand): Ditto. * config/riscv/riscv-opts.h (riscv_vector_bits_enum): New enum. (riscv_vector_lmul_enum): Ditto. (vlmul_field_enum): Ditto. --- gcc/config/riscv/predicates.md | 13 +++++++++++++ gcc/config/riscv/riscv-opts.h | 29 +++++++++++++++++++++++++++++ gcc/config/riscv/riscv-protos.h | 9 +++++++++ 3 files changed, 51 insertions(+) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 8654dbc5943..b3f2d622c7b 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -264,6 +264,14 @@ }) ;; Predicates for the V extension. +(define_special_predicate "p_reg_or_const_csr_operand" + (match_code "reg, subreg, const_int") +{ + if (CONST_INT_P (op)) + return satisfies_constraint_K (op); + return GET_MODE (op) == Pmode; +}) + (define_special_predicate "vector_length_operand" (ior (match_operand 0 "pmode_register_operand") (match_operand 0 "const_csr_operand"))) @@ -291,6 +299,11 @@ (and (match_code "const_vector") (match_test "rtx_equal_p (op, riscv_vector::gen_scalar_move_mask (GET_MODE (op)))"))) +(define_predicate "vector_reg_or_const_dup_operand" + (ior (match_operand 0 "register_operand") + (match_test "const_vec_duplicate_p (op) + && !CONST_POLY_INT_P (CONST_VECTOR_ELT (op, 0))"))) + (define_predicate "vector_mask_operand" (ior (match_operand 0 "register_operand") (match_operand 0 "vector_all_trues_mask_operand"))) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index cf0cd669be4..af77df11430 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -67,6 +67,35 @@ enum stack_protector_guard { SSP_GLOBAL /* global canary */ }; +/* RISC-V auto-vectorization preference. */ +enum riscv_autovec_preference_enum { + NO_AUTOVEC, + RVV_SCALABLE, + RVV_FIXED_VLMAX +}; + +/* vectorization factor. */ +enum riscv_vector_lmul_enum +{ + RVV_LMUL1 = 1, + RVV_LMUL2 = 2, + RVV_LMUL4 = 4, + RVV_LMUL8 = 8 +}; + +enum vlmul_field_enum +{ + VLMUL_FIELD_000, /* LMUL = 1. */ + VLMUL_FIELD_001, /* LMUL = 2. */ + VLMUL_FIELD_010, /* LMUL = 4. */ + VLMUL_FIELD_011, /* LMUL = 8. */ + VLMUL_FIELD_100, /* RESERVED. */ + VLMUL_FIELD_101, /* LMUL = 1/8. */ + VLMUL_FIELD_110, /* LMUL = 1/4. */ + VLMUL_FIELD_111, /* LMUL = 1/2. */ + MAX_VLMUL_FIELD +}; + #define MASK_ZICSR (1 << 0) #define MASK_ZIFENCEI (1 << 1) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 5244e8dcbf0..55056222e57 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -237,4 +237,13 @@ extern const char* th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); #endif +/* Routines implemented in riscv-v.cc. */ + +namespace riscv_vector { +extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode); +extern bool riscv_vector_mask_mode_p (machine_mode); +extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode); +extern rtx get_mask_policy_no_pred (); +extern rtx get_tail_policy_no_pred (); +} #endif /* ! GCC_RISCV_PROTOS_H */ -- 2.34.1