From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x1132.google.com (mail-yw1-x1132.google.com [IPv6:2607:f8b0:4864:20::1132]) by sourceware.org (Postfix) with ESMTPS id 11EF73858C60 for ; Wed, 26 Apr 2023 21:45:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 11EF73858C60 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-yw1-x1132.google.com with SMTP id 00721157ae682-54f9d6eccf3so91948147b3.2 for ; Wed, 26 Apr 2023 14:45:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682545516; x=1685137516; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=6pnW24Sh3iAFjZcKaX99961qsS6TmwayWQhBuoY06KY=; b=V/HAuY3HqACeidbQP2wsMCUxoinG0KTBs/9TLcHdIO4yedJHLTOsonHDqvNHYF07zE WVCauvT6jvuyZwSDxw6mTxqEcDE7K31XTtY6a0pE8ScIGcMb4MOY3pmM6KTAldrRZzu0 GiLrFW4ZKQN7q8g47DnKViTEchnZGO6u+9iJnlhii3p6I5Uyq2/Xc4HihYcNA+iR8lyw 9glxAgLtSbMf1Bh/w5flwuytVO6jZMWC9Ca1oAnG0gp8p2Lh4UPyb2/70mEWTiXa6zB3 a9ibIjPOdDNCtWLbihUie7LnZS1f4f3LSJ+a2h6xjUHpMIXoI6qhBWxlS+FspqQ9EVhC ML+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682545516; x=1685137516; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6pnW24Sh3iAFjZcKaX99961qsS6TmwayWQhBuoY06KY=; b=cU5D5FZ49PBi9p1VWO6OlJlLSvCzcmCRVrFeeCWCeLssYue/VpcWzHLb8so5+ORO2r IC0Pdu9lbtfR90pnOQXmuAxYSBkbJm6pTHyIexgNA2SPLAOjoBAQARZzeII1dChAxwVz CAghWvBOBqGjTQl4sRjuR3KQnh+NP4bn91BPl9RfZBeqH5CtvPnkBBAFaCBJRuVeGOm3 hM6AONGAmBmkIw/nKJKFVucj6lRuQVvwKOR3+D7NcmJJqz65uTtCGgCJb99yXCqZkGs1 R8knZQGRj6CqNlAF+0ChcVJkrNHoD6kWxB1ZTHmpKFQeiNAB8bViuDUyuQ7fGP32Bg7R qovg== X-Gm-Message-State: AAQBX9fQz3qayrYHzAUDDyGRAp5jQn+cdNlA7pbx58h5maYIkpUiuMPk j1sYGjq2eWiOdhfm+ypMWCPwC5N9nnirTI2b76E= X-Google-Smtp-Source: AKy350bxNCyukaL2GLXi5q0oSH86lSQIIfzCqBHX1H/tnug/H+ijdiQ8zcjalXMAWgbjK6wnDS/h5g== X-Received: by 2002:a0d:d5cb:0:b0:536:eb74:8089 with SMTP id x194-20020a0dd5cb000000b00536eb748089mr15358162ywd.30.1682545516276; Wed, 26 Apr 2023 14:45:16 -0700 (PDT) Received: from system76-pc.ba.rivosinc.com ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id n12-20020a0dcb0c000000b00552e32354f8sm4469824ywd.32.2023.04.26.14.45.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Apr 2023 14:45:15 -0700 (PDT) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions Date: Wed, 26 Apr 2023 17:45:07 -0400 Message-Id: <20230426214514.3355280-4-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230426214514.3355280-1-collison@rivosinc.com> References: <20230426214514.3355280-1-collison@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: 2023-04-24 Michael Collison Juzhe Zhong * config/riscv/riscv-v.cc (riscv_vector_preferred_simd_mode): New function. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. (riscv_vector_mask_mode_p): Ditto. (riscv_vector_get_mask_mode): Ditto. --- gcc/config/riscv/riscv-v.cc | 79 +++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 392f5d02e17..ecd98680d64 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -39,9 +39,11 @@ #include "emit-rtl.h" #include "tm_p.h" #include "target.h" +#include "targhooks.h" #include "expr.h" #include "optabs.h" #include "tm-constrs.h" +#include "riscv-vector-builtins.h" #include "rtx-vector-builder.h" using namespace riscv_vector; @@ -176,6 +178,46 @@ calculate_ratio (unsigned int sew, enum vlmul_type vlmul) return ratio; } +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE for RVV. */ + +machine_mode +riscv_vector_preferred_simd_mode (scalar_mode mode) +{ + if (!TARGET_VECTOR) + return word_mode; + + switch (mode) + { + case E_QImode: + return VNx8QImode; + break; + case E_HImode: + return VNx4HImode; + break; + case E_SImode: + return VNx2SImode; + break; + case E_DImode: + if (riscv_vector_elen_flags != MASK_VECTOR_ELEN_32 + && riscv_vector_elen_flags != MASK_VECTOR_ELEN_FP_32) + return VNx1DImode; + break; + case E_SFmode: + if (TARGET_HARD_FLOAT && riscv_vector_elen_flags != MASK_VECTOR_ELEN_32 + && riscv_vector_elen_flags != MASK_VECTOR_ELEN_64) + return VNx2SFmode; + break; + case E_DFmode: + if (TARGET_DOUBLE_FLOAT && TARGET_VECTOR_ELEN_FP_64) + return VNx1DFmode; + break; + default: + break; + } + + return word_mode; +} + /* Emit an RVV unmask && vl mov from SRC to DEST. */ static void emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len, @@ -421,6 +463,43 @@ get_avl_type_rtx (enum avl_type type) return gen_int_mode (type, Pmode); } +rtx +get_mask_policy_no_pred () +{ + return get_mask_policy_for_pred (PRED_TYPE_none); +} + +rtx +get_tail_policy_no_pred () +{ + return get_mask_policy_for_pred (PRED_TYPE_none); +} + +/* Return true if it is a RVV mask mode. */ +bool +riscv_vector_mask_mode_p (machine_mode mode) +{ + return (mode == VNx1BImode || mode == VNx2BImode || mode == VNx4BImode + || mode == VNx8BImode || mode == VNx16BImode || mode == VNx32BImode + || mode == VNx64BImode); +} + +/* Implement TARGET_VECTORIZE_GET_MASK_MODE for RVV. */ + +opt_machine_mode +riscv_vector_get_mask_mode (machine_mode mode) +{ + machine_mode mask_mode; + int nf = 1; + + FOR_EACH_MODE_IN_CLASS (mask_mode, MODE_VECTOR_BOOL) + if (GET_MODE_INNER (mask_mode) == BImode + && known_eq (GET_MODE_NUNITS (mask_mode) * nf, GET_MODE_NUNITS (mode)) + && riscv_vector_mask_mode_p (mask_mode)) + return mask_mode; + return default_get_mask_mode (mode); +} + /* Return the RVV vector mode that has NUNITS elements of mode INNER_MODE. This function is not only used by builtins, but also will be used by auto-vectorization in the future. */ -- 2.34.1