From: Michael Collison <collison@rivosinc.com>
To: gcc-patches@gcc.gnu.org
Subject: [PATCH v5 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2.
Date: Wed, 26 Apr 2023 17:45:11 -0400 [thread overview]
Message-ID: <20230426214514.3355280-8-collison@rivosinc.com> (raw)
In-Reply-To: <20230426214514.3355280-1-collison@rivosinc.com>
While working on autovectorizing for the RISCV port I encountered an issue
where can_duplicate_and_interleave_p assumes that GET_MODE_NUNITS is a
evenly divisible by two. The RISC-V target has vector modes (e.g. VNx1DImode),
where GET_MODE_NUNITS is equal to one.
Tested on RISCV and x86_64-linux-gnu. Okay?
2023-03-09 Michael Collison <collison@rivosinc.com>
* tree-vect-slp.cc (can_duplicate_and_interleave_p):
Check that GET_MODE_NUNITS is a multiple of 2.
---
gcc/tree-vect-slp.cc | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index d73deaecce0..a64fe454e19 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -423,10 +423,13 @@ can_duplicate_and_interleave_p (vec_info *vinfo, unsigned int count,
(GET_MODE_BITSIZE (int_mode), 1);
tree vector_type
= get_vectype_for_scalar_type (vinfo, int_type, count);
+ poly_int64 half_nelts;
if (vector_type
&& VECTOR_MODE_P (TYPE_MODE (vector_type))
&& known_eq (GET_MODE_SIZE (TYPE_MODE (vector_type)),
- GET_MODE_SIZE (base_vector_mode)))
+ GET_MODE_SIZE (base_vector_mode))
+ && multiple_p (GET_MODE_NUNITS (TYPE_MODE (vector_type)),
+ 2, &half_nelts))
{
/* Try fusing consecutive sequences of COUNT / NVECTORS elements
together into elements of type INT_TYPE and using the result
@@ -434,7 +437,7 @@ can_duplicate_and_interleave_p (vec_info *vinfo, unsigned int count,
poly_uint64 nelts = GET_MODE_NUNITS (TYPE_MODE (vector_type));
vec_perm_builder sel1 (nelts, 2, 3);
vec_perm_builder sel2 (nelts, 2, 3);
- poly_int64 half_nelts = exact_div (nelts, 2);
+
for (unsigned int i = 0; i < 3; ++i)
{
sel1.quick_push (i);
--
2.34.1
next prev parent reply other threads:[~2023-04-26 21:45 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-26 21:45 [PATCH v5 00/10] RISC-V: autovec: Add autovec support Michael Collison
2023-04-26 21:45 ` [PATCH v5 01/10] RISC-V: autovec: Add new predicates and function prototypes Michael Collison
2023-04-28 22:28 ` Jeff Law
2023-04-26 21:45 ` [PATCH v5 02/10] RISC-V: autovec: Export policy functions to global scope Michael Collison
2023-04-28 22:15 ` Jeff Law
2023-04-26 21:45 ` [PATCH v5 03/10] RISC-V:autovec: Add auto-vectorization support functions Michael Collison
2023-04-28 22:19 ` Jeff Law
2023-05-03 10:53 ` Kito Cheng
2023-05-03 17:31 ` Michael Collison
2023-05-06 20:13 ` Jeff Law
2023-04-26 21:45 ` [PATCH v5 04/10] RISC-V:autovec: Add target vectorization hooks Michael Collison
2023-05-03 10:59 ` Kito Cheng
2023-04-26 21:45 ` [PATCH v5 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store Michael Collison
2023-04-26 21:45 ` [PATCH v5 06/10] RISC-V:autovec: Add autovectorization tests for add & sub Michael Collison
2023-04-26 21:45 ` Michael Collison [this message]
2023-05-02 10:11 ` [PATCH v5 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2 Richard Sandiford
2023-04-26 21:45 ` [PATCH v5 08/10] RISC-V:autovec: Add autovectorization tests for binary integer Michael Collison
2023-04-26 21:45 ` [PATCH v5 09/10] RISC-V: autovec: This patch adds a guard for VNx1 vectors that are present in ports like riscv Michael Collison
2023-04-26 21:45 ` [PATCH v5 10/10] RISC-V: autovec: This patch supports 8 bit auto-vectorization in riscv Michael Collison
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