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From: Kito Cheng <kito.cheng@sifive.com>
To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com,
	palmer@dabbelt.com, jeffreyalaw@gmail.com
Cc: Kito Cheng <kito.cheng@sifive.com>
Subject: [PATCH v2] Docs: Add vector register constarint for asm operands
Date: Thu, 27 Apr 2023 22:01:07 +0800	[thread overview]
Message-ID: <20230427140106.40452-1-kito.cheng@sifive.com> (raw)

`vr`, `vm` and `vd` constarint for vector register constarint, those 3
constarint has implemented on LLVM as well.

gcc/ChangeLog:

	* doc/md.texi (RISC-V): Add vr, vm, vd constarint.

---

V2 changes:
- Drop unrelated changes.

---
 gcc/doc/md.texi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 07bf8bdebffb..cc4a93a87638 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3535,6 +3535,15 @@ An address that is held in a general-purpose register.
 @item S
 A constraint that matches an absolute symbolic address.
 
+@item vr
+A vector register (if available)..
+
+@item vd
+A vector register, excluding v0 (if available).
+
+@item vm
+A vector register, only v0 (if available).
+
 @end table
 
 @item RX---@file{config/rx/constraints.md}
-- 
2.39.2


             reply	other threads:[~2023-04-27 14:01 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-27 14:01 Kito Cheng [this message]
2023-05-03 10:34 ` Kito Cheng

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