From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by sourceware.org (Postfix) with ESMTPS id 2619A3858D33 for ; Thu, 27 Apr 2023 14:01:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2619A3858D33 Authentication-Results: sourceware.org; dmarc=pass (p=quarantine dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-63b35789313so6053923b3a.3 for ; Thu, 27 Apr 2023 07:01:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1682604101; x=1685196101; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=mnn0bWnAGFl/9Cjh9mFz8RMsfDRFXW143nw2rM+MQaY=; b=REo4tlEe/t8etFIm+xIL3JoQlkWBsJ9+PtM3nPAPI/09oFQxO/eDMCjYm16tkIaAw+ kfCPTfzRjSX5c2c3vI+DNSVdnKCyCUggTtFsQq5AdkiymJs0kPI+Ccv8tWVSRfSriGNM MdTs6oLXP99Nx4duQXjJNf5zQk/aBJRcOSXH733WmWa+qyrkydrZVywtRB7HTtdRa7Mu IMex3IIbKubfFqNO2VzV5bLmo+tQzxyuUqEltlw3/5oC2tleI7K/d+l/ps5SjI8mDO/5 6M3C8SRhTxUI6IJ4WYUZdjq8PxzaGQnkYfTzNWldSq0m0HAzlQSE34CfAD0NFEq5ZsrM PlDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682604101; x=1685196101; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=mnn0bWnAGFl/9Cjh9mFz8RMsfDRFXW143nw2rM+MQaY=; b=HIGS8FBVPzcqWG93EOnfPL2LnXISmc5hjPyJgbD2CzM7Ia42+O4JBg0Y2Jacl4FLw0 FvPFX1nnbWJUImnmSnbmjhkCMRr/kETlQkoeYWTKMjMIwd2ov2dbtM5I3BxJqBfEZda5 6IyqrvUhY7u9vhaCOYlLOvl234lQGmgLXCA4Jm6aTvs7FSqo5iEU4EU+z621WoNyDVb3 ux+qBnTnCN/1ByF+9BeLJXo9JaoNJQanEc7TMWxD10Qe+QBvDQU2VurA2AMqUzg9gy/R DCf0z0TNNUPEXWkmW78Bt2w8yTt/I9YA8TLsS9iwdXVVG9fjD4P5DhZ0h88eP6DhxYzI LM+w== X-Gm-Message-State: AC+VfDxBweqJhOCNAk7i/Y+yPHe0U7cOQXiZ1p63zvNq6byYWMa2RmE8 HJjVDGUqNKTwxbkDhEaCY4wrFTXq8/kwuP6JmcBRt+uRIyVRcceFVAYXSiT+dhJTkt5iGMjJEN6 6/nU9ggSmEvBeToBgbjLLgoFKJqcy3wY96DVji0zgNPkjG9b/incBGY+LmWhiISCM2y6IGZ0NiP vq7Vo= X-Google-Smtp-Source: ACHHUZ7id5PQQv9b1D7S9CGKuFXDBa6rhw1fs41qpz0TBqHRN+o9UMjY/7nnT8a1uZ95GDeZS0oSxg== X-Received: by 2002:a05:6a20:394d:b0:f0:1d03:5fe7 with SMTP id r13-20020a056a20394d00b000f01d035fe7mr2179922pzg.38.1682604101101; Thu, 27 Apr 2023 07:01:41 -0700 (PDT) Received: from hsinchu02.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id e6-20020a17090a280600b0024bff9dbe6esm2451061pjd.41.2023.04.27.07.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 07:01:40 -0700 (PDT) From: Kito Cheng To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com Cc: Kito Cheng Subject: [PATCH v2] Docs: Add vector register constarint for asm operands Date: Thu, 27 Apr 2023 22:01:07 +0800 Message-Id: <20230427140106.40452-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: `vr`, `vm` and `vd` constarint for vector register constarint, those 3 constarint has implemented on LLVM as well. gcc/ChangeLog: * doc/md.texi (RISC-V): Add vr, vm, vd constarint. --- V2 changes: - Drop unrelated changes. --- gcc/doc/md.texi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 07bf8bdebffb..cc4a93a87638 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3535,6 +3535,15 @@ An address that is held in a general-purpose register. @item S A constraint that matches an absolute symbolic address. +@item vr +A vector register (if available).. + +@item vd +A vector register, excluding v0 (if available). + +@item vm +A vector register, only v0 (if available). + @end table @item RX---@file{config/rx/constraints.md} -- 2.39.2