From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x642.google.com (mail-pl1-x642.google.com [IPv6:2607:f8b0:4864:20::642]) by sourceware.org (Postfix) with ESMTPS id 49C543856090 for ; Thu, 27 Apr 2023 16:24:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 49C543856090 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x642.google.com with SMTP id d9443c01a7336-1a68f2345c5so67982865ad.2 for ; Thu, 27 Apr 2023 09:24:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682612661; x=1685204661; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JszsntAIyeAGykGBRUfRjYENXaFzUL1saHgV7Mp/d2w=; b=LNVLSXvuGR9Wz8a8ccqXYyINn6nihUTHzjksTJZHbfuV9zKL4I9Jfgwv1OPkOTS9im yiuCW5kh/3DysTxo0Kv4fFMoqiAnoYuI3F1fUAyxzJJwbCR2i7JqgAWy01wmf03YapPk RI09WZhpheZn/mFPEavGNbVlttJ1UOIylg3ID2+34RfPJGrWMcg3jXqgsGVwBU9uP6ZM lty/kdVLuxWjkNEYIVOYOqgNz5m5eNpSSsA3Z/0VAi05SkomFxsnDJ8bLKB32ZC8Uur0 bUl+1pHEKF1S7UIwjTc6cQYtbmgY/NVHDYPo4VvWK803BJt7Sfhk0SrvFDrBfu7frV/3 vaiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682612661; x=1685204661; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JszsntAIyeAGykGBRUfRjYENXaFzUL1saHgV7Mp/d2w=; b=JZlqTGK3J7bhVVeqCqm3sn/E2NWtb4wZ0eUOE9EcVllW9xw7L6lKVPRnYuC6yXuny+ e+VKSe3MsUIGXWC21qWjZEBXkdQ6xmOrEnPup8YrVI+yYPH+RfQuh9UiOWc7oi1f5V5f ZRDBSpn1SniaAmfhOCXL6JC5sepN7PaJmeTrS5UTgF/zza9lKddLWSqq3iPf8hFsyzDB 6dAd6xMwQYdmSvsbHXwITGFjHpnptNyfmzy/D8Hgx+ny1xzQVWY5VPYHXWuJNbMTXCsC vENL7dliHbqGMSdCrfzYsmDBiHpslYNO9fVKOFx4nFj/hC6o3MC294tZqLVA3n3CgaNT cgDA== X-Gm-Message-State: AC+VfDwnWGg2+jFjQ9EH9PH/V/ZjeekVut9iESnjCQg/ZGQo/odTLKua MSbskbXqV4pdstq7M+LdObRDU3Z+GLhx7bGP93xPtkk/WMs= X-Google-Smtp-Source: ACHHUZ5jaFKhA4yOq7V98b9Rv45owBQEd+09iNokAbe50Bof+dN6LSvCU1infrIBZu5x1aVkEPJWwg== X-Received: by 2002:a17:903:2346:b0:1a6:a8e5:9240 with SMTP id c6-20020a170903234600b001a6a8e59240mr2515706plh.4.1682612661233; Thu, 27 Apr 2023 09:24:21 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id n19-20020a170902969300b001a6db2bef16sm11815906plp.303.2023.04.27.09.24.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 09:24:20 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 09/11] RISC-V: Weaken mem_thread_fence Date: Thu, 27 Apr 2023 09:22:59 -0700 Message-Id: <20230427162301.1151333-10-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This change brings atomic fences in line with table A.6 of the ISA manual. Relax mem_thread_fence according to the memmodel given. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/sync.md (mem_thread_fence_1): Change fence depending on the given memory model. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Consolidate tests in [PATCH v3 10/10] * Remove helper functions --- gcc/config/riscv/sync.md | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 3e6345e83a3..ba132d8a1ce 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -45,14 +45,24 @@ DONE; }) -;; Until the RISC-V memory model (hence its mapping from C++) is finalized, -;; conservatively emit a full FENCE. (define_insn "mem_thread_fence_1" [(set (match_operand:BLK 0 "" "") (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (match_operand:SI 1 "const_int_operand" "")] ;; model "" - "fence\tiorw,iorw") + { + enum memmodel model = (enum memmodel) INTVAL (operands[1]); + model = memmodel_base (model); + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw"; + else if (model == MEMMODEL_ACQ_REL) + return "fence.tso"; + else if (model == MEMMODEL_ACQUIRE) + return "fence\tr,rw"; + else if (model == MEMMODEL_RELEASE) + return "fence\trw,w"; + } + [(set (attr "length") (const_int 4))]) ;; Atomic memory operations. -- 2.34.1