From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x443.google.com (mail-pf1-x443.google.com [IPv6:2607:f8b0:4864:20::443]) by sourceware.org (Postfix) with ESMTPS id 4CAA83854144 for ; Thu, 27 Apr 2023 16:24:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4CAA83854144 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pf1-x443.google.com with SMTP id d2e1a72fcca58-63b64a32fd2so10835427b3a.2 for ; Thu, 27 Apr 2023 09:24:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682612663; x=1685204663; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RRuZrOOs3faWx9Jun4Te3diKDc/iKDLt6SwONFdl680=; b=shtylZst4+pgHNFHWnbF8YnQhsV4ioCv4GwYSEzCw4yEfK2VlyzP73eE4QM8Th13mC 3AXx2MOwe2l3gcGNpYxbdHgzEePI9rHK2w7EpjnuJRPvMfDFS5blu0L8BjQutYnU0C4X QHPh4O17wW4srsvyOXFWZYOiSUhn1M+de6gz9XqwdDF1c36LGorcl8HTUna0yk7Aa0Tq JZQcJdwEJnSrXu+AL3XJZTbbeQW9e0ggRBLSpfBvXnCx3LwlM3/0wROaBzCjSDY8QOyr mi8fvqD3yedps6qZuILtFW9Gw9ELLkPwDnkF8Mf90raGdszUJmk0h7wrE+fgPCM812TE DfLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682612663; x=1685204663; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RRuZrOOs3faWx9Jun4Te3diKDc/iKDLt6SwONFdl680=; b=bEmIstkpL+V7zdU3V1LBZwoPEXbvzmQPAAVkZZHvskX8fh/igL988WoRyAg6kEe23N zgSkmFvUBA0NWl9AruciEZ5d79Mo5GlyVhYq/QcIEzIdwS1r1q9ECQACIuYNnvPLYhuM NBheyyL1vQzGdHqOOxgX44ik5CFGYfbWT36xrFexnkYsfP38dIisaJLM1X2E4atbJv7G YlAiE8ZGVxH7Sv8VQpKNAh5w0lUVucaQB4pVg6tZGdGXRPvYQDqAjZ5vwJNs6XNX+EUp ftb50uFyOiyqF5+exbO0N20q3kcb0YcwdczswE4mwRG7a4JRiVTBacPd5qkpGCaTnh+7 yy5w== X-Gm-Message-State: AC+VfDxs9q7j6gzeoZ8okIkmiilEp25DcU+ArQqG4Q2hvM5lmYKw0hBK sKTOgk6mjNlaf+7o/uiMBUXW1iDuLPU5wz4msGlQlLPieiY= X-Google-Smtp-Source: ACHHUZ49xp/nQzWKixOG7ET/iq9wXNwvTzYgZ/aTpy8WYZ1sh8N5HFY61/NEBcX+ASHcANY2QGEiPQ== X-Received: by 2002:a17:903:4051:b0:1a5:1586:7761 with SMTP id n17-20020a170903405100b001a515867761mr1705762pla.36.1682612663165; Thu, 27 Apr 2023 09:24:23 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id n19-20020a170902969300b001a6db2bef16sm11815906plp.303.2023.04.27.09.24.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 09:24:22 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 10/11] RISC-V: Weaken atomic loads Date: Thu, 27 Apr 2023 09:23:00 -0700 Message-Id: <20230427162301.1151333-11-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This change brings atomic loads in line with table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/sync.md (atomic_load): Implement atomic load mapping. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/sync.md | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index ba132d8a1ce..6e7c762ac57 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -26,6 +26,7 @@ UNSPEC_SYNC_OLD_OP_SUBWORD UNSPEC_SYNC_EXCHANGE UNSPEC_SYNC_EXCHANGE_SUBWORD + UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER ]) @@ -66,8 +67,31 @@ ;; Atomic memory operations. -;; Implement atomic stores with conservative fences. Fall back to fences for -;; atomic loads. +(define_insn "atomic_load" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "TARGET_ATOMIC" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw\;" + "l\t%0,%1\;" + "fence\tr,rw"; + if (model == MEMMODEL_ACQUIRE) + return "l\t%0,%1\;" + "fence\tr,rw"; + else + return "l\t%0,%1"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 12))]) + +;; Implement atomic stores with conservative fences. ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. (define_insn "atomic_store" [(set (match_operand:GPR 0 "memory_operand" "=A") -- 2.34.1