From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by sourceware.org (Postfix) with ESMTPS id 173093856248 for ; Thu, 27 Apr 2023 16:24:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 173093856248 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1a69f686345so67671385ad.2 for ; Thu, 27 Apr 2023 09:24:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682612656; x=1685204656; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bNjSgMTTHLV0g1Ugg2ndTxjKWJO/vLcHLnGM5M4SXmU=; b=19osVDk5TFg6tB+U3Q0eYb7Z0YBWR4Lz4gYp8OTzTVb2aAsaYCPTLzlledfJSYVqAo 44d5MnUI4igEC9RcOdhtbnRyXmtkrpY+/ZR1x7I7e23VdXAlN+23rAlvRUD/pgxO7MH/ lcRjwuCZ550ZdV55q1NBL7BByLvPYL5A0i7/UyLhf5MNW5zvc8nH5qbEchN76PkynePg wouPxZYZ2oDxYk9AT7D4WQi1meP6eYIYToTK3GtGRZJmUjWGrNDF8gq0tyEmRzh81yNg 1+Lc/GOJkkONt0slh8DGt7jaQqbkgkq28ESUrD7mhX6ScP6r+gJC+BlG5VAjAN/yvErN /Cgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682612656; x=1685204656; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bNjSgMTTHLV0g1Ugg2ndTxjKWJO/vLcHLnGM5M4SXmU=; b=hyTSbvJUxsE0+9epYWTVWQwbPOHCPYevQsyqlPUds4WyHJ4hC+j4z31QoApiutBKKa A6vSwhXgIY/crMFBc3W9o3hnrj4qHTww8kUPY1DADGxkpeygIFhFV7lI1PSX20NWBpD8 OXFIsVT7yNMv1glMayQjoZSIHGdviXRLd59+uKWDOAgYoyj8p8FltKV4NBAMZAWJFQW0 dWwCvhXYQ4Kr/xoi/5YaqJbCPcLhZY38LVRaQ5j+/26pzuTlORh9PTpEroeI5XWSh4Lw 7MY8w0OrwboKKUsIy4B6ilcVU9Dwor2c8uJegDuoqHlvsgrTsgfB+QA9yy3J8ykEjCHF lYBQ== X-Gm-Message-State: AC+VfDw52wGlK80Ud5lY8GB0i8bcy3/xOtmqxE6BGmcvyuaf+aNFhHd9 efQ2QcXWQnBl/Ydg2UIHZ329XSTMUAFoPsnfJzri2TO6 X-Google-Smtp-Source: ACHHUZ76jgYYUYJh1XAm824pb4+9wLdkFRnodhVzN4BIN6sAdaeSQ3Kmwl+90i07iqBJnQ5XKNJ+bA== X-Received: by 2002:a17:902:868a:b0:1a6:9f09:866d with SMTP id g10-20020a170902868a00b001a69f09866dmr2097789plo.61.1682612656039; Thu, 27 Apr 2023 09:24:16 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id n19-20020a170902969300b001a6db2bef16sm11815906plp.303.2023.04.27.09.24.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 09:24:15 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 05/11] RISC-V: Add AMO release bits Date: Thu, 27 Apr 2023 09:22:55 -0700 Message-Id: <20230427162301.1151333-6-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch sets the relevant .rl bits on amo operations. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/riscv.cc (riscv_print_operand): change behavior of %A to include release bits. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 02eb5125ac1..d46781d8981 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4503,8 +4503,13 @@ riscv_print_operand (FILE *file, rtx op, int letter) break; case 'A': - if (riscv_memmodel_needs_amo_acquire (model)) + if (riscv_memmodel_needs_amo_acquire (model) + && riscv_memmodel_needs_release_fence (model)) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) fputs (".aq", file); + else if (riscv_memmodel_needs_release_fence (model)) + fputs (".rl", file); break; case 'F': -- 2.34.1