From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by sourceware.org (Postfix) with ESMTPS id 7539B385735A for ; Thu, 27 Apr 2023 16:24:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7539B385735A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x644.google.com with SMTP id d9443c01a7336-1a68d61579bso65780255ad.1 for ; Thu, 27 Apr 2023 09:24:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682612657; x=1685204657; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Fkgy1RpPD1W3gIeYbyfMEFXSyb13FWzwkogasS4gr10=; b=kOnEh29KgXdKALWhNxlywil5NdFguC+h9g1WFKJmblDieeRe7VlJJK1NBNlfW7kSW3 DB3hRG1fGDZZdUf1vjUqZxpp5Uqho6ErLwGblYc7c6PtNrWjZzsfgX5ahjuIZFHGFTpl mfFTAHZZa64oqv+PmcR9tODwGzAY8xTqS+Up6BM1H42GQYB1jrHQeg8bL4MmcBzJHWMC XbudEqt6mslAdPc6A3JwGOQriUDIbw7YyaUne7B2xXqOzFfGKYITW4+HoQqWgMUazaoc ybqaaVIpq7/r3dcCewMoqDhSOo3+VHDhENWckWqnXXMWjvhIGKvuArQEkXJdVPEYWx8r SFzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682612657; x=1685204657; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Fkgy1RpPD1W3gIeYbyfMEFXSyb13FWzwkogasS4gr10=; b=URx2sKw58hJZ7rOksWerS3ivL5rByFm7N/h4o8Gpl9FMH/4CJaoc3hwslZborZxTMD Ghy5PldsGiA9JW+fnP3FO+8W8xhQJELzbUm5yJQxS/zA1wGY2Xrj6v/nIKHSBUN2P9Z8 2hW0FjDhYkK36q/+kCFGSFtzWPtGfcZaQQM37hmx3pQrv+e/OAO03UiJGwGXPfK6aUWR ac+ZBmgYpVDygRgb0DJ3twiTbnuonnT3Fdld+dqvCPUGEHwAsrH/Ah5pi4+TiU1+2sSy hDYWhb8ALPhepii7IBm3HDmUBae3xHHLwHn9HLPQowL7wTQVJzP3JE32DHxJaTgnhKCW AbqA== X-Gm-Message-State: AC+VfDzAu1kUIEeeAbC+U7J/Itoc44TFAgDLn2mpYlD4yivG9n4elKDB KjQv3pPMnIr+I3ThvH3ycQBUAn1JAglutKqxMch21vSOHTA= X-Google-Smtp-Source: ACHHUZ5OJ/jLPy0D1djMtyCah6+GXxT27pFqDPtzqpJBOjZTPsN/byN/nro9yHfmBBtRuucRgOBlbA== X-Received: by 2002:a17:902:f684:b0:1a9:20d6:3c3f with SMTP id l4-20020a170902f68400b001a920d63c3fmr2296358plg.55.1682612657393; Thu, 27 Apr 2023 09:24:17 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id n19-20020a170902969300b001a6db2bef16sm11815906plp.303.2023.04.27.09.24.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 09:24:17 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 06/11] RISC-V: Strengthen atomic stores Date: Thu, 27 Apr 2023 09:22:56 -0700 Message-Id: <20230427162301.1151333-7-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This change makes atomic stores strictly stronger than table A.6 of the ISA manual. This mapping makes the overall patchset compatible with table A.7 as well. 2023-04-27 Patrick O'Neill PR 89835 gcc/ChangeLog: * config/riscv/sync.md: gcc/testsuite/ChangeLog: * gcc.target/riscv/pr89835.c: New test. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/sync.md | 21 ++++++++++++++++++--- gcc/testsuite/gcc.target/riscv/pr89835.c | 9 +++++++++ 2 files changed, 27 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr89835.c diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 5620d6ffa58..1acb78a9ae4 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -56,7 +56,9 @@ ;; Atomic memory operations. -;; Implement atomic stores with amoswap. Fall back to fences for atomic loads. +;; Implement atomic stores with conservative fences. Fall back to fences for +;; atomic loads. +;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. (define_insn "atomic_store" [(set (match_operand:GPR 0 "memory_operand" "=A") (unspec_volatile:GPR @@ -64,9 +66,22 @@ (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "TARGET_ATOMIC" - "%F2amoswap.%A2 zero,%z1,%0" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,w\;" + "s\t%z1,%0\;" + "fence\trw,rw"; + if (model == MEMMODEL_RELEASE) + return "fence\trw,w\;" + "s\t%z1,%0"; + else + return "s\t%z1,%0"; + } [(set_attr "type" "atomic") - (set (attr "length") (const_int 8))]) + (set (attr "length") (const_int 12))]) (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") diff --git a/gcc/testsuite/gcc.target/riscv/pr89835.c b/gcc/testsuite/gcc.target/riscv/pr89835.c new file mode 100644 index 00000000000..ab190e11b60 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr89835.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that relaxed atomic stores use simple store instuctions. */ +/* { dg-final { scan-assembler-not "amoswap" } } */ + +void +foo(int bar, int baz) +{ + __atomic_store_n(&bar, baz, __ATOMIC_RELAXED); +} -- 2.34.1