From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 718453858C50 for ; Sat, 29 Apr 2023 13:32:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 718453858C50 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682775176; x=1714311176; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WCaj+I3lb4v8LJm7QTtkbd/bP1vLHlvBgJgguxCqraI=; b=DPm+7v/hbMp7D7UaWxMKruhM55Uak7Tu3oY2RWM8bKg36YlM98IKLEFU nwxvuzaI5PlE5MUBWT2aL6G0dPimnKITOidlxA5dcsLwgAhYfuZxyWVnj +CBrg5Q14PzLC5t4EI/79RqNDVHqpnFk68u/USNkmioZ+9NuG9fsDMZNJ yCHRl1zZwYfrxpZSK2KRdTKDaTt1jMGcE3mSP9Vrp+MwWbIirm2rq4ezY yRHFhBA2tMxwyDPZrv6UzfW9ziRDP//ZSRB49UPHRn/XDhPeGxN3mtjXu 0rWiKWgKl4t2Z8WlP/5vOqWhqlaffdkKkhIXYlGel8u7r4wI2wivug2X0 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10695"; a="345397845" X-IronPort-AV: E=Sophos;i="5.99,237,1677571200"; d="scan'208";a="345397845" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2023 06:32:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10695"; a="697928411" X-IronPort-AV: E=Sophos;i="5.99,237,1677571200"; d="scan'208";a="697928411" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga007.fm.intel.com with ESMTP; 29 Apr 2023 06:32:52 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 968E7100780E; Sat, 29 Apr 2023 21:32:51 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com, jeffreyalaw@gmail.com Subject: [PATCH v2] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET Date: Sat, 29 Apr 2023 21:32:50 +0800 Message-Id: <20230429133250.3789188-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230428152102.1653600-1-pan2.li@intel.com> References: <20230428152102.1653600-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li When some RVV integer compare operators act on the same vector registers without mask. They can be simplified to VMSET. This PATCH allow the eq, le, leu, ge, geu to perform such kind of the simplification by adding vector bool support in relational_result of the simplify rtx. Given we have: vbool1_t test_shortcut_for_riscv_vmseq_case_0(vint8m8_t v1, size_t vl) { return __riscv_vmseq_vv_i8m8_b1(v1, v1, vl); } Before this patch: vsetvli zero,a2,e8,m8,ta,ma vl8re8.v v8,0(a1) vmseq.vv v8,v8,v8 vsetvli a5,zero,e8,m8,ta,ma vsm.v v8,0(a0) ret After this patch: vsetvli zero,a2,e8,m8,ta,ma vmset.m v1 <- optimized to vmset.m vsetvli a5,zero,e8,m8,ta,ma vsm.v v1,0(a0) ret As above, we may have one instruction eliminated and require less vector registers. gcc/ChangeLog: * machmode.h (VECTOR_BOOL_MODE_P): Add new predication macro. * simplify-rtx.cc (relational_result): Add vector bool support. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Adjust test check condition. Signed-off-by: Pan Li --- gcc/machmode.h | 4 ++++ gcc/simplify-rtx.cc | 4 ++++ .../riscv/rvv/base/integer_compare_insn_shortcut.c | 6 +----- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/gcc/machmode.h b/gcc/machmode.h index f1865c1ef42..5fbece0042f 100644 --- a/gcc/machmode.h +++ b/gcc/machmode.h @@ -134,6 +134,10 @@ extern const unsigned char mode_class[NUM_MACHINE_MODES]; || GET_MODE_CLASS (MODE) == MODE_VECTOR_ACCUM \ || GET_MODE_CLASS (MODE) == MODE_VECTOR_UACCUM) +/* Nonzero if MODE is a vector bool mode. */ +#define VECTOR_BOOL_MODE_P(MODE) \ + (GET_MODE_CLASS (MODE) == MODE_VECTOR_BOOL) + /* Nonzero if MODE is a scalar integral mode. */ #define SCALAR_INT_MODE_P(MODE) \ (GET_MODE_CLASS (MODE) == MODE_INT \ diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index d4aeebc7a5f..12aba4c4b05 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -2535,6 +2535,10 @@ relational_result (machine_mode mode, machine_mode cmp_mode, rtx res) { if (res == const0_rtx) return CONST0_RTX (mode); + + if (VECTOR_BOOL_MODE_P (mode) && res == const1_rtx) + return CONSTM1_RTX (mode); + #ifdef VECTOR_STORE_FLAG_VALUE rtx val = VECTOR_STORE_FLAG_VALUE (mode); if (val == NULL_RTX) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c index 8954adad09d..1bca8467a16 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c @@ -283,9 +283,5 @@ vbool64_t test_shortcut_for_riscv_vmsgeu_case_6(vuint8mf8_t v1, size_t vl) { return __riscv_vmsgeu_vv_u8mf8_b64(v1, v1, vl); } -/* { dg-final { scan-assembler-times {vmseq\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ -/* { dg-final { scan-assembler-times {vmsle\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ -/* { dg-final { scan-assembler-times {vmsleu\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ -/* { dg-final { scan-assembler-times {vmsge\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ -/* { dg-final { scan-assembler-times {vmsgeu\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ /* { dg-final { scan-assembler-times {vmclr\.m\sv[0-9]} 35 } } */ +/* { dg-final { scan-assembler-times {vmset\.m\sv[0-9]} 35 } } */ -- 2.34.1