From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-vi1eur04on2085.outbound.protection.outlook.com [40.107.8.85]) by sourceware.org (Postfix) with ESMTPS id 8D54F3857011 for ; Wed, 3 May 2023 14:38:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8D54F3857011 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0pckzxm4RW/EIrd3uPx7iWbthl5mvL0S0tYWm/A1ZM4=; b=GOQTX3oMKR6WnR+roZp6Q2Xe/3aytb0vnABcMHAhI91TIthZaco8ze9OlCsg68eDgUUUYLGksUUn8TA9JF9jZOzgz/PFoIlT3qvERVML7dYnSAIBFYCT8tk2L76EYQZLWpsjC27hKOqzW+HgMFeKjsIU4KLpgrHQgFgC8MatxSc= Received: from DB9PR02CA0020.eurprd02.prod.outlook.com (2603:10a6:10:1d9::25) by DB9PR08MB7398.eurprd08.prod.outlook.com (2603:10a6:10:372::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.21; Wed, 3 May 2023 14:37:55 +0000 Received: from DBAEUR03FT054.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:1d9:cafe::80) by DB9PR02CA0020.outlook.office365.com (2603:10a6:10:1d9::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.21 via Frontend Transport; Wed, 3 May 2023 14:37:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT054.mail.protection.outlook.com (100.127.142.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.20 via Frontend Transport; Wed, 3 May 2023 14:37:54 +0000 Received: ("Tessian outbound 3a01b65b5aad:v136"); Wed, 03 May 2023 14:37:54 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 04075fba958288d1 X-CR-MTA-TID: 64aa7808 Received: from 6c1604fa4a15.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id F2633256-6ED9-467D-8D8C-665570D65BED.1; Wed, 03 May 2023 14:37:48 +0000 Received: from EUR04-HE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 6c1604fa4a15.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Wed, 03 May 2023 14:37:48 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BYdaQRc2hP6gqYo1yi9vb7pMjS2bL8V2xdUzLYW+GG40WUgjZ1aEWWT1T1nvujCVGzJnSFOXg9F2IGmw8CtgUsT9Qv/13ysXD3ubwNyDPke4tl6j+bJ9yvT4fB8gfVZq3LoqjWfCNE+b2sNBLnP8fA60MdByPtZlxUDPMvN37+6WQv9AFbFga0WOs7zpVoAkRwjVZTdwTf18xk/4vxYmW2lyLfO4/V7JXEr9taQR6eDZSf5cheoee8AfRDs1SKKHcS0wj5JUoBQh3n/vYFpj+gqact1xzwmxCLAuTfqLJhqMXyQo9VKKkm1ufg2ZHrZpxhhbSUVcaL/OaiJ10bIPsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0pckzxm4RW/EIrd3uPx7iWbthl5mvL0S0tYWm/A1ZM4=; b=mRHCYM+FIMEk6OaP2KsxzzPu458bTqStmmRR2w9vBUfOcttgBSKheZ2Y2zbV29X89BSiF6wt7414gviKPrX1ePJdOlMP3yVoXGDmK1vCSQMwD2IulA6eUikHhGJa1ImMfv+LDuasSUJjI/OyXYfsLvwfaKr2S5X6o5I11gB0wmaB7wB+NOzkDzhSfL9jQqQf+f5yQh79DLuveGmm9fSqWGAkqo3JwWVV67GtURrbrUkzYlc/AtCN9remd7+Nymo4yQv233i2+TY9pk3StygqYOJj7jUM0LfG0SZVQphCl6b8q5L0/is/14Y3buLDTXwwTlmGTGlljtMC1RWFhyMiRg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0pckzxm4RW/EIrd3uPx7iWbthl5mvL0S0tYWm/A1ZM4=; b=GOQTX3oMKR6WnR+roZp6Q2Xe/3aytb0vnABcMHAhI91TIthZaco8ze9OlCsg68eDgUUUYLGksUUn8TA9JF9jZOzgz/PFoIlT3qvERVML7dYnSAIBFYCT8tk2L76EYQZLWpsjC27hKOqzW+HgMFeKjsIU4KLpgrHQgFgC8MatxSc= Received: from AM5PR0601CA0033.eurprd06.prod.outlook.com (2603:10a6:203:68::19) by PA4PR08MB5936.eurprd08.prod.outlook.com (2603:10a6:102:f1::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.22; Wed, 3 May 2023 14:37:42 +0000 Received: from AM7EUR03FT041.eop-EUR03.prod.protection.outlook.com (2603:10a6:203:68:cafe::15) by AM5PR0601CA0033.outlook.office365.com (2603:10a6:203:68::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6340.31 via Frontend Transport; Wed, 3 May 2023 14:37:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT041.mail.protection.outlook.com (100.127.140.233) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6363.21 via Frontend Transport; Wed, 3 May 2023 14:37:42 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 3 May 2023 14:37:41 +0000 Received: from e129018.arm.com (10.57.22.152) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Wed, 3 May 2023 14:37:40 +0000 From: Christophe Lyon To: , , , CC: Christophe Lyon Subject: [PATCH v2 03/22] arm: [MVE intrinsics] Rework vreinterpretq Date: Wed, 3 May 2023 16:37:09 +0200 Message-ID: <20230503143709.50270-1-christophe.lyon@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <132f5b97-20d1-6a89-6f70-aa584b7e5eca@arm.com> References: <132f5b97-20d1-6a89-6f70-aa584b7e5eca@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT041:EE_|PA4PR08MB5936:EE_|DBAEUR03FT054:EE_|DB9PR08MB7398:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f7e9ab1-50d2-4013-df66-08db4be3fb55 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: RxiCicO1m0ShSfX7eNDfZ9eFFqXMmeOE3AqHVA5ovEHct/0vZM7XIFtdtnNG+lHE17NO3a6donbgtO4aIIyl/zIoddI4uKZM9MSLRaPaPOpJsSO1VH39n5+axEDOajVCXHOvjNaNYhXunF8naB3iy9MFQdBfjusDrszuOtNPuRBeBe7+K/7QQTnkxKHAIcEIreBV3Az9gKqwlYIXFaxTPkgO/aUHd0amb6oZV9inX5J6QAndvvr96jUpitQ1GI7GTX50ETayULzsNzAbBbqzySOz0V8uYEyq3Pdt0/7mx5IO6rRskDQO3r5oUf4cAG/9sazIXpomx71XW6FceTSpDMhrw1pLymleleRP/aVpHiw2AXEqVpoB+Hgh/78BrnJuxqu+7ygzikN0WaKy7KtvOgyFH6hl/M60PVJ7yx7ddDEM9k10/7ZbBb4PP/xBjfDV377qyFZFHOJrZTN/q91l6WZu0sS2BghY5DpQRrOmubiSalTsFCRB1dbtrTrblBhrA/Wk0/9C/WpLkCdGhRe+k0c7T6Slo46sGRUteMxLQbEYf+0hr1Crck7rt9S5xKv0Gr95LsLE5hLlFQF7ED3cKxGRytHdpCtMfc214MsxDP6muCaNCneFV3KoyYUMBfEXQIdO34YOaDcXjP2R8V0h9XXohvoVxnu8K70+FwQV2a7CzTQAzAygad+CE6O6q+VvMbGaF6fKVOjftUglVkRejCdak0tBkvt2f8xkDFx05OlXJvmGlXN04MReT0+TJG5ZrIkyVOpMw2wasJ1+CSg65enM9ERxMkZruhN8NGNjHp4= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(39860400002)(346002)(396003)(136003)(451199021)(46966006)(40470700004)(36840700001)(47076005)(186003)(2906002)(30864003)(336012)(426003)(2616005)(84970400001)(83380400001)(110136005)(44832011)(36860700001)(1076003)(26005)(34020700004)(81166007)(70586007)(70206006)(356005)(478600001)(40460700003)(5660300002)(82740400003)(40480700001)(8936002)(8676002)(41300700001)(36756003)(6666004)(86362001)(6636002)(7696005)(316002)(82310400005)(4326008)(36900700001)(559001)(579004);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB5936 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT054.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: a4d604bc-2a67-4d73-f6b0-08db4be3f3e2 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nz6XyLbkcfAUkW/vGXJDJSlG/tbmYrTvGSy2q3Ak2I1fimssGV9459W33Axy+GXHxXK7Ceqg+ElRbu7dFrRnFDyyYVDtGp6tvOjjQk9PCt90w3+kxykyClMBIbT1fwTTwjZzwFQDOVTWhu1QJP1pgBvUppZN2zSrMOyaIzfxUMvLI4du77GtTe+w1rBFd4EibZaZ3FQDb416RgvQ+JC7SSL67L/Geg3UqoRrlJfnCriZE/WQEb7COa1wjvxLFz/UcFwbdf7Rc5KlIC8Yk2+JacbZVRLFs8xsPVlFcx0nP7Ot0LFU3/8ppxG+ln2dMwFvs6NWhFtuCSccCvBbksSJ2iGMFcCKoPnnvjWhB059ZJGGgoNQIMPOhdSC6A0FNw7AVLG+wizdU18i5JBl81lbiX8t1hID9gt0YyvQhn3UYCaOwhLNc/FsjE7sC0lGqk1QHvUlHvoq06R6lo7ewbntq2YRyNdiiHyLRK+fllqR4aUTvKNY1BE36WuIQusgfyu0EYRJ4jjBiK53d4T/OMaE5iftFSSJfKrgF3/HRTxxSQntJSWE5jVMr0503tLQC+aRwP2wj/5e5cyTI3HH+yZ6jTTfdAH2bWV5M4WqOfFzN7QfZzzb4d8RKuqHoXuxxSNpLHjw0AiBhxhnaJzYaR6oR7QMdpzT66nFbAZTHTtemXA6cyf22OtQ1NYhLAWquF3pQJvFNpbyUt236fJ4NsfbUb9lq6F5Sk1HO4wk4AX60FHXXZFxZYKYkBT9cGtyEaisj1rIRr3dmJXt5fWgHBlwdQ== X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230028)(4636009)(396003)(376002)(136003)(346002)(39860400002)(451199021)(46966006)(36840700001)(40470700004)(84970400001)(36860700001)(336012)(36756003)(40460700003)(81166007)(5660300002)(2906002)(30864003)(44832011)(40480700001)(316002)(86362001)(70206006)(41300700001)(8676002)(8936002)(70586007)(4326008)(82310400005)(6636002)(34020700004)(83380400001)(426003)(47076005)(26005)(1076003)(478600001)(7696005)(110136005)(186003)(82740400003)(6666004)(2616005)(559001)(579004);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2023 14:37:54.9425 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f7e9ab1-50d2-4013-df66-08db4be3fb55 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT054.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB7398 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch implements vreinterpretq using the new MVE intrinsics framework. The old definitions for vreinterpretq are removed as a consequence. 2022-09-08 Murray Steele Christophe Lyon gcc/ * config/arm/arm-mve-builtins-base.cc (vreinterpretq_impl): New class. * config/arm/arm-mve-builtins-base.def: Define vreinterpretq. * config/arm/arm-mve-builtins-base.h (vreinterpretq): New declaration. * config/arm/arm-mve-builtins-shapes.cc (parse_element_type): New function. (parse_type): Likewise. (parse_signature): Likewise. (build_one): Likewise. (build_all): Likewise. (overloaded_base): New struct. (unary_convert_def): Likewise. * config/arm/arm-mve-builtins-shapes.h (unary_convert): Declare. * config/arm/arm-mve-builtins.cc (TYPES_reinterpret_signed1): New macro. (TYPES_reinterpret_unsigned1): Likewise. (TYPES_reinterpret_integer): Likewise. (TYPES_reinterpret_integer1): Likewise. (TYPES_reinterpret_float1): Likewise. (TYPES_reinterpret_float): Likewise. (reinterpret_integer): New. (reinterpret_float): New. (handle_arm_mve_h): Register builtins. * config/arm/arm_mve.h (vreinterpretq_s16): Remove. (vreinterpretq_s32): Likewise. (vreinterpretq_s64): Likewise. (vreinterpretq_s8): Likewise. (vreinterpretq_u16): Likewise. (vreinterpretq_u32): Likewise. (vreinterpretq_u64): Likewise. (vreinterpretq_u8): Likewise. (vreinterpretq_f16): Likewise. (vreinterpretq_f32): Likewise. (vreinterpretq_s16_s32): Likewise. (vreinterpretq_s16_s64): Likewise. (vreinterpretq_s16_s8): Likewise. (vreinterpretq_s16_u16): Likewise. (vreinterpretq_s16_u32): Likewise. (vreinterpretq_s16_u64): Likewise. (vreinterpretq_s16_u8): Likewise. (vreinterpretq_s32_s16): Likewise. (vreinterpretq_s32_s64): Likewise. (vreinterpretq_s32_s8): Likewise. (vreinterpretq_s32_u16): Likewise. (vreinterpretq_s32_u32): Likewise. (vreinterpretq_s32_u64): Likewise. (vreinterpretq_s32_u8): Likewise. (vreinterpretq_s64_s16): Likewise. (vreinterpretq_s64_s32): Likewise. (vreinterpretq_s64_s8): Likewise. (vreinterpretq_s64_u16): Likewise. (vreinterpretq_s64_u32): Likewise. (vreinterpretq_s64_u64): Likewise. (vreinterpretq_s64_u8): Likewise. (vreinterpretq_s8_s16): Likewise. (vreinterpretq_s8_s32): Likewise. (vreinterpretq_s8_s64): Likewise. (vreinterpretq_s8_u16): Likewise. (vreinterpretq_s8_u32): Likewise. (vreinterpretq_s8_u64): Likewise. (vreinterpretq_s8_u8): Likewise. (vreinterpretq_u16_s16): Likewise. (vreinterpretq_u16_s32): Likewise. (vreinterpretq_u16_s64): Likewise. (vreinterpretq_u16_s8): Likewise. (vreinterpretq_u16_u32): Likewise. (vreinterpretq_u16_u64): Likewise. (vreinterpretq_u16_u8): Likewise. (vreinterpretq_u32_s16): Likewise. (vreinterpretq_u32_s32): Likewise. (vreinterpretq_u32_s64): Likewise. (vreinterpretq_u32_s8): Likewise. (vreinterpretq_u32_u16): Likewise. (vreinterpretq_u32_u64): Likewise. (vreinterpretq_u32_u8): Likewise. (vreinterpretq_u64_s16): Likewise. (vreinterpretq_u64_s32): Likewise. (vreinterpretq_u64_s64): Likewise. (vreinterpretq_u64_s8): Likewise. (vreinterpretq_u64_u16): Likewise. (vreinterpretq_u64_u32): Likewise. (vreinterpretq_u64_u8): Likewise. (vreinterpretq_u8_s16): Likewise. (vreinterpretq_u8_s32): Likewise. (vreinterpretq_u8_s64): Likewise. (vreinterpretq_u8_s8): Likewise. (vreinterpretq_u8_u16): Likewise. (vreinterpretq_u8_u32): Likewise. (vreinterpretq_u8_u64): Likewise. (vreinterpretq_s32_f16): Likewise. (vreinterpretq_s32_f32): Likewise. (vreinterpretq_u16_f16): Likewise. (vreinterpretq_u16_f32): Likewise. (vreinterpretq_u32_f16): Likewise. (vreinterpretq_u32_f32): Likewise. (vreinterpretq_u64_f16): Likewise. (vreinterpretq_u64_f32): Likewise. (vreinterpretq_u8_f16): Likewise. (vreinterpretq_u8_f32): Likewise. (vreinterpretq_f16_f32): Likewise. (vreinterpretq_f16_s16): Likewise. (vreinterpretq_f16_s32): Likewise. (vreinterpretq_f16_s64): Likewise. (vreinterpretq_f16_s8): Likewise. (vreinterpretq_f16_u16): Likewise. (vreinterpretq_f16_u32): Likewise. (vreinterpretq_f16_u64): Likewise. (vreinterpretq_f16_u8): Likewise. (vreinterpretq_f32_f16): Likewise. (vreinterpretq_f32_s16): Likewise. (vreinterpretq_f32_s32): Likewise. (vreinterpretq_f32_s64): Likewise. (vreinterpretq_f32_s8): Likewise. (vreinterpretq_f32_u16): Likewise. (vreinterpretq_f32_u32): Likewise. (vreinterpretq_f32_u64): Likewise. (vreinterpretq_f32_u8): Likewise. (vreinterpretq_s16_f16): Likewise. (vreinterpretq_s16_f32): Likewise. (vreinterpretq_s64_f16): Likewise. (vreinterpretq_s64_f32): Likewise. (vreinterpretq_s8_f16): Likewise. (vreinterpretq_s8_f32): Likewise. (__arm_vreinterpretq_f16): Likewise. (__arm_vreinterpretq_f32): Likewise. (__arm_vreinterpretq_s16): Likewise. (__arm_vreinterpretq_s32): Likewise. (__arm_vreinterpretq_s64): Likewise. (__arm_vreinterpretq_s8): Likewise. (__arm_vreinterpretq_u16): Likewise. (__arm_vreinterpretq_u32): Likewise. (__arm_vreinterpretq_u64): Likewise. (__arm_vreinterpretq_u8): Likewise. * config/arm/arm_mve_types.h (__arm_vreinterpretq_s16_s32): Remove. (__arm_vreinterpretq_s16_s64): Likewise. (__arm_vreinterpretq_s16_s8): Likewise. (__arm_vreinterpretq_s16_u16): Likewise. (__arm_vreinterpretq_s16_u32): Likewise. (__arm_vreinterpretq_s16_u64): Likewise. (__arm_vreinterpretq_s16_u8): Likewise. (__arm_vreinterpretq_s32_s16): Likewise. (__arm_vreinterpretq_s32_s64): Likewise. (__arm_vreinterpretq_s32_s8): Likewise. (__arm_vreinterpretq_s32_u16): Likewise. (__arm_vreinterpretq_s32_u32): Likewise. (__arm_vreinterpretq_s32_u64): Likewise. (__arm_vreinterpretq_s32_u8): Likewise. (__arm_vreinterpretq_s64_s16): Likewise. (__arm_vreinterpretq_s64_s32): Likewise. (__arm_vreinterpretq_s64_s8): Likewise. (__arm_vreinterpretq_s64_u16): Likewise. (__arm_vreinterpretq_s64_u32): Likewise. (__arm_vreinterpretq_s64_u64): Likewise. (__arm_vreinterpretq_s64_u8): Likewise. (__arm_vreinterpretq_s8_s16): Likewise. (__arm_vreinterpretq_s8_s32): Likewise. (__arm_vreinterpretq_s8_s64): Likewise. (__arm_vreinterpretq_s8_u16): Likewise. (__arm_vreinterpretq_s8_u32): Likewise. (__arm_vreinterpretq_s8_u64): Likewise. (__arm_vreinterpretq_s8_u8): Likewise. (__arm_vreinterpretq_u16_s16): Likewise. (__arm_vreinterpretq_u16_s32): Likewise. (__arm_vreinterpretq_u16_s64): Likewise. (__arm_vreinterpretq_u16_s8): Likewise. (__arm_vreinterpretq_u16_u32): Likewise. (__arm_vreinterpretq_u16_u64): Likewise. (__arm_vreinterpretq_u16_u8): Likewise. (__arm_vreinterpretq_u32_s16): Likewise. (__arm_vreinterpretq_u32_s32): Likewise. (__arm_vreinterpretq_u32_s64): Likewise. (__arm_vreinterpretq_u32_s8): Likewise. (__arm_vreinterpretq_u32_u16): Likewise. (__arm_vreinterpretq_u32_u64): Likewise. (__arm_vreinterpretq_u32_u8): Likewise. (__arm_vreinterpretq_u64_s16): Likewise. (__arm_vreinterpretq_u64_s32): Likewise. (__arm_vreinterpretq_u64_s64): Likewise. (__arm_vreinterpretq_u64_s8): Likewise. (__arm_vreinterpretq_u64_u16): Likewise. (__arm_vreinterpretq_u64_u32): Likewise. (__arm_vreinterpretq_u64_u8): Likewise. (__arm_vreinterpretq_u8_s16): Likewise. (__arm_vreinterpretq_u8_s32): Likewise. (__arm_vreinterpretq_u8_s64): Likewise. (__arm_vreinterpretq_u8_s8): Likewise. (__arm_vreinterpretq_u8_u16): Likewise. (__arm_vreinterpretq_u8_u32): Likewise. (__arm_vreinterpretq_u8_u64): Likewise. (__arm_vreinterpretq_s32_f16): Likewise. (__arm_vreinterpretq_s32_f32): Likewise. (__arm_vreinterpretq_s16_f16): Likewise. (__arm_vreinterpretq_s16_f32): Likewise. (__arm_vreinterpretq_s64_f16): Likewise. (__arm_vreinterpretq_s64_f32): Likewise. (__arm_vreinterpretq_s8_f16): Likewise. (__arm_vreinterpretq_s8_f32): Likewise. (__arm_vreinterpretq_u16_f16): Likewise. (__arm_vreinterpretq_u16_f32): Likewise. (__arm_vreinterpretq_u32_f16): Likewise. (__arm_vreinterpretq_u32_f32): Likewise. (__arm_vreinterpretq_u64_f16): Likewise. (__arm_vreinterpretq_u64_f32): Likewise. (__arm_vreinterpretq_u8_f16): Likewise. (__arm_vreinterpretq_u8_f32): Likewise. (__arm_vreinterpretq_f16_f32): Likewise. (__arm_vreinterpretq_f16_s16): Likewise. (__arm_vreinterpretq_f16_s32): Likewise. (__arm_vreinterpretq_f16_s64): Likewise. (__arm_vreinterpretq_f16_s8): Likewise. (__arm_vreinterpretq_f16_u16): Likewise. (__arm_vreinterpretq_f16_u32): Likewise. (__arm_vreinterpretq_f16_u64): Likewise. (__arm_vreinterpretq_f16_u8): Likewise. (__arm_vreinterpretq_f32_f16): Likewise. (__arm_vreinterpretq_f32_s16): Likewise. (__arm_vreinterpretq_f32_s32): Likewise. (__arm_vreinterpretq_f32_s64): Likewise. (__arm_vreinterpretq_f32_s8): Likewise. (__arm_vreinterpretq_f32_u16): Likewise. (__arm_vreinterpretq_f32_u32): Likewise. (__arm_vreinterpretq_f32_u64): Likewise. (__arm_vreinterpretq_f32_u8): Likewise. (__arm_vreinterpretq_s16): Likewise. (__arm_vreinterpretq_s32): Likewise. (__arm_vreinterpretq_s64): Likewise. (__arm_vreinterpretq_s8): Likewise. (__arm_vreinterpretq_u16): Likewise. (__arm_vreinterpretq_u32): Likewise. (__arm_vreinterpretq_u64): Likewise. (__arm_vreinterpretq_u8): Likewise. (__arm_vreinterpretq_f16): Likewise. (__arm_vreinterpretq_f32): Likewise. * config/arm/mve.md (@arm_mve_reinterpret): New pattern. * config/arm/unspecs.md: (REINTERPRET): New unspec. gcc/testsuite/ * g++.target/arm/mve.exp: Add general-c++ and general directories. * g++.target/arm/mve/general-c++/nomve_fp_1.c: New test. * g++.target/arm/mve/general-c++/vreinterpretq_1.C: New test. * gcc.target/arm/mve/general-c/nomve_fp_1.c: New test. * gcc.target/arm/mve/general-c/vreinterpretq_1.c: New test. --- gcc/config/arm/arm-mve-builtins-base.cc | 33 + gcc/config/arm/arm-mve-builtins-base.def | 2 + gcc/config/arm/arm-mve-builtins-base.h | 2 + gcc/config/arm/arm-mve-builtins-shapes.cc | 28 + gcc/config/arm/arm-mve-builtins-shapes.h | 8 + gcc/config/arm/arm-mve-builtins.cc | 60 + gcc/config/arm/arm_mve.h | 300 ---- gcc/config/arm/arm_mve_types.h | 1365 +---------------- gcc/config/arm/mve.md | 18 + gcc/config/arm/unspecs.md | 1 + gcc/testsuite/g++.target/arm/mve.exp | 8 +- .../arm/mve/general-c++/nomve_fp_1.c | 15 + .../arm/mve/general-c++/vreinterpretq_1.C | 25 + .../gcc.target/arm/mve/general-c/nomve_fp_1.c | 15 + .../arm/mve/general-c/vreinterpretq_1.c | 25 + 15 files changed, 290 insertions(+), 1615 deletions(-) create mode 100644 gcc/testsuite/g++.target/arm/mve/general-c++/nomve_fp_1.c create mode 100644 gcc/testsuite/g++.target/arm/mve/general-c++/vreinterpretq_1.C create mode 100644 gcc/testsuite/gcc.target/arm/mve/general-c/nomve_fp_1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/general-c/vreinterpretq_1.c diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc index e9f285faf2b..abf6a1e19de 100644 --- a/gcc/config/arm/arm-mve-builtins-base.cc +++ b/gcc/config/arm/arm-mve-builtins-base.cc @@ -38,8 +38,41 @@ using namespace arm_mve; namespace { +/* Implements vreinterpretq_* intrinsics. */ +class vreinterpretq_impl : public quiet +{ + gimple * + fold (gimple_folder &f) const override + { + /* We should punt to rtl if the effect of the reinterpret on + registers does not conform to GCC's endianness model like we do + on aarch64, but MVE intrinsics are not currently supported on + big-endian. For this, we'd need to handle big-endian properly + in the .md file, like we do on aarch64 with + define_insn_and_split "*aarch64_sve_reinterpret". */ + gcc_assert (targetm.can_change_mode_class (f.vector_mode (0), + f.vector_mode (1), + VFP_REGS)); + + /* Otherwise vreinterpret corresponds directly to a VIEW_CONVERT_EXPR + reinterpretation. */ + tree rhs = build1 (VIEW_CONVERT_EXPR, TREE_TYPE (f.lhs), + gimple_call_arg (f.call, 0)); + return gimple_build_assign (f.lhs, VIEW_CONVERT_EXPR, rhs); + } + + rtx + expand (function_expander &e) const override + { + machine_mode mode = e.vector_mode (0); + return e.use_exact_insn (code_for_arm_mve_reinterpret (mode)); + } +}; + } /* end anonymous namespace */ namespace arm_mve { +FUNCTION (vreinterpretq, vreinterpretq_impl,) + } /* end namespace arm_mve */ diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def index d15ba2e23e8..5c0c1b9cee7 100644 --- a/gcc/config/arm/arm-mve-builtins-base.def +++ b/gcc/config/arm/arm-mve-builtins-base.def @@ -18,7 +18,9 @@ . */ #define REQUIRES_FLOAT false +DEF_MVE_FUNCTION (vreinterpretq, unary_convert, reinterpret_integer, none) #undef REQUIRES_FLOAT #define REQUIRES_FLOAT true +DEF_MVE_FUNCTION (vreinterpretq, unary_convert, reinterpret_float, none) #undef REQUIRES_FLOAT diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h index c4d7b750cd5..60e7bd24eda 100644 --- a/gcc/config/arm/arm-mve-builtins-base.h +++ b/gcc/config/arm/arm-mve-builtins-base.h @@ -23,6 +23,8 @@ namespace arm_mve { namespace functions { +extern const function_base *const vreinterpretq; + } /* end namespace arm_mve::functions */ } /* end namespace arm_mve */ diff --git a/gcc/config/arm/arm-mve-builtins-shapes.cc b/gcc/config/arm/arm-mve-builtins-shapes.cc index f20660d8319..d0da0ffef91 100644 --- a/gcc/config/arm/arm-mve-builtins-shapes.cc +++ b/gcc/config/arm/arm-mve-builtins-shapes.cc @@ -338,6 +338,34 @@ struct overloaded_base : public function_shape } }; +/* _t foo_t0[_t1](_t) + + where the target type must be specified explicitly but the source + type can be inferred. + + Example: vreinterpretq. + int16x8_t [__arm_]vreinterpretq_s16[_s8](int8x16_t a) + int32x4_t [__arm_]vreinterpretq_s32[_s8](int8x16_t a) + int8x16_t [__arm_]vreinterpretq_s8[_s16](int16x8_t a) + int8x16_t [__arm_]vreinterpretq_s8[_s32](int32x4_t a) */ +struct unary_convert_def : public overloaded_base<1> +{ + void + build (function_builder &b, const function_group_info &group, + bool preserve_user_namespace) const override + { + b.add_overloaded_functions (group, MODE_none, preserve_user_namespace); + build_all (b, "v0,v1", group, MODE_none, preserve_user_namespace); + } + + tree + resolve (function_resolver &r) const override + { + return r.resolve_unary (); + } +}; +SHAPE (unary_convert) + } /* end namespace arm_mve */ #undef SHAPE diff --git a/gcc/config/arm/arm-mve-builtins-shapes.h b/gcc/config/arm/arm-mve-builtins-shapes.h index 9e353b85a76..04d19a02890 100644 --- a/gcc/config/arm/arm-mve-builtins-shapes.h +++ b/gcc/config/arm/arm-mve-builtins-shapes.h @@ -22,8 +22,16 @@ namespace arm_mve { + /* The naming convention is: + + - to use names like "unary" etc. if the rules are somewhat generic, + especially if there are no ranges involved. */ + namespace shapes { + + extern const function_shape *const unary_convert; + } /* end namespace arm_mve::shapes */ } /* end namespace arm_mve */ diff --git a/gcc/config/arm/arm-mve-builtins.cc b/gcc/config/arm/arm-mve-builtins.cc index b0cceb75ceb..e409a029346 100644 --- a/gcc/config/arm/arm-mve-builtins.cc +++ b/gcc/config/arm/arm-mve-builtins.cc @@ -199,6 +199,52 @@ CONSTEXPR const type_suffix_info type_suffixes[NUM_TYPE_SUFFIXES + 1] = { #define TYPES_signed_32(S, D) \ S (s32) +#define TYPES_reinterpret_signed1(D, A) \ + D (A, s8), D (A, s16), D (A, s32), D (A, s64) + +#define TYPES_reinterpret_unsigned1(D, A) \ + D (A, u8), D (A, u16), D (A, u32), D (A, u64) + +#define TYPES_reinterpret_integer(S, D) \ + TYPES_reinterpret_unsigned1 (D, s8), \ + D (s8, s16), D (s8, s32), D (s8, s64), \ + TYPES_reinterpret_unsigned1 (D, s16), \ + D (s16, s8), D (s16, s32), D (s16, s64), \ + TYPES_reinterpret_unsigned1 (D, s32), \ + D (s32, s8), D (s32, s16), D (s32, s64), \ + TYPES_reinterpret_unsigned1 (D, s64), \ + D (s64, s8), D (s64, s16), D (s64, s32), \ + TYPES_reinterpret_signed1 (D, u8), \ + D (u8, u16), D (u8, u32), D (u8, u64), \ + TYPES_reinterpret_signed1 (D, u16), \ + D (u16, u8), D (u16, u32), D (u16, u64), \ + TYPES_reinterpret_signed1 (D, u32), \ + D (u32, u8), D (u32, u16), D (u32, u64), \ + TYPES_reinterpret_signed1 (D, u64), \ + D (u64, u8), D (u64, u16), D (u64, u32) + +/* { _s8 _s16 _s32 _s64 } x { _s8 _s16 _s32 _s64 } + { _u8 _u16 _u32 _u64 } { _u8 _u16 _u32 _u64 }. */ +#define TYPES_reinterpret_integer1(D, A) \ + TYPES_reinterpret_signed1 (D, A), \ + TYPES_reinterpret_unsigned1 (D, A) + +#define TYPES_reinterpret_float1(D, A) \ + D (A, f16), D (A, f32) + +#define TYPES_reinterpret_float(S, D) \ + TYPES_reinterpret_float1 (D, s8), \ + TYPES_reinterpret_float1 (D, s16), \ + TYPES_reinterpret_float1 (D, s32), \ + TYPES_reinterpret_float1 (D, s64), \ + TYPES_reinterpret_float1 (D, u8), \ + TYPES_reinterpret_float1 (D, u16), \ + TYPES_reinterpret_float1 (D, u32), \ + TYPES_reinterpret_float1 (D, u64), \ + TYPES_reinterpret_integer1 (D, f16), \ + TYPES_reinterpret_integer1 (D, f32), \ + D (f16, f32), D (f32, f16) + /* Describe a pair of type suffixes in which only the first is used. */ #define DEF_VECTOR_TYPE(X) { TYPE_SUFFIX_ ## X, NUM_TYPE_SUFFIXES } @@ -231,6 +277,8 @@ DEF_MVE_TYPES_ARRAY (integer_16_32); DEF_MVE_TYPES_ARRAY (integer_32); DEF_MVE_TYPES_ARRAY (signed_16_32); DEF_MVE_TYPES_ARRAY (signed_32); +DEF_MVE_TYPES_ARRAY (reinterpret_integer); +DEF_MVE_TYPES_ARRAY (reinterpret_float); /* Used by functions that have no governing predicate. */ static const predication_index preds_none[] = { PRED_none, NUM_PREDS }; @@ -253,6 +301,14 @@ static const predication_index preds_p_or_none[] = { PRED_p, PRED_none, NUM_PREDS }; +/* A list of all MVE ACLE functions. */ +static CONSTEXPR const function_group_info function_groups[] = { +#define DEF_MVE_FUNCTION(NAME, SHAPE, TYPES, PREDS) \ + { #NAME, &functions::NAME, &shapes::SHAPE, types_##TYPES, preds_##PREDS, \ + REQUIRES_FLOAT }, +#include "arm-mve-builtins.def" +}; + /* The scalar type associated with each vector type. */ extern GTY(()) tree scalar_types[NUM_VECTOR_TYPES]; tree scalar_types[NUM_VECTOR_TYPES]; @@ -431,6 +487,10 @@ handle_arm_mve_h (bool preserve_user_namespace) /* Define MVE functions. */ function_table = new hash_table (1023); + function_builder builder; + for (unsigned int i = 0; i < ARRAY_SIZE (function_groups); ++i) + builder.register_function_group (function_groups[i], + preserve_user_namespace); } /* Return true if CANDIDATE is equivalent to MODEL_TYPE for overloading diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 0d2ba968fc0..7688b5a7e53 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -358,14 +358,6 @@ #define vstrwq_scatter_shifted_offset_p(__base, __offset, __value, __p) __arm_vstrwq_scatter_shifted_offset_p(__base, __offset, __value, __p) #define vstrwq_scatter_shifted_offset(__base, __offset, __value) __arm_vstrwq_scatter_shifted_offset(__base, __offset, __value) #define vuninitializedq(__v) __arm_vuninitializedq(__v) -#define vreinterpretq_s16(__a) __arm_vreinterpretq_s16(__a) -#define vreinterpretq_s32(__a) __arm_vreinterpretq_s32(__a) -#define vreinterpretq_s64(__a) __arm_vreinterpretq_s64(__a) -#define vreinterpretq_s8(__a) __arm_vreinterpretq_s8(__a) -#define vreinterpretq_u16(__a) __arm_vreinterpretq_u16(__a) -#define vreinterpretq_u32(__a) __arm_vreinterpretq_u32(__a) -#define vreinterpretq_u64(__a) __arm_vreinterpretq_u64(__a) -#define vreinterpretq_u8(__a) __arm_vreinterpretq_u8(__a) #define vddupq_m(__inactive, __a, __imm, __p) __arm_vddupq_m(__inactive, __a, __imm, __p) #define vddupq_u8(__a, __imm) __arm_vddupq_u8(__a, __imm) #define vddupq_u32(__a, __imm) __arm_vddupq_u32(__a, __imm) @@ -518,8 +510,6 @@ #define vfmsq_m(__a, __b, __c, __p) __arm_vfmsq_m(__a, __b, __c, __p) #define vmaxnmq_m(__inactive, __a, __b, __p) __arm_vmaxnmq_m(__inactive, __a, __b, __p) #define vminnmq_m(__inactive, __a, __b, __p) __arm_vminnmq_m(__inactive, __a, __b, __p) -#define vreinterpretq_f16(__a) __arm_vreinterpretq_f16(__a) -#define vreinterpretq_f32(__a) __arm_vreinterpretq_f32(__a) #define vminnmq_x(__a, __b, __p) __arm_vminnmq_x(__a, __b, __p) #define vmaxnmq_x(__a, __b, __p) __arm_vmaxnmq_x(__a, __b, __p) #define vcmulq_x(__a, __b, __p) __arm_vcmulq_x(__a, __b, __p) @@ -2365,96 +2355,6 @@ #define vaddq_u32(__a, __b) __arm_vaddq_u32(__a, __b) #define vaddq_f16(__a, __b) __arm_vaddq_f16(__a, __b) #define vaddq_f32(__a, __b) __arm_vaddq_f32(__a, __b) -#define vreinterpretq_s16_s32(__a) __arm_vreinterpretq_s16_s32(__a) -#define vreinterpretq_s16_s64(__a) __arm_vreinterpretq_s16_s64(__a) -#define vreinterpretq_s16_s8(__a) __arm_vreinterpretq_s16_s8(__a) -#define vreinterpretq_s16_u16(__a) __arm_vreinterpretq_s16_u16(__a) -#define vreinterpretq_s16_u32(__a) __arm_vreinterpretq_s16_u32(__a) -#define vreinterpretq_s16_u64(__a) __arm_vreinterpretq_s16_u64(__a) -#define vreinterpretq_s16_u8(__a) __arm_vreinterpretq_s16_u8(__a) -#define vreinterpretq_s32_s16(__a) __arm_vreinterpretq_s32_s16(__a) -#define vreinterpretq_s32_s64(__a) __arm_vreinterpretq_s32_s64(__a) -#define vreinterpretq_s32_s8(__a) __arm_vreinterpretq_s32_s8(__a) -#define vreinterpretq_s32_u16(__a) __arm_vreinterpretq_s32_u16(__a) -#define vreinterpretq_s32_u32(__a) __arm_vreinterpretq_s32_u32(__a) -#define vreinterpretq_s32_u64(__a) __arm_vreinterpretq_s32_u64(__a) -#define vreinterpretq_s32_u8(__a) __arm_vreinterpretq_s32_u8(__a) -#define vreinterpretq_s64_s16(__a) __arm_vreinterpretq_s64_s16(__a) -#define vreinterpretq_s64_s32(__a) __arm_vreinterpretq_s64_s32(__a) -#define vreinterpretq_s64_s8(__a) __arm_vreinterpretq_s64_s8(__a) -#define vreinterpretq_s64_u16(__a) __arm_vreinterpretq_s64_u16(__a) -#define vreinterpretq_s64_u32(__a) __arm_vreinterpretq_s64_u32(__a) -#define vreinterpretq_s64_u64(__a) __arm_vreinterpretq_s64_u64(__a) -#define vreinterpretq_s64_u8(__a) __arm_vreinterpretq_s64_u8(__a) -#define vreinterpretq_s8_s16(__a) __arm_vreinterpretq_s8_s16(__a) -#define vreinterpretq_s8_s32(__a) __arm_vreinterpretq_s8_s32(__a) -#define vreinterpretq_s8_s64(__a) __arm_vreinterpretq_s8_s64(__a) -#define vreinterpretq_s8_u16(__a) __arm_vreinterpretq_s8_u16(__a) -#define vreinterpretq_s8_u32(__a) __arm_vreinterpretq_s8_u32(__a) -#define vreinterpretq_s8_u64(__a) __arm_vreinterpretq_s8_u64(__a) -#define vreinterpretq_s8_u8(__a) __arm_vreinterpretq_s8_u8(__a) -#define vreinterpretq_u16_s16(__a) __arm_vreinterpretq_u16_s16(__a) -#define vreinterpretq_u16_s32(__a) __arm_vreinterpretq_u16_s32(__a) -#define vreinterpretq_u16_s64(__a) __arm_vreinterpretq_u16_s64(__a) -#define vreinterpretq_u16_s8(__a) __arm_vreinterpretq_u16_s8(__a) -#define vreinterpretq_u16_u32(__a) __arm_vreinterpretq_u16_u32(__a) -#define vreinterpretq_u16_u64(__a) __arm_vreinterpretq_u16_u64(__a) -#define vreinterpretq_u16_u8(__a) __arm_vreinterpretq_u16_u8(__a) -#define vreinterpretq_u32_s16(__a) __arm_vreinterpretq_u32_s16(__a) -#define vreinterpretq_u32_s32(__a) __arm_vreinterpretq_u32_s32(__a) -#define vreinterpretq_u32_s64(__a) __arm_vreinterpretq_u32_s64(__a) -#define vreinterpretq_u32_s8(__a) __arm_vreinterpretq_u32_s8(__a) -#define vreinterpretq_u32_u16(__a) __arm_vreinterpretq_u32_u16(__a) -#define vreinterpretq_u32_u64(__a) __arm_vreinterpretq_u32_u64(__a) -#define vreinterpretq_u32_u8(__a) __arm_vreinterpretq_u32_u8(__a) -#define vreinterpretq_u64_s16(__a) __arm_vreinterpretq_u64_s16(__a) -#define vreinterpretq_u64_s32(__a) __arm_vreinterpretq_u64_s32(__a) -#define vreinterpretq_u64_s64(__a) __arm_vreinterpretq_u64_s64(__a) -#define vreinterpretq_u64_s8(__a) __arm_vreinterpretq_u64_s8(__a) -#define vreinterpretq_u64_u16(__a) __arm_vreinterpretq_u64_u16(__a) -#define vreinterpretq_u64_u32(__a) __arm_vreinterpretq_u64_u32(__a) -#define vreinterpretq_u64_u8(__a) __arm_vreinterpretq_u64_u8(__a) -#define vreinterpretq_u8_s16(__a) __arm_vreinterpretq_u8_s16(__a) -#define vreinterpretq_u8_s32(__a) __arm_vreinterpretq_u8_s32(__a) -#define vreinterpretq_u8_s64(__a) __arm_vreinterpretq_u8_s64(__a) -#define vreinterpretq_u8_s8(__a) __arm_vreinterpretq_u8_s8(__a) -#define vreinterpretq_u8_u16(__a) __arm_vreinterpretq_u8_u16(__a) -#define vreinterpretq_u8_u32(__a) __arm_vreinterpretq_u8_u32(__a) -#define vreinterpretq_u8_u64(__a) __arm_vreinterpretq_u8_u64(__a) -#define vreinterpretq_s32_f16(__a) __arm_vreinterpretq_s32_f16(__a) -#define vreinterpretq_s32_f32(__a) __arm_vreinterpretq_s32_f32(__a) -#define vreinterpretq_u16_f16(__a) __arm_vreinterpretq_u16_f16(__a) -#define vreinterpretq_u16_f32(__a) __arm_vreinterpretq_u16_f32(__a) -#define vreinterpretq_u32_f16(__a) __arm_vreinterpretq_u32_f16(__a) -#define vreinterpretq_u32_f32(__a) __arm_vreinterpretq_u32_f32(__a) -#define vreinterpretq_u64_f16(__a) __arm_vreinterpretq_u64_f16(__a) -#define vreinterpretq_u64_f32(__a) __arm_vreinterpretq_u64_f32(__a) -#define vreinterpretq_u8_f16(__a) __arm_vreinterpretq_u8_f16(__a) -#define vreinterpretq_u8_f32(__a) __arm_vreinterpretq_u8_f32(__a) -#define vreinterpretq_f16_f32(__a) __arm_vreinterpretq_f16_f32(__a) -#define vreinterpretq_f16_s16(__a) __arm_vreinterpretq_f16_s16(__a) -#define vreinterpretq_f16_s32(__a) __arm_vreinterpretq_f16_s32(__a) -#define vreinterpretq_f16_s64(__a) __arm_vreinterpretq_f16_s64(__a) -#define vreinterpretq_f16_s8(__a) __arm_vreinterpretq_f16_s8(__a) -#define vreinterpretq_f16_u16(__a) __arm_vreinterpretq_f16_u16(__a) -#define vreinterpretq_f16_u32(__a) __arm_vreinterpretq_f16_u32(__a) -#define vreinterpretq_f16_u64(__a) __arm_vreinterpretq_f16_u64(__a) -#define vreinterpretq_f16_u8(__a) __arm_vreinterpretq_f16_u8(__a) -#define vreinterpretq_f32_f16(__a) __arm_vreinterpretq_f32_f16(__a) -#define vreinterpretq_f32_s16(__a) __arm_vreinterpretq_f32_s16(__a) -#define vreinterpretq_f32_s32(__a) __arm_vreinterpretq_f32_s32(__a) -#define vreinterpretq_f32_s64(__a) __arm_vreinterpretq_f32_s64(__a) -#define vreinterpretq_f32_s8(__a) __arm_vreinterpretq_f32_s8(__a) -#define vreinterpretq_f32_u16(__a) __arm_vreinterpretq_f32_u16(__a) -#define vreinterpretq_f32_u32(__a) __arm_vreinterpretq_f32_u32(__a) -#define vreinterpretq_f32_u64(__a) __arm_vreinterpretq_f32_u64(__a) -#define vreinterpretq_f32_u8(__a) __arm_vreinterpretq_f32_u8(__a) -#define vreinterpretq_s16_f16(__a) __arm_vreinterpretq_s16_f16(__a) -#define vreinterpretq_s16_f32(__a) __arm_vreinterpretq_s16_f32(__a) -#define vreinterpretq_s64_f16(__a) __arm_vreinterpretq_s64_f16(__a) -#define vreinterpretq_s64_f32(__a) __arm_vreinterpretq_s64_f32(__a) -#define vreinterpretq_s8_f16(__a) __arm_vreinterpretq_s8_f16(__a) -#define vreinterpretq_s8_f32(__a) __arm_vreinterpretq_s8_f32(__a) #define vuninitializedq_u8(void) __arm_vuninitializedq_u8(void) #define vuninitializedq_u16(void) __arm_vuninitializedq_u16(void) #define vuninitializedq_u32(void) __arm_vuninitializedq_u32(void) @@ -37874,126 +37774,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t]: __arm_vuninitializedq_f16 (), \ int (*)[__ARM_mve_type_float32x4_t]: __arm_vuninitializedq_f32 ());}) -#define __arm_vreinterpretq_f16(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_f16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_f16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_f16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_f16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_f16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_f16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_f16_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) - -#define __arm_vreinterpretq_f32(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_f32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_f32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_f32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_f32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_f32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_f32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) - -#define __arm_vreinterpretq_s16(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_s16_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_s16_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) - -#define __arm_vreinterpretq_s32(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_s32_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_s32_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) - -#define __arm_vreinterpretq_s64(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_s64_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s64_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s64_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s64_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s64_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s64_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s64_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s64_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_s64_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) - -#define __arm_vreinterpretq_s8(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_s8_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s8_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s8_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s8_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s8_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s8_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s8_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_s8_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) - -#define __arm_vreinterpretq_u16(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_u16_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_u16_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) - -#define __arm_vreinterpretq_u32(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_u32_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_u32_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) - -#define __arm_vreinterpretq_u64(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_u64_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u64_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u64_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u64_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u64_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u64_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u64_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u64_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_u64_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) - -#define __arm_vreinterpretq_u8(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_u8_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u8_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u8_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u8_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u8_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u8_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u8_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \ - int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_u8_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) - #define __arm_vstrwq_scatter_base_wb(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \ int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_wb_s32 (p0, p1, __ARM_mve_coerce(__p2, int32x4_t)), \ @@ -39931,86 +39711,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint32x4_t]: __arm_vuninitializedq_u32 (), \ int (*)[__ARM_mve_type_uint64x2_t]: __arm_vuninitializedq_u64 ());}) -#define __arm_vreinterpretq_s16(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) - -#define __arm_vreinterpretq_s32(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) - -#define __arm_vreinterpretq_s64(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s64_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s64_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s64_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s64_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s64_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s64_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s64_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) - -#define __arm_vreinterpretq_s8(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s8_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s8_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s8_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s8_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s8_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s8_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) - -#define __arm_vreinterpretq_u16(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) - -#define __arm_vreinterpretq_u32(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) - -#define __arm_vreinterpretq_u64(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u64_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u64_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u64_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u64_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u64_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u64_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u64_s64 (__ARM_mve_coerce(__p0, int64x2_t)));}) - -#define __arm_vreinterpretq_u8(p0) ({ __typeof(p0) __p0 = (p0); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ - int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u8_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ - int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u8_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ - int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u8_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \ - int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u8_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ - int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u8_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ - int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u8_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));}) - #define __arm_vabsq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int8x16_t]: __arm_vabsq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \ diff --git a/gcc/config/arm/arm_mve_types.h b/gcc/config/arm/arm_mve_types.h index 12bb519142f..ae2591faa03 100644 --- a/gcc/config/arm/arm_mve_types.h +++ b/gcc/config/arm/arm_mve_types.h @@ -29,1124 +29,101 @@ typedef float float32_t; #pragma GCC arm "arm_mve_types.h" -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16_s32 (int32x4_t __a) -{ - return (int16x8_t) __a; -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16_s64 (int64x2_t __a) -{ - return (int16x8_t) __a; -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16_s8 (int8x16_t __a) -{ - return (int16x8_t) __a; -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16_u16 (uint16x8_t __a) -{ - return (int16x8_t) __a; -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16_u32 (uint32x4_t __a) -{ - return (int16x8_t) __a; -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16_u64 (uint64x2_t __a) -{ - return (int16x8_t) __a; -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16_u8 (uint8x16_t __a) -{ - return (int16x8_t) __a; -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32_s16 (int16x8_t __a) -{ - return (int32x4_t) __a; -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32_s64 (int64x2_t __a) -{ - return (int32x4_t) __a; -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32_s8 (int8x16_t __a) -{ - return (int32x4_t) __a; -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32_u16 (uint16x8_t __a) -{ - return (int32x4_t) __a; -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32_u32 (uint32x4_t __a) -{ - return (int32x4_t) __a; -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32_u64 (uint64x2_t __a) -{ - return (int32x4_t) __a; -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32_u8 (uint8x16_t __a) -{ - return (int32x4_t) __a; -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64_s16 (int16x8_t __a) -{ - return (int64x2_t) __a; -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64_s32 (int32x4_t __a) -{ - return (int64x2_t) __a; -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64_s8 (int8x16_t __a) -{ - return (int64x2_t) __a; -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64_u16 (uint16x8_t __a) -{ - return (int64x2_t) __a; -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64_u32 (uint32x4_t __a) -{ - return (int64x2_t) __a; -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64_u64 (uint64x2_t __a) -{ - return (int64x2_t) __a; -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64_u8 (uint8x16_t __a) -{ - return (int64x2_t) __a; -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8_s16 (int16x8_t __a) -{ - return (int8x16_t) __a; -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8_s32 (int32x4_t __a) -{ - return (int8x16_t) __a; -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8_s64 (int64x2_t __a) -{ - return (int8x16_t) __a; -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8_u16 (uint16x8_t __a) -{ - return (int8x16_t) __a; -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8_u32 (uint32x4_t __a) -{ - return (int8x16_t) __a; -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8_u64 (uint64x2_t __a) -{ - return (int8x16_t) __a; -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8_u8 (uint8x16_t __a) -{ - return (int8x16_t) __a; -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16_s16 (int16x8_t __a) -{ - return (uint16x8_t) __a; -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16_s32 (int32x4_t __a) -{ - return (uint16x8_t) __a; -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16_s64 (int64x2_t __a) -{ - return (uint16x8_t) __a; -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16_s8 (int8x16_t __a) -{ - return (uint16x8_t) __a; -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16_u32 (uint32x4_t __a) -{ - return (uint16x8_t) __a; -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16_u64 (uint64x2_t __a) -{ - return (uint16x8_t) __a; -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16_u8 (uint8x16_t __a) -{ - return (uint16x8_t) __a; -} - - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32_s16 (int16x8_t __a) -{ - return (uint32x4_t) __a; -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32_s32 (int32x4_t __a) -{ - return (uint32x4_t) __a; -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32_s64 (int64x2_t __a) -{ - return (uint32x4_t) __a; -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32_s8 (int8x16_t __a) -{ - return (uint32x4_t) __a; -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32_u16 (uint16x8_t __a) -{ - return (uint32x4_t) __a; -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32_u64 (uint64x2_t __a) -{ - return (uint32x4_t) __a; -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32_u8 (uint8x16_t __a) -{ - return (uint32x4_t) __a; -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64_s16 (int16x8_t __a) -{ - return (uint64x2_t) __a; -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64_s32 (int32x4_t __a) -{ - return (uint64x2_t) __a; -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64_s64 (int64x2_t __a) -{ - return (uint64x2_t) __a; -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64_s8 (int8x16_t __a) -{ - return (uint64x2_t) __a; -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64_u16 (uint16x8_t __a) -{ - return (uint64x2_t) __a; -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64_u32 (uint32x4_t __a) -{ - return (uint64x2_t) __a; -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64_u8 (uint8x16_t __a) -{ - return (uint64x2_t) __a; -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8_s16 (int16x8_t __a) -{ - return (uint8x16_t) __a; -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8_s32 (int32x4_t __a) -{ - return (uint8x16_t) __a; -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8_s64 (int64x2_t __a) -{ - return (uint8x16_t) __a; -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8_s8 (int8x16_t __a) -{ - return (uint8x16_t) __a; -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8_u16 (uint16x8_t __a) -{ - return (uint8x16_t) __a; -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8_u32 (uint32x4_t __a) -{ - return (uint8x16_t) __a; -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8_u64 (uint64x2_t __a) -{ - return (uint8x16_t) __a; -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vuninitializedq_u8 (void) -{ - uint8x16_t __uninit; - __asm__ ("": "=w"(__uninit)); - return __uninit; -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vuninitializedq_u16 (void) -{ - uint16x8_t __uninit; - __asm__ ("": "=w"(__uninit)); - return __uninit; -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vuninitializedq_u32 (void) -{ - uint32x4_t __uninit; - __asm__ ("": "=w"(__uninit)); - return __uninit; -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vuninitializedq_u64 (void) -{ - uint64x2_t __uninit; - __asm__ ("": "=w"(__uninit)); - return __uninit; -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vuninitializedq_s8 (void) -{ - int8x16_t __uninit; - __asm__ ("": "=w"(__uninit)); - return __uninit; -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vuninitializedq_s16 (void) -{ - int16x8_t __uninit; - __asm__ ("": "=w"(__uninit)); - return __uninit; -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vuninitializedq_s32 (void) -{ - int32x4_t __uninit; - __asm__ ("": "=w"(__uninit)); - return __uninit; -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vuninitializedq_s64 (void) -{ - int64x2_t __uninit; - __asm__ ("": "=w"(__uninit)); - return __uninit; -} - -#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32_f16 (float16x8_t __a) -{ - return (int32x4_t) __a; -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32_f32 (float32x4_t __a) -{ - return (int32x4_t) __a; -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16_f16 (float16x8_t __a) -{ - return (int16x8_t) __a; -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16_f32 (float32x4_t __a) -{ - return (int16x8_t) __a; -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64_f16 (float16x8_t __a) -{ - return (int64x2_t) __a; -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64_f32 (float32x4_t __a) -{ - return (int64x2_t) __a; -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8_f16 (float16x8_t __a) -{ - return (int8x16_t) __a; -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8_f32 (float32x4_t __a) -{ - return (int8x16_t) __a; -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16_f16 (float16x8_t __a) -{ - return (uint16x8_t) __a; -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16_f32 (float32x4_t __a) -{ - return (uint16x8_t) __a; -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32_f16 (float16x8_t __a) -{ - return (uint32x4_t) __a; -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32_f32 (float32x4_t __a) -{ - return (uint32x4_t) __a; -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64_f16 (float16x8_t __a) -{ - return (uint64x2_t) __a; -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64_f32 (float32x4_t __a) -{ - return (uint64x2_t) __a; -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8_f16 (float16x8_t __a) -{ - return (uint8x16_t) __a; -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8_f32 (float32x4_t __a) -{ - return (uint8x16_t) __a; -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_f32 (float32x4_t __a) -{ - return (float16x8_t) __a; -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_s16 (int16x8_t __a) -{ - return (float16x8_t) __a; -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_s32 (int32x4_t __a) -{ - return (float16x8_t) __a; -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_s64 (int64x2_t __a) -{ - return (float16x8_t) __a; -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_s8 (int8x16_t __a) -{ - return (float16x8_t) __a; -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_u16 (uint16x8_t __a) -{ - return (float16x8_t) __a; -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_u32 (uint32x4_t __a) -{ - return (float16x8_t) __a; -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_u64 (uint64x2_t __a) -{ - return (float16x8_t) __a; -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16_u8 (uint8x16_t __a) -{ - return (float16x8_t) __a; -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_f16 (float16x8_t __a) -{ - return (float32x4_t) __a; -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_s16 (int16x8_t __a) -{ - return (float32x4_t) __a; -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_s32 (int32x4_t __a) -{ - return (float32x4_t) __a; -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_s64 (int64x2_t __a) -{ - return (float32x4_t) __a; -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_s8 (int8x16_t __a) -{ - return (float32x4_t) __a; -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_u16 (uint16x8_t __a) -{ - return (float32x4_t) __a; -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_u32 (uint32x4_t __a) -{ - return (float32x4_t) __a; -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_u64 (uint64x2_t __a) -{ - return (float32x4_t) __a; -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32_u8 (uint8x16_t __a) -{ - return (float32x4_t) __a; -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vuninitializedq_f16 (void) -{ - float16x8_t __uninit; - __asm__ ("": "=w" (__uninit)); - return __uninit; -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vuninitializedq_f32 (void) -{ - float32x4_t __uninit; - __asm__ ("": "=w" (__uninit)); - return __uninit; -} - -#endif - -#ifdef __cplusplus - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16 (int32x4_t __a) -{ - return __arm_vreinterpretq_s16_s32 (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16 (int64x2_t __a) -{ - return __arm_vreinterpretq_s16_s64 (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16 (int8x16_t __a) -{ - return __arm_vreinterpretq_s16_s8 (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16 (uint16x8_t __a) -{ - return __arm_vreinterpretq_s16_u16 (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16 (uint32x4_t __a) -{ - return __arm_vreinterpretq_s16_u32 (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16 (uint64x2_t __a) -{ - return __arm_vreinterpretq_s16_u64 (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16 (uint8x16_t __a) -{ - return __arm_vreinterpretq_s16_u8 (__a); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32 (int16x8_t __a) -{ - return __arm_vreinterpretq_s32_s16 (__a); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32 (int64x2_t __a) -{ - return __arm_vreinterpretq_s32_s64 (__a); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32 (int8x16_t __a) -{ - return __arm_vreinterpretq_s32_s8 (__a); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32 (uint16x8_t __a) -{ - return __arm_vreinterpretq_s32_u16 (__a); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32 (uint32x4_t __a) -{ - return __arm_vreinterpretq_s32_u32 (__a); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32 (uint64x2_t __a) -{ - return __arm_vreinterpretq_s32_u64 (__a); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32 (uint8x16_t __a) -{ - return __arm_vreinterpretq_s32_u8 (__a); -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64 (int16x8_t __a) -{ - return __arm_vreinterpretq_s64_s16 (__a); -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64 (int32x4_t __a) -{ - return __arm_vreinterpretq_s64_s32 (__a); -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64 (int8x16_t __a) -{ - return __arm_vreinterpretq_s64_s8 (__a); -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64 (uint16x8_t __a) -{ - return __arm_vreinterpretq_s64_u16 (__a); -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64 (uint32x4_t __a) -{ - return __arm_vreinterpretq_s64_u32 (__a); -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64 (uint64x2_t __a) -{ - return __arm_vreinterpretq_s64_u64 (__a); -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64 (uint8x16_t __a) -{ - return __arm_vreinterpretq_s64_u8 (__a); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8 (int16x8_t __a) -{ - return __arm_vreinterpretq_s8_s16 (__a); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8 (int32x4_t __a) -{ - return __arm_vreinterpretq_s8_s32 (__a); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8 (int64x2_t __a) -{ - return __arm_vreinterpretq_s8_s64 (__a); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8 (uint16x8_t __a) -{ - return __arm_vreinterpretq_s8_u16 (__a); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8 (uint32x4_t __a) -{ - return __arm_vreinterpretq_s8_u32 (__a); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8 (uint64x2_t __a) -{ - return __arm_vreinterpretq_s8_u64 (__a); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8 (uint8x16_t __a) -{ - return __arm_vreinterpretq_s8_u8 (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16 (int16x8_t __a) -{ - return __arm_vreinterpretq_u16_s16 (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16 (int32x4_t __a) -{ - return __arm_vreinterpretq_u16_s32 (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16 (int64x2_t __a) -{ - return __arm_vreinterpretq_u16_s64 (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16 (int8x16_t __a) -{ - return __arm_vreinterpretq_u16_s8 (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16 (uint32x4_t __a) -{ - return __arm_vreinterpretq_u16_u32 (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16 (uint64x2_t __a) -{ - return __arm_vreinterpretq_u16_u64 (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16 (uint8x16_t __a) -{ - return __arm_vreinterpretq_u16_u8 (__a); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32 (int16x8_t __a) -{ - return __arm_vreinterpretq_u32_s16 (__a); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32 (int32x4_t __a) -{ - return __arm_vreinterpretq_u32_s32 (__a); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32 (int64x2_t __a) -{ - return __arm_vreinterpretq_u32_s64 (__a); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32 (int8x16_t __a) -{ - return __arm_vreinterpretq_u32_s8 (__a); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32 (uint16x8_t __a) -{ - return __arm_vreinterpretq_u32_u16 (__a); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32 (uint64x2_t __a) -{ - return __arm_vreinterpretq_u32_u64 (__a); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32 (uint8x16_t __a) -{ - return __arm_vreinterpretq_u32_u8 (__a); -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64 (int16x8_t __a) -{ - return __arm_vreinterpretq_u64_s16 (__a); -} - -__extension__ extern __inline uint64x2_t +__extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64 (int32x4_t __a) +__arm_vuninitializedq_u8 (void) { - return __arm_vreinterpretq_u64_s32 (__a); + uint8x16_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; } -__extension__ extern __inline uint64x2_t +__extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64 (int64x2_t __a) +__arm_vuninitializedq_u16 (void) { - return __arm_vreinterpretq_u64_s64 (__a); + uint16x8_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; } -__extension__ extern __inline uint64x2_t +__extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64 (int8x16_t __a) +__arm_vuninitializedq_u32 (void) { - return __arm_vreinterpretq_u64_s8 (__a); + uint32x4_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; } __extension__ extern __inline uint64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64 (uint16x8_t __a) +__arm_vuninitializedq_u64 (void) { - return __arm_vreinterpretq_u64_u16 (__a); + uint64x2_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; } -__extension__ extern __inline uint64x2_t +__extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64 (uint32x4_t __a) +__arm_vuninitializedq_s8 (void) { - return __arm_vreinterpretq_u64_u32 (__a); + int8x16_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; } -__extension__ extern __inline uint64x2_t +__extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64 (uint8x16_t __a) +__arm_vuninitializedq_s16 (void) { - return __arm_vreinterpretq_u64_u8 (__a); + int16x8_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; } -__extension__ extern __inline uint8x16_t +__extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8 (int16x8_t __a) +__arm_vuninitializedq_s32 (void) { - return __arm_vreinterpretq_u8_s16 (__a); + int32x4_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; } -__extension__ extern __inline uint8x16_t +__extension__ extern __inline int64x2_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8 (int32x4_t __a) +__arm_vuninitializedq_s64 (void) { - return __arm_vreinterpretq_u8_s32 (__a); + int64x2_t __uninit; + __asm__ ("": "=w"(__uninit)); + return __uninit; } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8 (int64x2_t __a) -{ - return __arm_vreinterpretq_u8_s64 (__a); -} +#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ -__extension__ extern __inline uint8x16_t +__extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8 (int8x16_t __a) +__arm_vuninitializedq_f16 (void) { - return __arm_vreinterpretq_u8_s8 (__a); + float16x8_t __uninit; + __asm__ ("": "=w" (__uninit)); + return __uninit; } -__extension__ extern __inline uint8x16_t +__extension__ extern __inline float32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8 (uint16x8_t __a) +__arm_vuninitializedq_f32 (void) { - return __arm_vreinterpretq_u8_u16 (__a); + float32x4_t __uninit; + __asm__ ("": "=w" (__uninit)); + return __uninit; } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8 (uint32x4_t __a) -{ - return __arm_vreinterpretq_u8_u32 (__a); -} +#endif -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8 (uint64x2_t __a) -{ - return __arm_vreinterpretq_u8_u64 (__a); -} +#ifdef __cplusplus __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -1205,244 +182,6 @@ __arm_vuninitializedq (int64x2_t /* __v ATTRIBUTE UNUSED */) } #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32 (float16x8_t __a) -{ - return __arm_vreinterpretq_s32_f16 (__a); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s32 (float32x4_t __a) -{ - return __arm_vreinterpretq_s32_f32 (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16 (float16x8_t __a) -{ - return __arm_vreinterpretq_s16_f16 (__a); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s16 (float32x4_t __a) -{ - return __arm_vreinterpretq_s16_f32 (__a); -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64 (float16x8_t __a) -{ - return __arm_vreinterpretq_s64_f16 (__a); -} - -__extension__ extern __inline int64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s64 (float32x4_t __a) -{ - return __arm_vreinterpretq_s64_f32 (__a); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8 (float16x8_t __a) -{ - return __arm_vreinterpretq_s8_f16 (__a); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_s8 (float32x4_t __a) -{ - return __arm_vreinterpretq_s8_f32 (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16 (float16x8_t __a) -{ - return __arm_vreinterpretq_u16_f16 (__a); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u16 (float32x4_t __a) -{ - return __arm_vreinterpretq_u16_f32 (__a); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32 (float16x8_t __a) -{ - return __arm_vreinterpretq_u32_f16 (__a); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u32 (float32x4_t __a) -{ - return __arm_vreinterpretq_u32_f32 (__a); -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64 (float16x8_t __a) -{ - return __arm_vreinterpretq_u64_f16 (__a); -} - -__extension__ extern __inline uint64x2_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u64 (float32x4_t __a) -{ - return __arm_vreinterpretq_u64_f32 (__a); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8 (float16x8_t __a) -{ - return __arm_vreinterpretq_u8_f16 (__a); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_u8 (float32x4_t __a) -{ - return __arm_vreinterpretq_u8_f32 (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16 (float32x4_t __a) -{ - return __arm_vreinterpretq_f16_f32 (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16 (int16x8_t __a) -{ - return __arm_vreinterpretq_f16_s16 (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16 (int32x4_t __a) -{ - return __arm_vreinterpretq_f16_s32 (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16 (int64x2_t __a) -{ - return __arm_vreinterpretq_f16_s64 (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16 (int8x16_t __a) -{ - return __arm_vreinterpretq_f16_s8 (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16 (uint16x8_t __a) -{ - return __arm_vreinterpretq_f16_u16 (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16 (uint32x4_t __a) -{ - return __arm_vreinterpretq_f16_u32 (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16 (uint64x2_t __a) -{ - return __arm_vreinterpretq_f16_u64 (__a); -} - -__extension__ extern __inline float16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f16 (uint8x16_t __a) -{ - return __arm_vreinterpretq_f16_u8 (__a); -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32 (float16x8_t __a) -{ - return __arm_vreinterpretq_f32_f16 (__a); -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32 (int16x8_t __a) -{ - return __arm_vreinterpretq_f32_s16 (__a); -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32 (int32x4_t __a) -{ - return __arm_vreinterpretq_f32_s32 (__a); -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32 (int64x2_t __a) -{ - return __arm_vreinterpretq_f32_s64 (__a); -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32 (int8x16_t __a) -{ - return __arm_vreinterpretq_f32_s8 (__a); -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32 (uint16x8_t __a) -{ - return __arm_vreinterpretq_f32_u16 (__a); -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32 (uint32x4_t __a) -{ - return __arm_vreinterpretq_f32_u32 (__a); -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32 (uint64x2_t __a) -{ - return __arm_vreinterpretq_f32_u64 (__a); -} - -__extension__ extern __inline float32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vreinterpretq_f32 (uint8x16_t __a) -{ - return __arm_vreinterpretq_f32_u8 (__a); -} - __extension__ extern __inline float16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vuninitializedq (float16x8_t /* __v ATTRIBUTE UNUSED */) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 35eab6c94bf..ab688396f97 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -10561,3 +10561,21 @@ (define_expand "vcond_mask_" } DONE; }) + +;; Reinterpret operand 1 in operand 0's mode, without changing its contents. +(define_expand "@arm_mve_reinterpret" + [(set (match_operand:MVE_vecs 0 "register_operand") + (unspec:MVE_vecs + [(match_operand 1 "arm_any_register_operand")] + REINTERPRET))] + "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (mode)) + || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (mode))" + { + machine_mode src_mode = GET_MODE (operands[1]); + if (targetm.can_change_mode_class (mode, src_mode, VFP_REGS)) + { + emit_move_insn (operands[0], gen_lowpart (mode, operands[1])); + DONE; + } + } +) diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 84384ee798d..dccda283573 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -1255,4 +1255,5 @@ (define_c_enum "unspec" [ SQRSHRL_64 SQRSHRL_48 VSHLCQ_M_ + REINTERPRET ]) diff --git a/gcc/testsuite/g++.target/arm/mve.exp b/gcc/testsuite/g++.target/arm/mve.exp index cd824035540..f75ec20ea64 100644 --- a/gcc/testsuite/g++.target/arm/mve.exp +++ b/gcc/testsuite/g++.target/arm/mve.exp @@ -42,8 +42,12 @@ set dg-do-what-default "assemble" dg-init # Main loop. -dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/../../gcc.target/arm/mve/intrinsics/*.\[cCS\]]] \ - "" $DEFAULT_CXXFLAGS +set gcc_subdir [string replace $subdir 0 2 gcc] +set files [glob -nocomplain \ + "$srcdir/$subdir/../../gcc.target/arm/mve/intrinsics/*.\[cCS\]" \ + "$srcdir/$gcc_subdir/mve/general/*.\[cCS\]" \ + "$srcdir/$subdir/mve/general-c++/*.\[cCS\]"] +dg-runtest [lsort $files] "" $DEFAULT_CXXFLAGS # All done. set dg-do-what-default ${save-dg-do-what-default} diff --git a/gcc/testsuite/g++.target/arm/mve/general-c++/nomve_fp_1.c b/gcc/testsuite/g++.target/arm/mve/general-c++/nomve_fp_1.c new file mode 100644 index 00000000000..e0692ceb8c8 --- /dev/null +++ b/gcc/testsuite/g++.target/arm/mve/general-c++/nomve_fp_1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* Do not use dg-add-options arm_v8_1m_mve, because this might expand to "", + which could imply mve+fp depending on the user settings. We want to make + sure the '+fp' extension is not enabled. */ +/* { dg-options "-mfpu=auto -march=armv8.1-m.main+mve" } */ + +#include + +void +f1 (uint8x16_t v) +{ + vreinterpretq_f16 (v); /* { dg-error {ACLE function 'void vreinterpretq_f16\(uint8x16_t\)' requires ISA extension 'mve.fp'} } */ + /* { dg-message {note: you can enable mve.fp by using the command-line option '-march', or by using the 'target' attribute or pragma} "" {target *-*-*} .-1 } */ +} diff --git a/gcc/testsuite/g++.target/arm/mve/general-c++/vreinterpretq_1.C b/gcc/testsuite/g++.target/arm/mve/general-c++/vreinterpretq_1.C new file mode 100644 index 00000000000..8b29ee58163 --- /dev/null +++ b/gcc/testsuite/g++.target/arm/mve/general-c++/vreinterpretq_1.C @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ + +#include + +void +f1 (int8x16_t s8, uint16x8_t u16, float32x4_t f32) +{ + __arm_vreinterpretq_s8 (); /* { dg-error {no matching function for call to '__arm_vreinterpretq_s8\(\)'} } */ + __arm_vreinterpretq_s8 (s8, s8); /* { dg-error {no matching function for call to '__arm_vreinterpretq_s8\(int8x16_t\&, int8x16_t\&\)'} } */ + __arm_vreinterpretq_s8 (0); /* { dg-error {no matching function for call to '__arm_vreinterpretq_s8\(int\)'} } */ + __arm_vreinterpretq_s8 (s8); /* { dg-error {no matching function for call to '__arm_vreinterpretq_s8\(int8x16_t\&\)'} } */ + __arm_vreinterpretq_s8 (u16); + __arm_vreinterpretq_u16 (); /* { dg-error {no matching function for call to '__arm_vreinterpretq_u16\(\)'} } */ + __arm_vreinterpretq_u16 (u16, u16); /* { dg-error {no matching function for call to '__arm_vreinterpretq_u16\(uint16x8_t\&, uint16x8_t\&\)'} } */ + __arm_vreinterpretq_u16 (0); /* { dg-error {no matching function for call to '__arm_vreinterpretq_u16\(int\)'} } */ + __arm_vreinterpretq_u16 (u16); /* { dg-error {no matching function for call to '__arm_vreinterpretq_u16\(uint16x8_t\&\)'} } */ + __arm_vreinterpretq_u16 (f32); + __arm_vreinterpretq_f32 (); /* { dg-error {no matching function for call to '__arm_vreinterpretq_f32\(\)'} } */ + __arm_vreinterpretq_f32 (f32, f32); /* { dg-error {no matching function for call to '__arm_vreinterpretq_f32\(float32x4_t\&, float32x4_t\&\)'} } */ + __arm_vreinterpretq_f32 (0); /* { dg-error {no matching function for call to '__arm_vreinterpretq_f32\(int\)'} } */ + __arm_vreinterpretq_f32 (f32); /* { dg-error {no matching function for call to '__arm_vreinterpretq_f32\(float32x4_t\&\)'} } */ + __arm_vreinterpretq_f32 (s8); +} diff --git a/gcc/testsuite/gcc.target/arm/mve/general-c/nomve_fp_1.c b/gcc/testsuite/gcc.target/arm/mve/general-c/nomve_fp_1.c new file mode 100644 index 00000000000..21c2af16a61 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/general-c/nomve_fp_1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* Do not use dg-add-options arm_v8_1m_mve, because this might expand to "", + which could imply mve+fp depending on the user settings. We want to make + sure the '+fp' extension is not enabled. */ +/* { dg-options "-mfpu=auto -march=armv8.1-m.main+mve" } */ + +#include + +void +foo (uint8x16_t v) +{ + vreinterpretq_f16 (v); /* { dg-error {ACLE function '__arm_vreinterpretq_f16_u8' requires ISA extension 'mve.fp'} } */ + /* { dg-message {note: you can enable mve.fp by using the command-line option '-march', or by using the 'target' attribute or pragma} "" {target *-*-*} .-1 } */ +} diff --git a/gcc/testsuite/gcc.target/arm/mve/general-c/vreinterpretq_1.c b/gcc/testsuite/gcc.target/arm/mve/general-c/vreinterpretq_1.c new file mode 100644 index 00000000000..0297bd50198 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/general-c/vreinterpretq_1.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ + +#include + +void +f1 (int8x16_t s8, uint16x8_t u16, float32x4_t f32) +{ + __arm_vreinterpretq_s8 (); /* { dg-error {too few arguments to function '__arm_vreinterpretq_s8'} } */ + __arm_vreinterpretq_s8 (s8, s8); /* { dg-error {too many arguments to function '__arm_vreinterpretq_s8'} } */ + __arm_vreinterpretq_s8 (0); /* { dg-error {passing 'int' to argument 1 of '__arm_vreinterpretq_s8', which expects an MVE vector type} } */ + __arm_vreinterpretq_s8 (s8); /* { dg-error {'__arm_vreinterpretq_s8' has no form that takes 'int8x16_t' arguments} } */ + __arm_vreinterpretq_s8 (u16); + __arm_vreinterpretq_u16 (); /* { dg-error {too few arguments to function '__arm_vreinterpretq_u16'} } */ + __arm_vreinterpretq_u16 (u16, u16); /* { dg-error {too many arguments to function '__arm_vreinterpretq_u16'} } */ + __arm_vreinterpretq_u16 (0); /* { dg-error {passing 'int' to argument 1 of '__arm_vreinterpretq_u16', which expects an MVE vector type} } */ + __arm_vreinterpretq_u16 (u16); /* { dg-error {'__arm_vreinterpretq_u16' has no form that takes 'uint16x8_t' arguments} } */ + __arm_vreinterpretq_u16 (f32); + __arm_vreinterpretq_f32 (); /* { dg-error {too few arguments to function '__arm_vreinterpretq_f32'} } */ + __arm_vreinterpretq_f32 (f32, f32); /* { dg-error {too many arguments to function '__arm_vreinterpretq_f32'} } */ + __arm_vreinterpretq_f32 (0); /* { dg-error {passing 'int' to argument 1 of '__arm_vreinterpretq_f32', which expects an MVE vector type} } */ + __arm_vreinterpretq_f32 (f32); /* { dg-error {'__arm_vreinterpretq_f32' has no form that takes 'float32x4_t' arguments} } */ + __arm_vreinterpretq_f32 (s8); +} -- 2.34.1