From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id EFA253858D28 for ; Thu, 4 May 2023 09:11:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EFA253858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683191488; x=1714727488; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qfEAUotMcvXLBEvpJw9crj8fK0wOdoInTrIOVz6EYyE=; b=UpiAaAnhxGGJJxuPZM4AnJFa5WyGz4XWdKYHVhf2YOWiCefBPOhUJjFA fGn2m4trHOQz29RGJd7KHHcKWo0Q8Wf36aW3NuvxNOersv3mvZSE+sGVR D1K6m6Kq78wPS5VdhmSCQkOdU7tdB03YR+R5ZxJKbveaVD0fkPv22ILT2 DJF5rtUk8KoKvBHgDc8xgZLye/NXoRaAJ1bHJGmIQXcXj6ZiIpGLnBBy/ sCJJlTr515TIYEPzFXvxue8BGYZrbkpaJzjyVA11hHqiqt7X4vDW43Okc PVl3F9HkZ8HK6jWdImxmktvOm9YZK+DZsf/h8U2KJenc7X14dbueKyeDG A==; X-IronPort-AV: E=McAfee;i="6600,9927,10699"; a="338022794" X-IronPort-AV: E=Sophos;i="5.99,249,1677571200"; d="scan'208";a="338022794" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 May 2023 02:11:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10699"; a="727497761" X-IronPort-AV: E=Sophos;i="5.99,249,1677571200"; d="scan'208";a="727497761" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga008.jf.intel.com with ESMTP; 04 May 2023 02:11:20 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id AC4B71005608; Thu, 4 May 2023 17:11:19 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH v2] RISC-V: Legitimise the const0_rtx for RVV indexed load/store Date: Thu, 4 May 2023 17:11:18 +0800 Message-Id: <20230504091118.2805091-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230504083537.2719788-1-pan2.li@intel.com> References: <20230504083537.2719788-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch try to legitimise the const0_rtx (aka zero register) as the base register for the RVV indexed load/store instructions by allowing the const as the operand of the indexed RTL pattern. Then the underlying combine pass will try to perform the const propagation. For example: vint32m1_t test_vluxei32_v_i32m1_shortcut (vuint32m1_t bindex, size_t vl) { return __riscv_vluxei32_v_i32m1 ((int32_t *)0, bindex, vl); } Before this patch: li a5,0 <- can be eliminated. vl1re32.v v1,0(a1) vsetvli zero,a2,e32,m1,ta,ma vluxei32.v v1,(a5),v1 <- can propagate the const 0 to a5 here. vs1r.v v1,0(a0) ret After this patch: test_vluxei32_v_i32m1_shortcut: vl1re32.v v1,0(a1) vsetvli zero,a2,e32,m1,ta,ma vluxei32.v v1,(0),v1 vs1r.v v1,0(a0) ret As above, this patch allow you to propagaate the const 0 (aka zero register) to the base register of the RVV indexed load in the combine pass. This may benefit the underlying RVV auto-vectorization. gcc/ChangeLog: * config/riscv/vector.md: Allow const as the operand of RVV indexed load/store. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Adjust indexed load/store check condition. Signed-off-by: Pan Li Co-authored-by: Ju-Zhe Zhong --- gcc/config/riscv/vector.md | 62 +++++++++---------- .../base/zero_base_load_store_optimization.c | 3 +- 2 files changed, 33 insertions(+), 32 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 92115e3935f..dc05e9fc713 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1511,12 +1511,12 @@ (define_insn "@pred_indexed_load_same_eew" (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:V - [(match_operand 3 "pmode_register_operand" " r, r, r, r") + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ,rJ, rJ") (mem:BLK (scratch)) (match_operand: 4 "register_operand" " vr, vr,vr, vr")] ORDER) (match_operand:V 2 "vector_merge_operand" " vu, vu, 0, 0")))] "TARGET_VECTOR" - "vlxei.v\t%0,(%3),%4%p1" + "vlxei.v\t%0,(%z3),%4%p1" [(set_attr "type" "vldx") (set_attr "mode" "")]) @@ -1533,12 +1533,12 @@ (define_insn "@pred_indexed_load_x2_greater_eew" (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VEEWEXT2 - [(match_operand 3 "pmode_register_operand" " r, r") + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ") (mem:BLK (scratch)) (match_operand: 4 "register_operand" " vr, vr")] ORDER) (match_operand:VEEWEXT2 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" - "vlxei.v\t%0,(%3),%4%p1" + "vlxei.v\t%0,(%z3),%4%p1" [(set_attr "type" "vldx") (set_attr "mode" "")]) @@ -1554,12 +1554,12 @@ (define_insn "@pred_indexed_load_x4_greater_eew" (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VEEWEXT4 - [(match_operand 3 "pmode_register_operand" " r, r") + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ") (mem:BLK (scratch)) (match_operand: 4 "register_operand" " vr, vr")] ORDER) (match_operand:VEEWEXT4 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" - "vlxei.v\t%0,(%3),%4%p1" + "vlxei.v\t%0,(%z3),%4%p1" [(set_attr "type" "vldx") (set_attr "mode" "")]) @@ -1575,12 +1575,12 @@ (define_insn "@pred_indexed_load_x8_greater_eew" (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VEEWEXT8 - [(match_operand 3 "pmode_register_operand" " r, r") + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ") (mem:BLK (scratch)) (match_operand: 4 "register_operand" " vr, vr")] ORDER) (match_operand:VEEWEXT8 2 "vector_merge_operand" " vu, 0")))] "TARGET_VECTOR" - "vlxei.v\t%0,(%3),%4%p1" + "vlxei.v\t%0,(%z3),%4%p1" [(set_attr "type" "vldx") (set_attr "mode" "")]) @@ -1597,12 +1597,12 @@ (define_insn "@pred_indexed_load_x2_smaller_eew" (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VEEWTRUNC2 - [(match_operand 3 "pmode_register_operand" " r, r, r, r, r, r") + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ") (mem:BLK (scratch)) (match_operand: 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER) (match_operand:VEEWTRUNC2 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" - "vlxei.v\t%0,(%3),%4%p1" + "vlxei.v\t%0,(%z3),%4%p1" [(set_attr "type" "vldx") (set_attr "mode" "")]) @@ -1618,12 +1618,12 @@ (define_insn "@pred_indexed_load_x4_smaller_eew" (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VEEWTRUNC4 - [(match_operand 3 "pmode_register_operand" " r, r, r, r, r, r") + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ") (mem:BLK (scratch)) (match_operand: 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER) (match_operand:VEEWTRUNC4 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" - "vlxei.v\t%0,(%3),%4%p1" + "vlxei.v\t%0,(%z3),%4%p1" [(set_attr "type" "vldx") (set_attr "mode" "")]) @@ -1639,12 +1639,12 @@ (define_insn "@pred_indexed_load_x8_smaller_eew" (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec:VEEWTRUNC8 - [(match_operand 3 "pmode_register_operand" " r, r, r, r, r, r") + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ") (mem:BLK (scratch)) (match_operand: 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER) (match_operand:VEEWTRUNC8 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] "TARGET_VECTOR" - "vlxei.v\t%0,(%3),%4%p1" + "vlxei.v\t%0,(%z3),%4%p1" [(set_attr "type" "vldx") (set_attr "mode" "")]) @@ -1657,11 +1657,11 @@ (define_insn "@pred_indexed_store" (match_operand 5 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand 1 "pmode_register_operand" " r") + (match_operand 1 "pmode_reg_or_0_operand" " rJ") (match_operand:VNX1_QHSDI 2 "register_operand" " vr") (match_operand:VNX1_QHSD 3 "register_operand" " vr")] ORDER))] "TARGET_VECTOR" - "vsxei.v\t%3,(%1),%2%p0" + "vsxei.v\t%3,(%z1),%2%p0" [(set_attr "type" "vstx") (set_attr "mode" "")]) @@ -1674,11 +1674,11 @@ (define_insn "@pred_indexed_store" (match_operand 5 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand 1 "pmode_register_operand" " r") + (match_operand 1 "pmode_reg_or_0_operand" " rJ") (match_operand:VNX2_QHSDI 2 "register_operand" " vr") (match_operand:VNX2_QHSD 3 "register_operand" " vr")] ORDER))] "TARGET_VECTOR" - "vsxei.v\t%3,(%1),%2%p0" + "vsxei.v\t%3,(%z1),%2%p0" [(set_attr "type" "vstx") (set_attr "mode" "")]) @@ -1691,11 +1691,11 @@ (define_insn "@pred_indexed_store" (match_operand 5 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand 1 "pmode_register_operand" " r") + (match_operand 1 "pmode_reg_or_0_operand" " rJ") (match_operand:VNX4_QHSDI 2 "register_operand" " vr") (match_operand:VNX4_QHSD 3 "register_operand" " vr")] ORDER))] "TARGET_VECTOR" - "vsxei.v\t%3,(%1),%2%p0" + "vsxei.v\t%3,(%z1),%2%p0" [(set_attr "type" "vstx") (set_attr "mode" "")]) @@ -1708,11 +1708,11 @@ (define_insn "@pred_indexed_store" (match_operand 5 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand 1 "pmode_register_operand" " r") + (match_operand 1 "pmode_reg_or_0_operand" " rJ") (match_operand:VNX8_QHSDI 2 "register_operand" " vr") (match_operand:VNX8_QHSD 3 "register_operand" " vr")] ORDER))] "TARGET_VECTOR" - "vsxei.v\t%3,(%1),%2%p0" + "vsxei.v\t%3,(%z1),%2%p0" [(set_attr "type" "vstx") (set_attr "mode" "")]) @@ -1725,11 +1725,11 @@ (define_insn "@pred_indexed_store" (match_operand 5 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand 1 "pmode_register_operand" " r") + (match_operand 1 "pmode_reg_or_0_operand" " rJ") (match_operand:VNX16_QHSI 2 "register_operand" " vr") (match_operand:VNX16_QHS 3 "register_operand" " vr")] ORDER))] "TARGET_VECTOR" - "vsxei.v\t%3,(%1),%2%p0" + "vsxei.v\t%3,(%z1),%2%p0" [(set_attr "type" "vstx") (set_attr "mode" "")]) @@ -1742,11 +1742,11 @@ (define_insn "@pred_indexed_store" (match_operand 5 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand 1 "pmode_register_operand" " r") + (match_operand 1 "pmode_reg_or_0_operand" " rJ") (match_operand:VNX32_QHSI 2 "register_operand" " vr") (match_operand:VNX32_QHS 3 "register_operand" " vr")] ORDER))] "TARGET_VECTOR" - "vsxei.v\t%3,(%1),%2%p0" + "vsxei.v\t%3,(%z1),%2%p0" [(set_attr "type" "vstx") (set_attr "mode" "")]) @@ -1759,11 +1759,11 @@ (define_insn "@pred_indexed_store" (match_operand 5 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand 1 "pmode_register_operand" " r") - (match_operand:VNX64_QHI 2 "register_operand" " vr") + (match_operand 1 "pmode_reg_or_0_operand" " rJ") + (match_operand:VNX64_QHI 2 "register_operand" " vr") (match_operand:VNX64_QH 3 "register_operand" " vr")] ORDER))] "TARGET_VECTOR" - "vsxei.v\t%3,(%1),%2%p0" + "vsxei.v\t%3,(%z1),%2%p0" [(set_attr "type" "vstx") (set_attr "mode" "")]) @@ -1776,11 +1776,11 @@ (define_insn "@pred_indexed_store" (match_operand 5 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (match_operand 1 "pmode_register_operand" " r") + (match_operand 1 "pmode_reg_or_0_operand" " rJ") (match_operand:VNX128_Q 2 "register_operand" " vr") (match_operand:VNX128_Q 3 "register_operand" " vr")] ORDER))] "TARGET_VECTOR" - "vsxei.v\t%3,(%1),%2%p0" + "vsxei.v\t%3,(%z1),%2%p0" [(set_attr "type" "vstx") (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c index 9f323b0ba9c..fbcfb7b8501 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c @@ -131,4 +131,5 @@ void test_vsoxei32_v_f32m1_shortcut (vuint32m1_t bindex, vfloat32m1_t val, size_ /* { dg-final { scan-assembler-times {v[ls]e[0-9]+\.v\s+v[0-9]+,\s*0\(zero\)} 6 } } */ /* { dg-final { scan-assembler-times {v[ls]se[0-9]+\.v\s+v[0-9]+,\s*0\(zero\),\s*[ax][0-9]+} 6 } } */ -/* { dg-final { scan-assembler-times {li\s+[a-x][0-9]+,\s*0} 12 } } */ +/* { dg-final { scan-assembler-times {v[ls][uo]xei[0-9]+\.v\s+v[0-9]+,\s*\(zero\),\s*v[0-9]+} 12 } } */ +/* { dg-final { scan-assembler-not {li\s+[a-x][0-9]+,\s*0} } } */ -- 2.34.1