From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x1135.google.com (mail-yw1-x1135.google.com [IPv6:2607:f8b0:4864:20::1135]) by sourceware.org (Postfix) with ESMTPS id 9BCBE3858D33 for ; Fri, 5 May 2023 15:46:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9BCBE3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-yw1-x1135.google.com with SMTP id 00721157ae682-559debdedb5so27870357b3.0 for ; Fri, 05 May 2023 08:46:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1683301569; x=1685893569; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=bpZv4+boLhiQdiHYet1AQOKXn5fR8gbq70J+gDe/QMI=; b=KNSaeE3IGJjxuyCAW+b91PNNQcC7Ii/qAYO5YnJMu384OKE0rtKOVfLjtJtcLS3Mu8 v/bm8jVOfMSCvy3C8PEOhiTsGzhZ6uF2CNnLWkjgzgmNriDjI4GXMUaiTr6+Y12Dln9Z siaJdK2I29FyNGjwmhmguYYQJXgbuvJ6XZbtYrLaa13UrzpnDpFDRSwaQTr+HaLKRwwR XPnuT3tSLQbqRqjDll2IyIRWC6WE1OOtDrHqDVl+TdHhvlAl1iS7M4JvBYE23f8/317T +/z9mRZSgRZ4tBINSBrTooR3ez6jTyS3Jb1kGXwf9q1wMFwVt3WLu+eeEUHIFEBT/pUG +IjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683301569; x=1685893569; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=bpZv4+boLhiQdiHYet1AQOKXn5fR8gbq70J+gDe/QMI=; b=M0Ix+OvO/ZM/hUUQ3NnK53zdsn7flw5Z/7KUui2gy8QG2BGtntaaOG1dfIOmxHqyUl SKKicxSU8XPyqZzU3Os3GnQfrfgxWFRLVoWXXtyLymbtofwd3zhDz9VsQUK3NkHthCIF FzmeCtVdcnMkM9rpdI60z9OH7f7Kovoa5+XpPu2WNr4qp+Fz/mgUwhG0uM6AyqwDmhP0 L/SX2z1g2ksu81/JNrab/Yb68jNHbuerXtpn7qGwr3+4x3p4AWJ5r4lJ7lE8NkOe9I7J Ho7qTTOZUwTGEeWVnZjkMfhYIf+A0KIvM+xsacoumc8VWz8rg2WEQcyV7kLUH+Mg7V1X I+RQ== X-Gm-Message-State: AC+VfDzelouAUyEkXi250bBJaPWnKj5PRhVl9FBv053dfPrjEI3OsDIk 5x+8l919BUKnNLHGd7hIi4S/ChGqURHWNx1D1KbpMw== X-Google-Smtp-Source: ACHHUZ5KODcdkWJWf9z7OnDOqcX4MpPv+rYm+AVNHh4PIWl9DKgakDWLba9NiuSEq7tSnKb2/gN7dQ== X-Received: by 2002:a0d:d901:0:b0:55a:ad64:1b62 with SMTP id b1-20020a0dd901000000b0055aad641b62mr2258874ywe.16.1683301568629; Fri, 05 May 2023 08:46:08 -0700 (PDT) Received: from system76-pc.ba.rivosinc.com ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id p203-20020a8174d4000000b0055a3420b25asm542446ywc.50.2023.05.05.08.46.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 08:46:08 -0700 (PDT) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v6 0/9] RISC-V: autovec: Add autovec support Date: Fri, 5 May 2023 11:45:58 -0400 Message-Id: <20230505154607.1155567-1-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This series of patches adds foundational support for RISC-V auto-vectorization support. These patches are based on the current upstream rvv vector intrinsic support and is not a new implementation. Most of the implementation consists of adding the new vector cost model, the autovectorization patterns themselves and target hooks. This implementation only provides support for integer addition and subtraction as a proof of concept. This patch set should not be construed to be feature complete. Based on conversations with the community these patches are intended to lay the groundwork for feature completion and collaboration within the RISC-V community. These patches are largely based off the work of Juzhe Zhong (juzhe.zhong@rivai.ai) of RiVAI. More specifically the rvv-next branch at: https://github.com/riscv-collab/riscv-gcc.git is the foundation of this patch set. As discussed on this list, if these patches are approved they will be merged into a "auto-vectorization" branch once gcc-13 branches for release. There are two known issues related to crashes (assert failures) associated with tree vectorization; one of which I have sent a patch for and have received feedback. Changes in v6: - Incorporated upstream comments, added target hook for TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT Changes in v5: - Incorporated upstream comments large to delete unnecessary code Changes in v4: - Added support for binary integer operations and test cases - Fixed bug to support 8-bit integer vectorization - Fixed several assert errors related to non-multiple of two vector modes Changes in v3: - Removed the cost model and cost hooks based on feedback from Richard Biener - Used RVV_VUNDEF macro to fix failing patterns Changes in v2 - Updated ChangeLog entry to include RiVAI contributions - Fixed ChangeLog email formatting - Fixed gnu formatting issues in the code Kevin Lee (1): RISC-V:autovec: This patch supports 8 bit auto-vectorization in riscv. Michael Collison (8): RISC-V: Add new predicates and function prototypes RISC-V: autovec: Export policy functions to global scope RISC-V:autovec: Add auto-vectorization support functions RISC-V:autovec: Add target vectorization hooks RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store RISC-V:autovec: Add autovectorization tests for add & sub vect: Verify that GET_MODE_NUNITS is a multiple of 2. RISC-V:autovec: Add autovectorization tests for binary integer gcc/config/riscv/riscv-opts.h | 10 ++ gcc/config/riscv/riscv-protos.h | 9 ++ gcc/config/riscv/riscv-v.cc | 91 ++++++++++++ gcc/config/riscv/riscv-vector-builtins.cc | 4 +- gcc/config/riscv/riscv-vector-builtins.h | 3 + gcc/config/riscv/riscv.cc | 130 ++++++++++++++++++ gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/vector-auto.md | 74 ++++++++++ gcc/config/riscv/vector.md | 4 +- .../riscv/rvv/autovec/loop-add-rv32.c | 25 ++++ .../gcc.target/riscv/rvv/autovec/loop-add.c | 25 ++++ .../riscv/rvv/autovec/loop-and-rv32.c | 25 ++++ .../gcc.target/riscv/rvv/autovec/loop-and.c | 25 ++++ .../riscv/rvv/autovec/loop-div-rv32.c | 27 ++++ .../gcc.target/riscv/rvv/autovec/loop-div.c | 27 ++++ .../riscv/rvv/autovec/loop-max-rv32.c | 26 ++++ .../gcc.target/riscv/rvv/autovec/loop-max.c | 26 ++++ .../riscv/rvv/autovec/loop-min-rv32.c | 26 ++++ .../gcc.target/riscv/rvv/autovec/loop-min.c | 26 ++++ .../riscv/rvv/autovec/loop-mod-rv32.c | 27 ++++ .../gcc.target/riscv/rvv/autovec/loop-mod.c | 27 ++++ .../riscv/rvv/autovec/loop-mul-rv32.c | 25 ++++ .../gcc.target/riscv/rvv/autovec/loop-mul.c | 25 ++++ .../riscv/rvv/autovec/loop-or-rv32.c | 25 ++++ .../gcc.target/riscv/rvv/autovec/loop-or.c | 25 ++++ .../riscv/rvv/autovec/loop-sub-rv32.c | 25 ++++ .../gcc.target/riscv/rvv/autovec/loop-sub.c | 25 ++++ .../riscv/rvv/autovec/loop-xor-rv32.c | 25 ++++ .../gcc.target/riscv/rvv/autovec/loop-xor.c | 25 ++++ gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 4 + gcc/tree-vect-slp.cc | 7 +- 31 files changed, 843 insertions(+), 6 deletions(-) create mode 100644 gcc/config/riscv/vector-auto.md create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c -- 2.34.1