From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb2c.google.com (mail-yb1-xb2c.google.com [IPv6:2607:f8b0:4864:20::b2c]) by sourceware.org (Postfix) with ESMTPS id 986A238555A4 for ; Fri, 5 May 2023 15:46:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 986A238555A4 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-yb1-xb2c.google.com with SMTP id 3f1490d57ef6-b9a6eec8611so14696698276.0 for ; Fri, 05 May 2023 08:46:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1683301574; x=1685893574; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=PESmz1kZ8w4HZ9xIg8EDswSQZyJiF32Yh9QHCXh0FdI=; b=dRIxqrsY8Ut50ys2o/BHXw3mwRXkdA+c6rOkNCuhZ/EMrOfSmfLrX3CjW+S9NiLSWz gY9FU6STPpZKPUkolpqb9SI00N+aqo6KIR6q/nekoxIpeeH80ga6TDtKb0cdztLvEPv7 NZuKlXl6eFV7cx+1M5EfVE7HASrcUL0cUGebTt/Qqe028sjXImJV4nVDenDpOYcbGFqx U1QAQzUc2VeBnxj5jbTYw+8RBtmWQQgIwuQRtJaYEtPhulOVvN7popWCVbvwZpqFcdQW HRahr03YiqT+V5c9RU3fCBomyem03Io986YfP4tbvoCWqL5QZnwagg5gR+jxzzJw9bS+ bNKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683301574; x=1685893574; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PESmz1kZ8w4HZ9xIg8EDswSQZyJiF32Yh9QHCXh0FdI=; b=RSlURW6FxEk3u642U7UWjZbwvEGanylbyg00qPg/7o43e1BdNudPmXIdhzo32VE52Y ybQN54VJaMBrhlBLrFoLaF2bJe56JOTkJv6Ir9tmlVcsTVAhVaxLsjmo43K7yAcDAn7q GD+SJTxanaEeywIeXIysbrdt9cepxKkdwGqC2BbrUWqKH8EMB9eQShG2f1+IsCMiUZA/ eIZv18chEBF2/RucjjQamxGyJHgyP9ggEblXyZqMQ05p0mfXArKu1PDqE8aYVID63GY7 3NN+SRKIYBqZ5B6bXXinvf1nm3Yvnx6Hd3+uGKhK5wHWGSasiJaJQb/d6NqxyWpYLiNY mz2A== X-Gm-Message-State: AC+VfDzFa7P3FV6sYyYN5XFx50WYbaqVdBEHCzsFuEKSeenm/AAc57Bs rcHV1FJH8pCrYhui7+1o6hBhDYfge2MEssr97fXS/g== X-Google-Smtp-Source: ACHHUZ6gHE4yCmUgmYa/VAfS74V0+nOAccVeMbyJfKJDipMjkwJb3SWrjl/Cq7WjlIYzsyMk3DwKHA== X-Received: by 2002:a81:6d10:0:b0:55a:2084:9e05 with SMTP id i16-20020a816d10000000b0055a20849e05mr2012798ywc.23.1683301573600; Fri, 05 May 2023 08:46:13 -0700 (PDT) Received: from system76-pc.ba.rivosinc.com ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id p203-20020a8174d4000000b0055a3420b25asm542446ywc.50.2023.05.05.08.46.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 08:46:13 -0700 (PDT) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v6 9/9] RISC-V:autovec: This patch supports 8 bit auto-vectorization in riscv. Date: Fri, 5 May 2023 11:46:07 -0400 Message-Id: <20230505154607.1155567-10-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505154607.1155567-1-collison@rivosinc.com> References: <20230505154607.1155567-1-collison@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Kevin Lee 2023-04-14 Kevin Lee gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit type * gcc.target/riscv/rvv/autovec/loop-add.c: Ditto * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-and.c: Ditto * gcc.target/riscv/rvv/autovec/loop-div-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-div.c: Ditto * gcc.target/riscv/rvv/autovec/loop-max-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-max.c: Ditto * gcc.target/riscv/rvv/autovec/loop-min-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-min.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mod-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mod.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mul-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mul.c: Ditto * gcc.target/riscv/rvv/autovec/loop-or-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-or.c: Ditto * gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-sub.c: Ditto * gcc.target/riscv/rvv/autovec/loop-xor-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-xor.c: Ditto --- .../gcc.target/riscv/rvv/autovec/loop-add-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-and-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-div-rv32.c | 10 ++++++---- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c | 10 ++++++---- .../gcc.target/riscv/rvv/autovec/loop-max-rv32.c | 9 +++++---- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c | 9 +++++---- .../gcc.target/riscv/rvv/autovec/loop-min-rv32.c | 9 +++++---- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c | 9 +++++---- .../gcc.target/riscv/rvv/autovec/loop-mod-rv32.c | 10 ++++++---- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c | 10 ++++++---- .../gcc.target/riscv/rvv/autovec/loop-mul-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-or-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-sub-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-xor-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c | 7 ++++--- 20 files changed, 92 insertions(+), 68 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c index bdc3b6892e9..d2765e67d0d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] + b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c index d7f992c7d27..c43f6d3e8cb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] + b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c index eb1ac5b44fd..703f4843c2b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] & b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c index ff0cc2a5df7..ae74e4c6cc5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] & b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c index 21960f265b7..59d379d8647 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] / b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c index bd675b4f6f0..aa8ca21bac9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] / b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c index 751ee9ecaa3..5e44b3f1a5a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c index f4dbf3f04fc..4e4cc3ea97d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c index e51cf590577..128bbed8d79 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c index 304f939f6f9..74e75dd5adc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c index 7c497f6e4cc..23bc5d04bd3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] % b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c index 7508f4a50d1..2b1d57a0cb2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] % b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c index fd6dcbf9c53..6561633536a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] * b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c index 9fce40890ef..08b207f0701 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] * b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c index 305d106abd9..58f7b06b5be 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] | b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c index 501017bc790..7e6b0bed282 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] | b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c index 7d0a40ec539..48ae9411872 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] - b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c index c8900884f83..23a91e38931 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] - b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c index 6a9ffdb11d5..0a65b6261b1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] ^ b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c index c9d7d7f8a75..9bfff8e6701 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -mno-strict-align" } */ #include @@ -10,8 +10,9 @@ dst[i] = a[i] ^ b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */ -- 2.34.1