From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x1135.google.com (mail-yw1-x1135.google.com [IPv6:2607:f8b0:4864:20::1135]) by sourceware.org (Postfix) with ESMTPS id 32B053855586 for ; Fri, 5 May 2023 15:46:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 32B053855586 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-yw1-x1135.google.com with SMTP id 00721157ae682-55a00da4e53so33967857b3.0 for ; Fri, 05 May 2023 08:46:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1683301573; x=1685893573; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WNV6xNtsAvEO3u/hQCvJL6iRLcjTfQe1JwnMUHwzqZ8=; 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2.34.1 In-Reply-To: <20230505154607.1155567-1-collison@rivosinc.com> References: <20230505154607.1155567-1-collison@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: 2023-04-05 Michael Collison * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: New test to verify code generation of vector "and" on rv32. * gcc.target/riscv/rvv/autovec/loop-and.c: New test to verify code generation of vector "and" on rv64. * gcc.target/riscv/rvv/autovec/loop-div-rv32.c: New test to verify code generation of vector divide on rv32. * gcc.target/riscv/rvv/autovec/loop-div.c: New test to verify code generation of vector divide on rv64. * gcc.target/riscv/rvv/autovec/loop-max-rv32.c: New test to verify code generation of vector maximum on rv32. * gcc.target/riscv/rvv/autovec/loop-max.c: New test to verify code generation of vector maximum on rv64. * gcc.target/riscv/rvv/autovec/loop-min-rv32.c: New test to verify code generation of vector minimum on rv32. * gcc.target/riscv/rvv/autovec/loop-min.c: New test to verify code generation of vector minimum on rv64. * gcc.target/riscv/rvv/autovec/loop-mod-rv32.c: New test to verify code generation of vector modulus on rv32. * gcc.target/riscv/rvv/autovec/loop-mod.c: New test to verify code generation of vector modulus on rv64. * gcc.target/riscv/rvv/autovec/loop-mul-rv32.c: New test to verify code generation of vector multiply on rv32. * gcc.target/riscv/rvv/autovec/loop-mul.c: New test to verify code generation of vector multiply on rv64. * gcc.target/riscv/rvv/autovec/loop-or-rv32.c: New test to verify code generation of vector "or" on rv32. * gcc.target/riscv/rvv/autovec/loop-or.c: New test to verify code generation of vector "or" on rv64. * gcc.target/riscv/rvv/autovec/loop-xor-rv32.c: New test to verify code generation of vector xor on rv32. * gcc.target/riscv/rvv/autovec/loop-xor.c: New test to verify code generation of vector xor on rv64. --- .../riscv/rvv/autovec/loop-and-rv32.c | 24 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-and.c | 24 ++++++++++++++++++ .../riscv/rvv/autovec/loop-div-rv32.c | 25 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-div.c | 25 +++++++++++++++++++ .../riscv/rvv/autovec/loop-max-rv32.c | 25 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-max.c | 25 +++++++++++++++++++ .../riscv/rvv/autovec/loop-min-rv32.c | 25 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-min.c | 25 +++++++++++++++++++ .../riscv/rvv/autovec/loop-mod-rv32.c | 25 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-mod.c | 25 +++++++++++++++++++ .../riscv/rvv/autovec/loop-mul-rv32.c | 24 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-mul.c | 24 ++++++++++++++++++ .../riscv/rvv/autovec/loop-or-rv32.c | 24 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-or.c | 24 ++++++++++++++++++ .../riscv/rvv/autovec/loop-xor-rv32.c | 24 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/loop-xor.c | 24 ++++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 4 +++ 17 files changed, 396 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c new file mode 100644 index 00000000000..eb1ac5b44fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vand_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] & b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c new file mode 100644 index 00000000000..ff0cc2a5df7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vand_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] & b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c new file mode 100644 index 00000000000..21960f265b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vdiv_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] / b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c new file mode 100644 index 00000000000..bd675b4f6f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vdiv_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] / b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c new file mode 100644 index 00000000000..751ee9ecaa3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmax_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c new file mode 100644 index 00000000000..f4dbf3f04fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmax_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c new file mode 100644 index 00000000000..e51cf590577 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmin_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c new file mode 100644 index 00000000000..304f939f6f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmin_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c new file mode 100644 index 00000000000..7c497f6e4cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmod_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] % b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c new file mode 100644 index 00000000000..7508f4a50d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vmod_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] % b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c new file mode 100644 index 00000000000..fd6dcbf9c53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] * b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c new file mode 100644 index 00000000000..9fce40890ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] * b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c new file mode 100644 index 00000000000..305d106abd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] | b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c new file mode 100644 index 00000000000..501017bc790 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] | b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c new file mode 100644 index 00000000000..6a9ffdb11d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vxor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] ^ b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c new file mode 100644 index 00000000000..c9d7d7f8a75 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void vxor_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \ + { \ + for (int i = 0; i < n; i++) \ + dst[i] = a[i] ^ b[i]; \ + } + +/* *int8_t not autovec currently. */ +#define TEST_ALL() \ + TEST_TYPE(int16_t) \ + TEST_TYPE(uint16_t) \ + TEST_TYPE(int32_t) \ + TEST_TYPE(uint32_t) \ + TEST_TYPE(int64_t) \ + TEST_TYPE(uint64_t) + +TEST_ALL() + +/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 4b5509db385..60b620b0875 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -42,10 +42,14 @@ dg-init # Main loop. set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3" +set AUTOVECFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -O2 -fno-vect-cost-model -std=c99" + dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \ "" $CFLAGS gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \ "" $CFLAGS +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \ + "" $AUTOVECFLAGS # All done. dg-finish -- 2.34.1