From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [52.229.205.26]) by sourceware.org (Postfix) with ESMTP id 3B54B3858D35 for ; Sat, 6 May 2023 08:40:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3B54B3858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from localhost.localdomain (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id EwgMCgDXdcVhElZkT0cSAA--.58786S4; Sat, 06 May 2023 16:40:02 +0800 (CST) From: Fei Gao To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, sinan.lin@linux.alibaba.com, jiawei@iscas.ac.cn, liaozhangjin@eswincomputing.com, Fei Gao Subject: [PATCH 0/2] RISC-V: support Zcmp extension Date: Sat, 6 May 2023 08:39:37 +0000 Message-Id: <20230506083939.22097-1-gaofei@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID:EwgMCgDXdcVhElZkT0cSAA--.58786S4 X-Coremail-Antispam: 1UD129KBjvJXoWxGr43Zw4kGF4xuFWrCrW5GFg_yoWrWr4UpF W5Xr1Skaykta1xJwsaqFWUGw4rXrsY9rW5Cr4Sqw1jyrW5AFyrAFyktw4fur15AF98tw45 u3W29F1ru39FyrDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUoOJ5UUUUU X-CM-SenderInfo: xjdrwv3l6h245lqf0zpsxwx03jof0z/ X-Spam-Status: No, score=-3.6 required=5.0 tests=BAYES_00,KAM_DMARC_STATUS,KAM_SHORT,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Before implementing Zcmp, I did some optimizations and restructures to save-restore. https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=a5b2a3bff8152aa34408d8ce40add82f4d22ff87 https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=60524be1e3929d83e15fceac6e2aa053c8a6fb20 https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=a782346757c54a5a3cfb9f416a7ebe3554a617d7 Then Zcmp can share the same logic as save-restore in stack allocation: pre-allocation by cm.push, step 1 and step 2. please be noted cm.push pushes ra, s0-s11 in reverse order than what save-restore does. So adaption has been done in .cfi directives in my patch. A discussion be found here: https://github.com/riscv/riscv-code-size-reduction/issues/182 Weeks before, Jiawei also posted Zcmp in https://gcc.gnu.org/pipermail/gcc-patches/2023-April/615287.html. [PATCH 0/5] RISC-V: Support ZC* extensions. Jiawei [PATCH 1/5] RISC-V: Minimal support for ZC extensions. Jiawei [PATCH 2/5] RISC-V: Enable compressible features when use ZC* extensions. Jiawei [PATCH 3/5] RISC-V: Add ZC* test for march args being passed. Jiawei [PATCH 4/5] RISC-V: Add Zcmp extension supports. Jiawei [PATCH 5/5] RISC-V: Add ZCMP push/pop testcases. Jiawei I tested his codes and observed some issues in [PATCH 4/5]. So I plan to post my codes as an alternative of Jiawei's [PATCH 4/5]. My Zcmp switch codes are almost same as Jiawei's. So i avoid repeating them in my patch series, but please pick up Jiawei's [PATCH 1/5] before picking up my patch series. Here're some comparison. Result left side is REF from Jiawei and right side is from my patch. 1. REF fails to generate zcmp insns. TC rv32e_zcmp.c foo: foo: addi sp,sp,-12 cm.push {ra}, -16 sw ra,8(sp) call f1 call f1 lw ra,8(sp) cm.pop {ra}, 16 addi sp,sp,12 tail f2 tail f2 2. REF fails to restore regs. TC rv32i_zcmp.c test_f0: test_f0: cm.push {ra,s0},-32 cm.push {ra, s0}, -32 fsw fs0,12(sp) fsw fs0,12(sp) call my_getchar call my_getchar mv s0,a0 mv s0,a0 call getf call getf fmv.s fs0,fa0 fmv.s fs0,fa0 call my_getchar call my_getchar fcvt.s.w fa5,s0 fcvt.s.w fa5,s0 fcvt.s.w fa4,a0 fcvt.s.w fa4,a0 fadd.s fa0,fa5,fs0 fadd.s fa0,fa5,fs0 flw fs0,-20(sp) //issue in restoring fs0 flw fs0,12(sp) fadd.s fa0,fa0,fa4 fadd.s fa0,fa0,fa4 fcvt.w.s a0,fa0,rtz fcvt.w.s a0,fa0,rtz cm.popret {ra,s0},32 cm.popret {ra, s0}, 32 3. REF accesses incorrect address of incoming para. TC: zcmp_stack_alignment.c fool_rv32e: fool_rv32e: cm.push {ra,s0-s1},-32 cm.push {ra, s0-s1}, -32 mv s0,a0 sw a1,12(sp) sw a1,12(sp) mv s0,a0 sw a2,8(sp) sw a2,8(sp) sw a3,4(sp) sw a3,4(sp) sw a4,0(sp) sw a4,0(sp) mv s1,a5 mv s1,a5 call bar call bar lw a1,12(sp) lw a1,12(sp) lw a2,8(sp) lw a2,8(sp) lw a3,4(sp) lw a3,4(sp) lw a4,0(sp) lw a4,0(sp) add a0,s0,a1 add a0,s0,a1 add a2,a0,a2 add a2,a0,a2 add a3,a2,a3 add a3,a2,a3 lw a0,28(sp) //issue in accessing incoming para lw a0,32(sp) add a4,a3,a4 add a4,a3,a4 add a4,a4,s1 add a4,a4,s1 add a0,a4,a0 add a0,a4,a0 cm.popret {ra,s0-s1},32 cm.popret {ra, s0-s1}, 32 Fei Gao (2): [RISC-V] disable shrink-wrap-separate if zcmp enabled. [RISC-V] support cm.push cm.pop cm.popret in zcmp gcc/config/riscv/predicates.md | 6 + gcc/config/riscv/riscv-protos.h | 3 + gcc/config/riscv/riscv.cc | 403 ++++++++++++++++-- gcc/config/riscv/riscv.h | 26 ++ gcc/config/riscv/riscv.md | 7 + gcc/config/riscv/zc.md | 55 +++ gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c | 239 +++++++++++ gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c | 239 +++++++++++ .../gcc.target/riscv/zcmp_stack_alignment.c | 23 + 9 files changed, 960 insertions(+), 41 deletions(-) create mode 100644 gcc/config/riscv/zc.md create mode 100644 gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c create mode 100644 gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c create mode 100644 gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c -- 2.17.1