* [PATCH v2] RISC-V: Fix CTZ unnecessary sign extension [PR #106888]
@ 2023-05-08 14:12 Raphael Moreira Zinsly
2023-05-08 21:59 ` Jeff Law
2023-05-20 2:55 ` Jeff Law
0 siblings, 2 replies; 3+ messages in thread
From: Raphael Moreira Zinsly @ 2023-05-08 14:12 UTC (permalink / raw)
To: gcc-patches; +Cc: jeffreyalaw, vineetg, shihua, Raphael Moreira Zinsly
Changes since v1:
- Remove subreg from operand 1.
-- >8 --
We were not able to match the CTZ sign extend pattern on RISC-V
because it gets optimized to zero extend and/or to ANDI patterns.
For the ANDI case, combine scrambles the RTL and generates the
extension by using subregs.
gcc/ChangeLog:
PR target/106888
* config/riscv/bitmanip.md
(<bitmanip_optab>disi2): Match with any_extend.
(<bitmanip_optab>disi2_sext): New pattern to match
with sign extend using an ANDI instruction.
gcc/testsuite/ChangeLog:
PR target/106888
* gcc.target/riscv/pr106888.c: New test.
* gcc.target/riscv/zbbw.c: Check for ANDI.
---
gcc/config/riscv/bitmanip.md | 13 ++++++++++++-
gcc/testsuite/gcc.target/riscv/pr106888.c | 12 ++++++++++++
gcc/testsuite/gcc.target/riscv/zbbw.c | 1 +
3 files changed, 25 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/pr106888.c
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index a27fc3e34a1..064b8f7df8c 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -246,13 +246,24 @@
(define_insn "*<bitmanip_optab>disi2"
[(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extend:DI
+ (any_extend:DI
(clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))]
"TARGET_64BIT && TARGET_ZBB"
"<bitmanip_insn>w\t%0,%1"
[(set_attr "type" "<bitmanip_insn>")
(set_attr "mode" "SI")])
+;; A SImode clz_ctz_pcnt may be extended to DImode via subreg.
+(define_insn "*<bitmanip_optab>disi2_sext"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (and:DI (subreg:DI
+ (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")) 0)
+ (match_operand:DI 2 "const_int_operand")))]
+ "TARGET_64BIT && TARGET_ZBB && ((INTVAL (operands[2]) & 0x3f) == 0x3f)"
+ "<bitmanip_insn>w\t%0,%1"
+ [(set_attr "type" "bitmanip")
+ (set_attr "mode" "SI")])
+
(define_insn "*<bitmanip_optab>di2"
[(set (match_operand:DI 0 "register_operand" "=r")
(clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
diff --git a/gcc/testsuite/gcc.target/riscv/pr106888.c b/gcc/testsuite/gcc.target/riscv/pr106888.c
new file mode 100644
index 00000000000..77fb8e5b79c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr106888.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */
+
+int
+ctz (int i)
+{
+ int res = __builtin_ctz (i);
+ return res&0xffff;
+}
+
+/* { dg-final { scan-assembler-times "ctzw" 1 } } */
+/* { dg-final { scan-assembler-not "andi" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c
index 709743c3b68..f7b2b63853f 100644
--- a/gcc/testsuite/gcc.target/riscv/zbbw.c
+++ b/gcc/testsuite/gcc.target/riscv/zbbw.c
@@ -23,3 +23,4 @@ popcount (int i)
/* { dg-final { scan-assembler-times "clzw" 1 } } */
/* { dg-final { scan-assembler-times "ctzw" 1 } } */
/* { dg-final { scan-assembler-times "cpopw" 1 } } */
+/* { dg-final { scan-assembler-not "andi\t" } } */
--
2.40.0
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] RISC-V: Fix CTZ unnecessary sign extension [PR #106888]
2023-05-08 14:12 [PATCH v2] RISC-V: Fix CTZ unnecessary sign extension [PR #106888] Raphael Moreira Zinsly
@ 2023-05-08 21:59 ` Jeff Law
2023-05-20 2:55 ` Jeff Law
1 sibling, 0 replies; 3+ messages in thread
From: Jeff Law @ 2023-05-08 21:59 UTC (permalink / raw)
To: Raphael Moreira Zinsly, gcc-patches; +Cc: vineetg, shihua
On 5/8/23 08:12, Raphael Moreira Zinsly wrote:
> Changes since v1:
> - Remove subreg from operand 1.
>
> -- >8 --
>
> We were not able to match the CTZ sign extend pattern on RISC-V
> because it gets optimized to zero extend and/or to ANDI patterns.
> For the ANDI case, combine scrambles the RTL and generates the
> extension by using subregs.
>
> gcc/ChangeLog:
> PR target/106888
> * config/riscv/bitmanip.md
> (<bitmanip_optab>disi2): Match with any_extend.
> (<bitmanip_optab>disi2_sext): New pattern to match
> with sign extend using an ANDI instruction.
>
> gcc/testsuite/ChangeLog:
> PR target/106888
> * gcc.target/riscv/pr106888.c: New test.
> * gcc.target/riscv/zbbw.c: Check for ANDI.
OK
jeff
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] RISC-V: Fix CTZ unnecessary sign extension [PR #106888]
2023-05-08 14:12 [PATCH v2] RISC-V: Fix CTZ unnecessary sign extension [PR #106888] Raphael Moreira Zinsly
2023-05-08 21:59 ` Jeff Law
@ 2023-05-20 2:55 ` Jeff Law
1 sibling, 0 replies; 3+ messages in thread
From: Jeff Law @ 2023-05-20 2:55 UTC (permalink / raw)
To: Raphael Moreira Zinsly, gcc-patches; +Cc: vineetg, shihua
On 5/8/23 08:12, Raphael Moreira Zinsly wrote:
> Changes since v1:
> - Remove subreg from operand 1.
>
> -- >8 --
>
> We were not able to match the CTZ sign extend pattern on RISC-V
> because it gets optimized to zero extend and/or to ANDI patterns.
> For the ANDI case, combine scrambles the RTL and generates the
> extension by using subregs.
>
> gcc/ChangeLog:
> PR target/106888
> * config/riscv/bitmanip.md
> (<bitmanip_optab>disi2): Match with any_extend.
> (<bitmanip_optab>disi2_sext): New pattern to match
> with sign extend using an ANDI instruction.
>
> gcc/testsuite/ChangeLog:
> PR target/106888
> * gcc.target/riscv/pr106888.c: New test.
> * gcc.target/riscv/zbbw.c: Check for ANDI.
THanks. I went ahead and retested this against the trunk and pushed it.
jeff
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-05-08 14:12 [PATCH v2] RISC-V: Fix CTZ unnecessary sign extension [PR #106888] Raphael Moreira Zinsly
2023-05-08 21:59 ` Jeff Law
2023-05-20 2:55 ` Jeff Law
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