From: Richard Sandiford <richard.sandiford@arm.com>
To: gcc-patches@gcc.gnu.org
Cc: Richard Sandiford <richard.sandiford@arm.com>
Subject: [PATCH 0/6] aarch64: Avoid hard-coding specific register allocations
Date: Tue, 9 May 2023 07:48:25 +0100 [thread overview]
Message-ID: <20230509064831.1651327-1-richard.sandiford@arm.com> (raw)
I have a patch that seems to improve register allocation for SIMD
lane operations, and for similar instructions that require a reduced
register range. However, it showed that a lot of asm tests are
sensitive to the current register allocation. This patch series
tries to correct the affected cases. Putting it in first is an
attempt to “prove” that the new tests work both ways.
Tested on aarch64-linux-gnu and pushed.
Richard
Richard Sandiford (6):
aarch64: Fix move-after-intrinsic function-body tests
aarch64: Allow moves after tied-register intrinsics
aarch64: Relax ordering requirements in SVE dup tests
aarch64: Relax predicate register matches
aarch64: Relax FP/vector register matches
aarch64: Avoid hard-coding specific register allocations
.../g++.target/aarch64/sve/vcond_1.C | 258 +++++++++---------
.../advsimd-intrinsics/bfcvtnq2-untied.c | 5 +
.../aarch64/advsimd-intrinsics/bfdot-1.c | 10 +
.../aarch64/advsimd-intrinsics/vdot-3-1.c | 10 +
.../aarch64/advsimd-intrinsics/vshl-opt-6.c | 2 +-
.../gcc.target/aarch64/asimd-mul-to-shl-sub.c | 4 +-
.../gcc.target/aarch64/asm-x-constraint-1.c | 4 +-
.../gcc.target/aarch64/auto-init-padding-1.c | 2 +-
.../gcc.target/aarch64/auto-init-padding-2.c | 3 +-
.../gcc.target/aarch64/auto-init-padding-3.c | 3 +-
.../gcc.target/aarch64/auto-init-padding-4.c | 3 +-
.../gcc.target/aarch64/auto-init-padding-9.c | 2 +-
.../gcc.target/aarch64/fmul_fcvt_2.c | 6 +-
gcc/testsuite/gcc.target/aarch64/ldp_stp_17.c | 2 +-
gcc/testsuite/gcc.target/aarch64/ldp_stp_21.c | 2 +-
gcc/testsuite/gcc.target/aarch64/ldp_stp_8.c | 2 +-
.../gcc.target/aarch64/memset-corner-cases.c | 22 +-
.../gcc.target/aarch64/memset-q-reg.c | 22 +-
.../gcc.target/aarch64/simd/vaddlv_1.c | 24 +-
.../gcc.target/aarch64/simd/vpaddd_f64.c | 2 +-
.../gcc.target/aarch64/simd/vpaddd_s64.c | 2 +-
.../gcc.target/aarch64/simd/vpaddd_u64.c | 2 +-
.../gcc.target/aarch64/sve-neon-modes_1.c | 4 +-
.../gcc.target/aarch64/sve-neon-modes_3.c | 16 +-
.../aarch64/sve/acle/asm/adda_f16.c | 5 +
.../aarch64/sve/acle/asm/adda_f32.c | 5 +
.../aarch64/sve/acle/asm/adda_f64.c | 5 +
.../gcc.target/aarch64/sve/acle/asm/brka_b.c | 5 +
.../gcc.target/aarch64/sve/acle/asm/brkb_b.c | 5 +
.../gcc.target/aarch64/sve/acle/asm/brkn_b.c | 5 +
.../aarch64/sve/acle/asm/clasta_bf16.c | 5 +
.../aarch64/sve/acle/asm/clasta_f16.c | 5 +
.../aarch64/sve/acle/asm/clasta_f32.c | 5 +
.../aarch64/sve/acle/asm/clasta_f64.c | 5 +
.../aarch64/sve/acle/asm/clastb_bf16.c | 5 +
.../aarch64/sve/acle/asm/clastb_f16.c | 5 +
.../aarch64/sve/acle/asm/clastb_f32.c | 5 +
.../aarch64/sve/acle/asm/clastb_f64.c | 5 +
.../gcc.target/aarch64/sve/acle/asm/dup_s16.c | 72 +++++
.../gcc.target/aarch64/sve/acle/asm/dup_s32.c | 60 ++++
.../gcc.target/aarch64/sve/acle/asm/dup_s64.c | 60 ++++
.../gcc.target/aarch64/sve/acle/asm/dup_u16.c | 72 +++++
.../gcc.target/aarch64/sve/acle/asm/dup_u32.c | 60 ++++
.../gcc.target/aarch64/sve/acle/asm/dup_u64.c | 60 ++++
.../aarch64/sve/acle/asm/dupq_b16.c | 86 +++---
.../aarch64/sve/acle/asm/dupq_b32.c | 48 ++--
.../aarch64/sve/acle/asm/dupq_b64.c | 16 +-
.../gcc.target/aarch64/sve/acle/asm/dupq_b8.c | 136 ++++-----
.../aarch64/sve/acle/asm/pfirst_b.c | 5 +
.../aarch64/sve/acle/asm/pnext_b16.c | 5 +
.../aarch64/sve/acle/asm/pnext_b32.c | 5 +
.../aarch64/sve/acle/asm/pnext_b64.c | 5 +
.../aarch64/sve/acle/asm/pnext_b8.c | 5 +
.../aarch64/sve/acle/general/whilele_10.c | 2 +-
.../aarch64/sve/acle/general/whilele_5.c | 10 +-
.../aarch64/sve/acle/general/whilele_6.c | 2 +-
.../aarch64/sve/acle/general/whilele_7.c | 6 +-
.../aarch64/sve/acle/general/whilele_9.c | 6 +-
.../aarch64/sve/acle/general/whilelt_1.c | 10 +-
.../aarch64/sve/acle/general/whilelt_2.c | 2 +-
.../aarch64/sve/acle/general/whilelt_3.c | 6 +-
gcc/testsuite/gcc.target/aarch64/sve/adr_1.c | 24 +-
gcc/testsuite/gcc.target/aarch64/sve/adr_2.c | 24 +-
gcc/testsuite/gcc.target/aarch64/sve/adr_3.c | 24 +-
gcc/testsuite/gcc.target/aarch64/sve/adr_4.c | 6 +-
gcc/testsuite/gcc.target/aarch64/sve/adr_5.c | 16 +-
.../gcc.target/aarch64/sve/extract_1.c | 4 +-
.../gcc.target/aarch64/sve/extract_2.c | 4 +-
.../gcc.target/aarch64/sve/extract_3.c | 4 +-
.../gcc.target/aarch64/sve/extract_4.c | 4 +-
.../aarch64/sve/load_scalar_offset_1.c | 8 +-
.../aarch64/sve/mask_gather_load_6.c | 4 +-
.../aarch64/sve/pcs/args_5_be_bf16.c | 18 +-
.../aarch64/sve/pcs/args_5_be_f16.c | 18 +-
.../aarch64/sve/pcs/args_5_be_f32.c | 18 +-
.../aarch64/sve/pcs/args_5_be_f64.c | 18 +-
.../aarch64/sve/pcs/args_5_be_s16.c | 18 +-
.../aarch64/sve/pcs/args_5_be_s32.c | 18 +-
.../aarch64/sve/pcs/args_5_be_s64.c | 18 +-
.../gcc.target/aarch64/sve/pcs/args_5_be_s8.c | 18 +-
.../aarch64/sve/pcs/args_5_be_u16.c | 18 +-
.../aarch64/sve/pcs/args_5_be_u32.c | 18 +-
.../aarch64/sve/pcs/args_5_be_u64.c | 18 +-
.../gcc.target/aarch64/sve/pcs/args_5_be_u8.c | 18 +-
.../aarch64/sve/pcs/return_6_1024.c | 48 ++--
.../aarch64/sve/pcs/return_6_2048.c | 48 ++--
.../gcc.target/aarch64/sve/pcs/return_6_256.c | 48 ++--
.../gcc.target/aarch64/sve/pcs/return_6_512.c | 48 ++--
.../gcc.target/aarch64/sve/pcs/return_9.c | 16 +-
.../gcc.target/aarch64/sve/pcs/varargs_1.c | 8 +-
.../gcc.target/aarch64/sve/peel_ind_2.c | 2 +-
.../gcc.target/aarch64/sve/pr89007-1.c | 2 +-
.../gcc.target/aarch64/sve/pr89007-2.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/slp_4.c | 2 +-
.../gcc.target/aarch64/sve/spill_3.c | 8 +-
.../aarch64/sve/store_scalar_offset_1.c | 8 +-
.../gcc.target/aarch64/sve/vcond_18.c | 14 +-
.../gcc.target/aarch64/sve/vcond_19.c | 34 +--
.../gcc.target/aarch64/sve/vcond_2.c | 248 ++++++++---------
.../gcc.target/aarch64/sve/vcond_20.c | 34 +--
.../gcc.target/aarch64/sve/vcond_3.c | 26 +-
.../gcc.target/aarch64/sve/vcond_7.c | 198 +++++++-------
.../aarch64/sve2/acle/asm/aesd_u8.c | 4 +-
.../aarch64/sve2/acle/asm/aese_u8.c | 4 +-
.../aarch64/sve2/acle/asm/aesimc_u8.c | 2 +-
.../aarch64/sve2/acle/asm/aesmc_u8.c | 2 +-
.../aarch64/sve2/acle/asm/sli_s16.c | 15 +
.../aarch64/sve2/acle/asm/sli_s32.c | 15 +
.../aarch64/sve2/acle/asm/sli_s64.c | 15 +
.../gcc.target/aarch64/sve2/acle/asm/sli_s8.c | 15 +
.../aarch64/sve2/acle/asm/sli_u16.c | 15 +
.../aarch64/sve2/acle/asm/sli_u32.c | 15 +
.../aarch64/sve2/acle/asm/sli_u64.c | 15 +
.../gcc.target/aarch64/sve2/acle/asm/sli_u8.c | 15 +
.../aarch64/sve2/acle/asm/sm4e_u32.c | 2 +-
.../aarch64/sve2/acle/asm/sri_s16.c | 15 +
.../aarch64/sve2/acle/asm/sri_s32.c | 15 +
.../aarch64/sve2/acle/asm/sri_s64.c | 15 +
.../gcc.target/aarch64/sve2/acle/asm/sri_s8.c | 15 +
.../aarch64/sve2/acle/asm/sri_u16.c | 15 +
.../aarch64/sve2/acle/asm/sri_u32.c | 15 +
.../aarch64/sve2/acle/asm/sri_u64.c | 15 +
.../gcc.target/aarch64/sve2/acle/asm/sri_u8.c | 15 +
.../gcc.target/aarch64/vadd_reduc-1.c | 4 +-
.../gcc.target/aarch64/vadd_reduc-2.c | 4 +-
gcc/testsuite/gcc.target/aarch64/vfp-1.c | 4 +-
126 files changed, 1680 insertions(+), 939 deletions(-)
--
2.25.1
next reply other threads:[~2023-05-09 6:48 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-09 6:48 Richard Sandiford [this message]
2023-05-09 6:48 ` [PATCH 1/6] aarch64: Fix move-after-intrinsic function-body tests Richard Sandiford
2023-05-09 6:48 ` [PATCH 2/6] aarch64: Allow moves after tied-register intrinsics Richard Sandiford
2023-05-15 14:04 ` Kyrylo Tkachov
2023-05-15 14:18 ` Richard Sandiford
2023-05-15 14:22 ` Kyrylo Tkachov
2023-05-15 14:25 ` Richard Sandiford
2023-05-09 6:48 ` [PATCH 3/6] aarch64: Relax ordering requirements in SVE dup tests Richard Sandiford
2023-05-09 6:48 ` [PATCH 4/6] aarch64: Relax predicate register matches Richard Sandiford
2023-05-09 6:48 ` [PATCH 5/6] aarch64: Relax FP/vector " Richard Sandiford
2023-05-09 6:48 ` [PATCH 6/6] aarch64: Avoid hard-coding specific register allocations Richard Sandiford
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