From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 855033858C2B for ; Tue, 9 May 2023 06:49:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 855033858C2B Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BA88C1596; Mon, 8 May 2023 23:49:56 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CF1AE3F5A1; Mon, 8 May 2023 23:49:11 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 6/6] aarch64: Avoid hard-coding specific register allocations Date: Tue, 9 May 2023 07:48:31 +0100 Message-Id: <20230509064831.1651327-7-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230509064831.1651327-1-richard.sandiford@arm.com> References: <20230509064831.1651327-1-richard.sandiford@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-30.3 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Some tests hard-coded specific allocations for temporary registers, whereas the RA should be free to pick anything that doesn't force unnecessary moves or spills. gcc/testsuite/ * gcc.target/aarch64/asimd-mul-to-shl-sub.c: Allow any register allocation for temporary results, rather than requiring specific registers. * gcc.target/aarch64/auto-init-padding-1.c: Likewise. * gcc.target/aarch64/auto-init-padding-2.c: Likewise. * gcc.target/aarch64/auto-init-padding-3.c: Likewise. * gcc.target/aarch64/auto-init-padding-4.c: Likewise. * gcc.target/aarch64/auto-init-padding-9.c: Likewise. * gcc.target/aarch64/memset-corner-cases.c: Likewise. * gcc.target/aarch64/memset-q-reg.c: Likewise. * gcc.target/aarch64/simd/vaddlv_1.c: Likewise. * gcc.target/aarch64/sve-neon-modes_1.c: Likewise. * gcc.target/aarch64/sve-neon-modes_3.c: Likewise. * gcc.target/aarch64/sve/load_scalar_offset_1.c: Likewise. * gcc.target/aarch64/sve/pcs/return_6_256.c: Likewise. * gcc.target/aarch64/sve/pcs/return_6_512.c: Likewise. * gcc.target/aarch64/sve/pcs/return_6_1024.c: Likewise. * gcc.target/aarch64/sve/pcs/return_6_2048.c: Likewise. * gcc.target/aarch64/sve/pr89007-1.c: Likewise. * gcc.target/aarch64/sve/pr89007-2.c: Likewise. * gcc.target/aarch64/sve/store_scalar_offset_1.c: Likewise. * gcc.target/aarch64/vadd_reduc-1.c: Likewise. * gcc.target/aarch64/vadd_reduc-2.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_bf16.c: Allow the temporary predicate register to be any of p4-p7, rather than requiring p4 specifically. * gcc.target/aarch64/sve/pcs/args_5_be_f16.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_f32.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_f64.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_s8.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_s16.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_s32.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_s64.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_u8.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_u16.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_u32.c: Likewise. * gcc.target/aarch64/sve/pcs/args_5_be_u64.c: Likewise. --- .../gcc.target/aarch64/asimd-mul-to-shl-sub.c | 4 +- .../gcc.target/aarch64/auto-init-padding-1.c | 2 +- .../gcc.target/aarch64/auto-init-padding-2.c | 3 +- .../gcc.target/aarch64/auto-init-padding-3.c | 3 +- .../gcc.target/aarch64/auto-init-padding-4.c | 3 +- .../gcc.target/aarch64/auto-init-padding-9.c | 2 +- .../gcc.target/aarch64/memset-corner-cases.c | 22 ++++----- .../gcc.target/aarch64/memset-q-reg.c | 22 ++++----- .../gcc.target/aarch64/simd/vaddlv_1.c | 24 +++++----- .../gcc.target/aarch64/sve-neon-modes_1.c | 4 +- .../gcc.target/aarch64/sve-neon-modes_3.c | 16 +++---- .../aarch64/sve/load_scalar_offset_1.c | 8 ++-- .../aarch64/sve/pcs/args_5_be_bf16.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_f16.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_f32.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_f64.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_s16.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_s32.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_s64.c | 18 +++---- .../gcc.target/aarch64/sve/pcs/args_5_be_s8.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_u16.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_u32.c | 18 +++---- .../aarch64/sve/pcs/args_5_be_u64.c | 18 +++---- .../gcc.target/aarch64/sve/pcs/args_5_be_u8.c | 18 +++---- .../aarch64/sve/pcs/return_6_1024.c | 48 +++++++++---------- .../aarch64/sve/pcs/return_6_2048.c | 48 +++++++++---------- .../gcc.target/aarch64/sve/pcs/return_6_256.c | 48 +++++++++---------- .../gcc.target/aarch64/sve/pcs/return_6_512.c | 48 +++++++++---------- .../gcc.target/aarch64/sve/pr89007-1.c | 2 +- .../gcc.target/aarch64/sve/pr89007-2.c | 2 +- .../aarch64/sve/store_scalar_offset_1.c | 8 ++-- .../gcc.target/aarch64/vadd_reduc-1.c | 4 +- .../gcc.target/aarch64/vadd_reduc-2.c | 4 +- 33 files changed, 269 insertions(+), 272 deletions(-) diff --git a/gcc/testsuite/gcc.target/aarch64/asimd-mul-to-shl-sub.c b/gcc/testsuite/gcc.target/aarch64/asimd-mul-to-shl-sub.c index d7c5e5f341b..28dbe81a37d 100644 --- a/gcc/testsuite/gcc.target/aarch64/asimd-mul-to-shl-sub.c +++ b/gcc/testsuite/gcc.target/aarch64/asimd-mul-to-shl-sub.c @@ -4,8 +4,8 @@ /* **foo: -** shl v1.4s, v0.4s, 16 -** sub v0.4s, v1.4s, v0.4s +** shl (v[0-9]+.4s), v0.4s, 16 +** sub v0.4s, \1, v0.4s ** ret */ #include diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c index d3a88c72454..c747ebdcdf7 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-1.c @@ -14,4 +14,4 @@ int foo () return var.internal1; } -/* { dg-final { scan-assembler-times "stp\tq0, q0," 2 } } */ +/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c index aceceb87fbe..6e280904da1 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-2.c @@ -14,5 +14,4 @@ int foo () return var.internal1; } -/* { dg-final { scan-assembler-times "stp\tq0, q0," 2 } } */ - +/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c index 085c3862921..9ddea58b468 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-3.c @@ -23,5 +23,4 @@ int foo () return var.four.internal1; } -/* { dg-final { scan-assembler-times "stp\tq0, q0," 4 } } */ - +/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 4 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c index 7a6ddbc20ee..75bba82ed34 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-4.c @@ -23,5 +23,4 @@ int foo () return var.four.internal1; } -/* { dg-final { scan-assembler-times "stp\tq0, q0," 5 } } */ - +/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 5 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c index c81e5ff28b0..0f1930f813e 100644 --- a/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c +++ b/gcc/testsuite/gcc.target/aarch64/auto-init-padding-9.c @@ -18,4 +18,4 @@ int foo () return var[2].four; } -/* { dg-final { scan-assembler-times "stp\tq0, q0," 5 } } */ +/* { dg-final { scan-assembler-times {stp\tq[0-9]+, q[0-9]+,} 5 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c b/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c index c43f0199adc..d4c752711f8 100644 --- a/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c +++ b/gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c @@ -29,8 +29,8 @@ set0byte (int64_t *src) /* 35bytes would become 4 scalar instructions. So favour NEON. **set0neon: -** movi v0.4s, 0 -** stp q0, q0, \[x0\] +** movi v([0-9]+).4s, 0 +** stp q\1, q\1, \[x0\] ** str wzr, \[x0, 31\] ** ret */ @@ -56,15 +56,15 @@ set0scalar (int64_t *src) /* 256-bytes expanded **set256byte: -** dup v0.16b, w1 -** stp q0, q0, \[x0\] -** stp q0, q0, \[x0, 32\] -** stp q0, q0, \[x0, 64\] -** stp q0, q0, \[x0, 96\] -** stp q0, q0, \[x0, 128\] -** stp q0, q0, \[x0, 160\] -** stp q0, q0, \[x0, 192\] -** stp q0, q0, \[x0, 224\] +** dup v([0-9]+).16b, w1 +** stp q\1, q\1, \[x0\] +** stp q\1, q\1, \[x0, 32\] +** stp q\1, q\1, \[x0, 64\] +** stp q\1, q\1, \[x0, 96\] +** stp q\1, q\1, \[x0, 128\] +** stp q\1, q\1, \[x0, 160\] +** stp q\1, q\1, \[x0, 192\] +** stp q\1, q\1, \[x0, 224\] ** ret */ void __attribute__((__noinline__)) diff --git a/gcc/testsuite/gcc.target/aarch64/memset-q-reg.c b/gcc/testsuite/gcc.target/aarch64/memset-q-reg.c index 156146badbc..eef5c21f50d 100644 --- a/gcc/testsuite/gcc.target/aarch64/memset-q-reg.c +++ b/gcc/testsuite/gcc.target/aarch64/memset-q-reg.c @@ -6,8 +6,8 @@ /* **set128bits: -** dup v0.16b, w1 -** str q0, \[x0\] +** dup v([0-9]+).16b, w1 +** str q\1, \[x0\] ** ret */ void __attribute__((__noinline__)) @@ -29,9 +29,9 @@ set128bitszero (int64_t *src) /* ** set128bitsplus: -** dup v0.16b, w1 -** str q0, \[x0\] -** str q0, \[x0, 12\] +** dup v([0-9]+).16b, w1 +** str q\1, \[x0\] +** str q\1, \[x0, 12\] ** ret */ void __attribute__((__noinline__)) @@ -42,8 +42,8 @@ set128bitsplus (int64_t *src, char c) /* ** set256bits: -** movi v0.16b, 0x63 -** stp q0, q0, \[x0\] +** movi v([0-9]+).16b, 0x63 +** stp q\1, q\1, \[x0\] ** ret */ void __attribute__((__noinline__)) @@ -66,10 +66,10 @@ set256bitszero (int64_t *src) /* ** set256bitsplus: -** movi v0.16b, 0x63 -** stp q0, q0, \[x0\] -** str q0, \[x0, 32\] -** str d0, \[x0, 48\] +** movi v([0-9]+).16b, 0x63 +** stp q\1, q\1, \[x0\] +** str q\1, \[x0, 32\] +** str d\1, \[x0, 48\] ** ret */ void __attribute__((__noinline__)) diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c index d4afaab5ba5..ef1f13efd2e 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c @@ -12,22 +12,22 @@ foo_##S (IT a) \ } FUNC (int8x8_t, int16_t, s8) -/* { dg-final { scan-assembler-times {saddlv\th0, v0\.8b} 1} } */ +/* { dg-final { scan-assembler-times {saddlv\th[0-9]+, v0\.8b} 1} } */ FUNC (int16x4_t, int32_t, s16) -/* { dg-final { scan-assembler-times {saddlv\ts0, v0\.4h} 1} } */ +/* { dg-final { scan-assembler-times {saddlv\ts[0-9]+, v0\.4h} 1} } */ FUNC (int32x2_t, int64_t, s32) -/* { dg-final { scan-assembler-times {saddlp\tv0\.1d, v0\.2s} 1} } */ +/* { dg-final { scan-assembler-times {saddlp\tv[0-9]+\.1d, v0\.2s} 1} } */ FUNC (uint8x8_t, uint16_t, u8) -/* { dg-final { scan-assembler-times {uaddlv\th0, v0\.8b} 1} } */ +/* { dg-final { scan-assembler-times {uaddlv\th[0-9]+, v0\.8b} 1} } */ FUNC (uint16x4_t, uint32_t, u16) -/* { dg-final { scan-assembler-times {uaddlv\ts0, v0\.4h} 1} } */ +/* { dg-final { scan-assembler-times {uaddlv\ts[0-9]+, v0\.4h} 1} } */ FUNC (uint32x2_t, uint64_t, u32) -/* { dg-final { scan-assembler-times {uaddlp\tv0.1d, v0\.2s} 1} } */ +/* { dg-final { scan-assembler-times {uaddlp\tv[0-9]+\.1d, v0\.2s} 1} } */ #define FUNCQ(IT, OT, S) \ OT \ @@ -37,20 +37,20 @@ fooq_##S (IT a) \ } FUNCQ (int8x16_t, int16_t, s8) -/* { dg-final { scan-assembler-times {saddlv\th0, v0\.16b} 1} } */ +/* { dg-final { scan-assembler-times {saddlv\th[0-9]+, v0\.16b} 1} } */ FUNCQ (int16x8_t, int32_t, s16) -/* { dg-final { scan-assembler-times {saddlv\ts0, v0\.8h} 1} } */ +/* { dg-final { scan-assembler-times {saddlv\ts[0-9]+, v0\.8h} 1} } */ FUNCQ (int32x4_t, int64_t, s32) -/* { dg-final { scan-assembler-times {saddlv\td0, v0\.4s} 1} } */ +/* { dg-final { scan-assembler-times {saddlv\td[0-9]+, v0\.4s} 1} } */ FUNCQ (uint8x16_t, uint16_t, u8) -/* { dg-final { scan-assembler-times {uaddlv\th0, v0\.16b} 1} } */ +/* { dg-final { scan-assembler-times {uaddlv\th[0-9]+, v0\.16b} 1} } */ FUNCQ (uint16x8_t, uint32_t, u16) -/* { dg-final { scan-assembler-times {uaddlv\ts0, v0\.8h} 1} } */ +/* { dg-final { scan-assembler-times {uaddlv\ts[0-9]+, v0\.8h} 1} } */ FUNCQ (uint32x4_t, uint64_t, u32) -/* { dg-final { scan-assembler-times {uaddlv\td0, v0\.4s} 1} } */ +/* { dg-final { scan-assembler-times {uaddlv\td[0-9]+, v0\.4s} 1} } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_1.c b/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_1.c index ce4f1c70bcc..c4019aaf4f9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_1.c @@ -6,8 +6,8 @@ typedef long v2di __attribute__((vector_size (16))); /* ** foo: -** ptrue p0.b, all -** mul z0.d, p0/m, z0.d, z1.d +** ptrue (p[0-7]).b, all +** mul z0.d, \1/m, z0.d, z1.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_3.c b/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_3.c index f1e78a83a9c..f7c93659f4d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_3.c +++ b/gcc/testsuite/gcc.target/aarch64/sve-neon-modes_3.c @@ -9,8 +9,8 @@ typedef unsigned int v4usi __attribute__((vector_size (16))); /* ** food: -** ptrue p0.b, all -** sdiv z0.d, p0/m, z0.d, z1.d +** ptrue (p[0-7]).b, all +** sdiv z0.d, \1/m, z0.d, z1.d ** ret */ @@ -22,8 +22,8 @@ food (v2di a, v2di b) /* ** fooud: -** ptrue p0.b, all -** udiv z0.d, p0/m, z0.d, z1.d +** ptrue (p[0-7]).b, all +** udiv z0.d, \1/m, z0.d, z1.d ** ret */ @@ -35,8 +35,8 @@ fooud (v2udi a, v2udi b) /* ** foos: -** ptrue p0.b, all -** sdiv z0.s, p0/m, z0.s, z1.s +** ptrue (p[0-7]).b, all +** sdiv z0.s, \1/m, z0.s, z1.s ** ret */ @@ -48,8 +48,8 @@ foos (v4si a, v4si b) /* ** foous: -** ptrue p0.b, all -** udiv z0.s, p0/m, z0.s, z1.s +** ptrue (p[0-7]).b, all +** udiv z0.s, \1/m, z0.s, z1.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/load_scalar_offset_1.c b/gcc/testsuite/gcc.target/aarch64/sve/load_scalar_offset_1.c index 32905350c27..4d1f7969f7d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/load_scalar_offset_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/load_scalar_offset_1.c @@ -64,7 +64,7 @@ void sve_load_8_s (int8_t *a) asm volatile ("" :: "w" (*(vnx16qi *)&a[i])); } -/* { dg-final { scan-assembler-times {\tld1d\tz0\.d, p[0-7]/z, \[x0, x1, lsl 3\]\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tld1w\tz0\.s, p[0-7]/z, \[x0, x1, lsl 2\]\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tld1h\tz0\.h, p[0-7]/z, \[x0, x1, lsl 1\]\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tld1b\tz0\.b, p[0-7]/z, \[x0, x1\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d, p[0-7]/z, \[x0, x1, lsl 3\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x0, x1, lsl 2\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.h, p[0-7]/z, \[x0, x1, lsl 1\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1b\tz[0-9]+\.b, p[0-7]/z, \[x0, x1\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c index e9b63a45dc3..4002e047977 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_bf16.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** st2h {\2 - \1}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** st2h {\3 - \2}, p0, \[x0\] ** | -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** st2h {\3 - \4}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** st2h {\4 - \5}, p0, \[x0\] ** ) ** st4h {z0\.h - z3\.h}, p1, \[x0\] ** st3h {z4\.h - z6\.h}, p2, \[x0\] ** st1h z7\.h, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c index 4152f91255a..6faf8a3d547 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f16.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** st2h {\2 - \1}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** st2h {\3 - \2}, p0, \[x0\] ** | -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** st2h {\3 - \4}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** st2h {\4 - \5}, p0, \[x0\] ** ) ** st4h {z0\.h - z3\.h}, p1, \[x0\] ** st3h {z4\.h - z6\.h}, p2, \[x0\] ** st1h z7\.h, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c index 0f78fac7947..7abd279f21f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f32.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1w (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\] -** ld1w (z[0-9]+\.s), p4/z, \[x1\] -** st2w {\2 - \1}, p0, \[x0\] +** ld1w (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\] +** ld1w (z[0-9]+\.s), \1/z, \[x1\] +** st2w {\3 - \2}, p0, \[x0\] ** | -** ld1w (z[0-9]+\.s), p4/z, \[x1\] -** ld1w (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\] -** st2w {\3 - \4}, p0, \[x0\] +** ld1w (z[0-9]+\.s), \1/z, \[x1\] +** ld1w (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\] +** st2w {\4 - \5}, p0, \[x0\] ** ) ** st4w {z0\.s - z3\.s}, p1, \[x0\] ** st3w {z4\.s - z6\.s}, p2, \[x0\] ** st1w z7\.s, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c index fe832d0d0a4..eea79659593 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_f64.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1d (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\] -** ld1d (z[0-9]+\.d), p4/z, \[x1\] -** st2d {\2 - \1}, p0, \[x0\] +** ld1d (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\] +** ld1d (z[0-9]+\.d), \1/z, \[x1\] +** st2d {\3 - \2}, p0, \[x0\] ** | -** ld1d (z[0-9]+\.d), p4/z, \[x1\] -** ld1d (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\] -** st2d {\3 - \4}, p0, \[x0\] +** ld1d (z[0-9]+\.d), \1/z, \[x1\] +** ld1d (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\] +** st2d {\4 - \5}, p0, \[x0\] ** ) ** st4d {z0\.d - z3\.d}, p1, \[x0\] ** st3d {z4\.d - z6\.d}, p2, \[x0\] ** st1d z7\.d, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c index 3f708e0f011..59b17a4c9e3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s16.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** st2h {\2 - \1}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** st2h {\3 - \2}, p0, \[x0\] ** | -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** st2h {\3 - \4}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** st2h {\4 - \5}, p0, \[x0\] ** ) ** st4h {z0\.h - z3\.h}, p1, \[x0\] ** st3h {z4\.h - z6\.h}, p2, \[x0\] ** st1h z7\.h, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c index 8c57190ea56..8988f9c9ba9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s32.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1w (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\] -** ld1w (z[0-9]+\.s), p4/z, \[x1\] -** st2w {\2 - \1}, p0, \[x0\] +** ld1w (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\] +** ld1w (z[0-9]+\.s), \1/z, \[x1\] +** st2w {\3 - \2}, p0, \[x0\] ** | -** ld1w (z[0-9]+\.s), p4/z, \[x1\] -** ld1w (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\] -** st2w {\3 - \4}, p0, \[x0\] +** ld1w (z[0-9]+\.s), \1/z, \[x1\] +** ld1w (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\] +** st2w {\4 - \5}, p0, \[x0\] ** ) ** st4w {z0\.s - z3\.s}, p1, \[x0\] ** st3w {z4\.s - z6\.s}, p2, \[x0\] ** st1w z7\.s, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c index e60d049fbd3..4719b4120e0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s64.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1d (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\] -** ld1d (z[0-9]+\.d), p4/z, \[x1\] -** st2d {\2 - \1}, p0, \[x0\] +** ld1d (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\] +** ld1d (z[0-9]+\.d), \1/z, \[x1\] +** st2d {\3 - \2}, p0, \[x0\] ** | -** ld1d (z[0-9]+\.d), p4/z, \[x1\] -** ld1d (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\] -** st2d {\3 - \4}, p0, \[x0\] +** ld1d (z[0-9]+\.d), \1/z, \[x1\] +** ld1d (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\] +** st2d {\4 - \5}, p0, \[x0\] ** ) ** st4d {z0\.d - z3\.d}, p1, \[x0\] ** st3d {z4\.d - z6\.d}, p2, \[x0\] ** st1d z7\.d, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c index bc0058372cb..995f3e70bf2 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_s8.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1b (z[0-9]+\.b), p4/z, \[x1, #1, mul vl\] -** ld1b (z[0-9]+\.b), p4/z, \[x1\] -** st2b {\2 - \1}, p0, \[x0\] +** ld1b (z[0-9]+\.b), \1/z, \[x1, #1, mul vl\] +** ld1b (z[0-9]+\.b), \1/z, \[x1\] +** st2b {\3 - \2}, p0, \[x0\] ** | -** ld1b (z[0-9]+\.b), p4/z, \[x1\] -** ld1b (z[0-9]+\.b), p4/z, \[x1, #1, mul vl\] -** st2b {\3 - \4}, p0, \[x0\] +** ld1b (z[0-9]+\.b), \1/z, \[x1\] +** ld1b (z[0-9]+\.b), \1/z, \[x1, #1, mul vl\] +** st2b {\4 - \5}, p0, \[x0\] ** ) ** st4b {z0\.b - z3\.b}, p1, \[x0\] ** st3b {z4\.b - z6\.b}, p2, \[x0\] ** st1b z7\.b, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c index 8aa651a415e..0b84622ad4a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u16.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** st2h {\2 - \1}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** st2h {\3 - \2}, p0, \[x0\] ** | -** ld1h (z[0-9]+\.h), p4/z, \[x1\] -** ld1h (z[0-9]+\.h), p4/z, \[x1, #1, mul vl\] -** st2h {\3 - \4}, p0, \[x0\] +** ld1h (z[0-9]+\.h), \1/z, \[x1\] +** ld1h (z[0-9]+\.h), \1/z, \[x1, #1, mul vl\] +** st2h {\4 - \5}, p0, \[x0\] ** ) ** st4h {z0\.h - z3\.h}, p1, \[x0\] ** st3h {z4\.h - z6\.h}, p2, \[x0\] ** st1h z7\.h, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c index 9ea3066edea..a5892f7b63b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u32.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1w (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\] -** ld1w (z[0-9]+\.s), p4/z, \[x1\] -** st2w {\2 - \1}, p0, \[x0\] +** ld1w (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\] +** ld1w (z[0-9]+\.s), \1/z, \[x1\] +** st2w {\3 - \2}, p0, \[x0\] ** | -** ld1w (z[0-9]+\.s), p4/z, \[x1\] -** ld1w (z[0-9]+\.s), p4/z, \[x1, #1, mul vl\] -** st2w {\3 - \4}, p0, \[x0\] +** ld1w (z[0-9]+\.s), \1/z, \[x1\] +** ld1w (z[0-9]+\.s), \1/z, \[x1, #1, mul vl\] +** st2w {\4 - \5}, p0, \[x0\] ** ) ** st4w {z0\.s - z3\.s}, p1, \[x0\] ** st3w {z4\.s - z6\.s}, p2, \[x0\] ** st1w z7\.s, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c index b64f3b6d57b..67438e8e562 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u64.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1d (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\] -** ld1d (z[0-9]+\.d), p4/z, \[x1\] -** st2d {\2 - \1}, p0, \[x0\] +** ld1d (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\] +** ld1d (z[0-9]+\.d), \1/z, \[x1\] +** st2d {\3 - \2}, p0, \[x0\] ** | -** ld1d (z[0-9]+\.d), p4/z, \[x1\] -** ld1d (z[0-9]+\.d), p4/z, \[x1, #1, mul vl\] -** st2d {\3 - \4}, p0, \[x0\] +** ld1d (z[0-9]+\.d), \1/z, \[x1\] +** ld1d (z[0-9]+\.d), \1/z, \[x1, #1, mul vl\] +** st2d {\4 - \5}, p0, \[x0\] ** ) ** st4d {z0\.d - z3\.d}, p1, \[x0\] ** st3d {z4\.d - z6\.d}, p2, \[x0\] ** st1d z7\.d, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c index 5575673aeb3..61d694c6c9c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/args_5_be_u8.c @@ -7,21 +7,21 @@ /* ** callee: ** addvl sp, sp, #-1 -** str p4, \[sp\] -** ptrue p4\.b, all +** str (p[4-7]), \[sp\] +** ptrue \1\.b, all ** ( -** ld1b (z[0-9]+\.b), p4/z, \[x1, #1, mul vl\] -** ld1b (z[0-9]+\.b), p4/z, \[x1\] -** st2b {\2 - \1}, p0, \[x0\] +** ld1b (z[0-9]+\.b), \1/z, \[x1, #1, mul vl\] +** ld1b (z[0-9]+\.b), \1/z, \[x1\] +** st2b {\3 - \2}, p0, \[x0\] ** | -** ld1b (z[0-9]+\.b), p4/z, \[x1\] -** ld1b (z[0-9]+\.b), p4/z, \[x1, #1, mul vl\] -** st2b {\3 - \4}, p0, \[x0\] +** ld1b (z[0-9]+\.b), \1/z, \[x1\] +** ld1b (z[0-9]+\.b), \1/z, \[x1, #1, mul vl\] +** st2b {\4 - \5}, p0, \[x0\] ** ) ** st4b {z0\.b - z3\.b}, p1, \[x0\] ** st3b {z4\.b - z6\.b}, p2, \[x0\] ** st1b z7\.b, p3, \[x0\] -** ldr p4, \[sp\] +** ldr \1, \[sp\] ** addvl sp, sp, #1 ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_1024.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_1024.c index de69d9a42ce..6c716ef7c34 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_1024.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_1024.c @@ -30,8 +30,8 @@ typedef double svfloat64_t __attribute__ ((vector_size (128))); /* ** callee_s8: ** ptrue (p[0-7])\.b, vl128 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (s8, svint8_t) @@ -39,8 +39,8 @@ CALLEE (s8, svint8_t) /* ** callee_u8: ** ptrue (p[0-7])\.b, vl128 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (u8, svuint8_t) @@ -48,8 +48,8 @@ CALLEE (u8, svuint8_t) /* ** callee_s16: ** ptrue (p[0-7])\.b, vl128 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (s16, svint16_t) @@ -57,8 +57,8 @@ CALLEE (s16, svint16_t) /* ** callee_u16: ** ptrue (p[0-7])\.b, vl128 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (u16, svuint16_t) @@ -66,8 +66,8 @@ CALLEE (u16, svuint16_t) /* ** callee_f16: ** ptrue (p[0-7])\.b, vl128 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (f16, svfloat16_t) @@ -75,8 +75,8 @@ CALLEE (f16, svfloat16_t) /* ** callee_bf16: ** ptrue (p[0-7])\.b, vl128 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (bf16, svbfloat16_t) @@ -84,8 +84,8 @@ CALLEE (bf16, svbfloat16_t) /* ** callee_s32: ** ptrue (p[0-7])\.b, vl128 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (s32, svint32_t) @@ -93,8 +93,8 @@ CALLEE (s32, svint32_t) /* ** callee_u32: ** ptrue (p[0-7])\.b, vl128 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (u32, svuint32_t) @@ -102,8 +102,8 @@ CALLEE (u32, svuint32_t) /* ** callee_f32: ** ptrue (p[0-7])\.b, vl128 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (f32, svfloat32_t) @@ -111,8 +111,8 @@ CALLEE (f32, svfloat32_t) /* ** callee_s64: ** ptrue (p[0-7])\.b, vl128 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (s64, svint64_t) @@ -120,8 +120,8 @@ CALLEE (s64, svint64_t) /* ** callee_u64: ** ptrue (p[0-7])\.b, vl128 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (u64, svuint64_t) @@ -129,8 +129,8 @@ CALLEE (u64, svuint64_t) /* ** callee_f64: ** ptrue (p[0-7])\.b, vl128 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (f64, svfloat64_t) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_2048.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_2048.c index 0b64ff2e8c2..0eb9607d9db 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_2048.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_2048.c @@ -30,8 +30,8 @@ typedef double svfloat64_t __attribute__ ((vector_size (256))); /* ** callee_s8: ** ptrue (p[0-7])\.b, vl256 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (s8, svint8_t) @@ -39,8 +39,8 @@ CALLEE (s8, svint8_t) /* ** callee_u8: ** ptrue (p[0-7])\.b, vl256 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (u8, svuint8_t) @@ -48,8 +48,8 @@ CALLEE (u8, svuint8_t) /* ** callee_s16: ** ptrue (p[0-7])\.b, vl256 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (s16, svint16_t) @@ -57,8 +57,8 @@ CALLEE (s16, svint16_t) /* ** callee_u16: ** ptrue (p[0-7])\.b, vl256 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (u16, svuint16_t) @@ -66,8 +66,8 @@ CALLEE (u16, svuint16_t) /* ** callee_f16: ** ptrue (p[0-7])\.b, vl256 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (f16, svfloat16_t) @@ -75,8 +75,8 @@ CALLEE (f16, svfloat16_t) /* ** callee_bf16: ** ptrue (p[0-7])\.b, vl256 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (bf16, svbfloat16_t) @@ -84,8 +84,8 @@ CALLEE (bf16, svbfloat16_t) /* ** callee_s32: ** ptrue (p[0-7])\.b, vl256 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (s32, svint32_t) @@ -93,8 +93,8 @@ CALLEE (s32, svint32_t) /* ** callee_u32: ** ptrue (p[0-7])\.b, vl256 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (u32, svuint32_t) @@ -102,8 +102,8 @@ CALLEE (u32, svuint32_t) /* ** callee_f32: ** ptrue (p[0-7])\.b, vl256 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (f32, svfloat32_t) @@ -111,8 +111,8 @@ CALLEE (f32, svfloat32_t) /* ** callee_s64: ** ptrue (p[0-7])\.b, vl256 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (s64, svint64_t) @@ -120,8 +120,8 @@ CALLEE (s64, svint64_t) /* ** callee_u64: ** ptrue (p[0-7])\.b, vl256 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (u64, svuint64_t) @@ -129,8 +129,8 @@ CALLEE (u64, svuint64_t) /* ** callee_f64: ** ptrue (p[0-7])\.b, vl256 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (f64, svfloat64_t) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_256.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_256.c index 9eb71e3dcc3..749eb332599 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_256.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_256.c @@ -30,8 +30,8 @@ typedef double svfloat64_t __attribute__ ((vector_size (32))); /* ** callee_s8: ** ptrue (p[0-7])\.b, vl32 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (s8, svint8_t) @@ -39,8 +39,8 @@ CALLEE (s8, svint8_t) /* ** callee_u8: ** ptrue (p[0-7])\.b, vl32 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (u8, svuint8_t) @@ -48,8 +48,8 @@ CALLEE (u8, svuint8_t) /* ** callee_s16: ** ptrue (p[0-7])\.b, vl32 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (s16, svint16_t) @@ -57,8 +57,8 @@ CALLEE (s16, svint16_t) /* ** callee_u16: ** ptrue (p[0-7])\.b, vl32 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (u16, svuint16_t) @@ -66,8 +66,8 @@ CALLEE (u16, svuint16_t) /* ** callee_f16: ** ptrue (p[0-7])\.b, vl32 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (f16, svfloat16_t) @@ -75,8 +75,8 @@ CALLEE (f16, svfloat16_t) /* ** callee_bf16: ** ptrue (p[0-7])\.b, vl32 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (bf16, svbfloat16_t) @@ -84,8 +84,8 @@ CALLEE (bf16, svbfloat16_t) /* ** callee_s32: ** ptrue (p[0-7])\.b, vl32 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (s32, svint32_t) @@ -93,8 +93,8 @@ CALLEE (s32, svint32_t) /* ** callee_u32: ** ptrue (p[0-7])\.b, vl32 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (u32, svuint32_t) @@ -102,8 +102,8 @@ CALLEE (u32, svuint32_t) /* ** callee_f32: ** ptrue (p[0-7])\.b, vl32 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (f32, svfloat32_t) @@ -111,8 +111,8 @@ CALLEE (f32, svfloat32_t) /* ** callee_s64: ** ptrue (p[0-7])\.b, vl32 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (s64, svint64_t) @@ -120,8 +120,8 @@ CALLEE (s64, svint64_t) /* ** callee_u64: ** ptrue (p[0-7])\.b, vl32 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (u64, svuint64_t) @@ -129,8 +129,8 @@ CALLEE (u64, svuint64_t) /* ** callee_f64: ** ptrue (p[0-7])\.b, vl32 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (f64, svfloat64_t) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_512.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_512.c index 8b8d0c7c860..f6a64cc4944 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_512.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_6_512.c @@ -30,8 +30,8 @@ typedef double svfloat64_t __attribute__ ((vector_size (64))); /* ** callee_s8: ** ptrue (p[0-7])\.b, vl64 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (s8, svint8_t) @@ -39,8 +39,8 @@ CALLEE (s8, svint8_t) /* ** callee_u8: ** ptrue (p[0-7])\.b, vl64 -** ld1b z0\.b, \1/z, \[x0\] -** st1b z0\.b, \1, \[x8\] +** ld1b (z[0-9]+)\.b, \1/z, \[x0\] +** st1b \2\.b, \1, \[x8\] ** ret */ CALLEE (u8, svuint8_t) @@ -48,8 +48,8 @@ CALLEE (u8, svuint8_t) /* ** callee_s16: ** ptrue (p[0-7])\.b, vl64 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (s16, svint16_t) @@ -57,8 +57,8 @@ CALLEE (s16, svint16_t) /* ** callee_u16: ** ptrue (p[0-7])\.b, vl64 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (u16, svuint16_t) @@ -66,8 +66,8 @@ CALLEE (u16, svuint16_t) /* ** callee_f16: ** ptrue (p[0-7])\.b, vl64 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (f16, svfloat16_t) @@ -75,8 +75,8 @@ CALLEE (f16, svfloat16_t) /* ** callee_bf16: ** ptrue (p[0-7])\.b, vl64 -** ld1h z0\.h, \1/z, \[x0\] -** st1h z0\.h, \1, \[x8\] +** ld1h (z[0-9]+)\.h, \1/z, \[x0\] +** st1h \2\.h, \1, \[x8\] ** ret */ CALLEE (bf16, svbfloat16_t) @@ -84,8 +84,8 @@ CALLEE (bf16, svbfloat16_t) /* ** callee_s32: ** ptrue (p[0-7])\.b, vl64 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (s32, svint32_t) @@ -93,8 +93,8 @@ CALLEE (s32, svint32_t) /* ** callee_u32: ** ptrue (p[0-7])\.b, vl64 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (u32, svuint32_t) @@ -102,8 +102,8 @@ CALLEE (u32, svuint32_t) /* ** callee_f32: ** ptrue (p[0-7])\.b, vl64 -** ld1w z0\.s, \1/z, \[x0\] -** st1w z0\.s, \1, \[x8\] +** ld1w (z[0-9]+)\.s, \1/z, \[x0\] +** st1w \2\.s, \1, \[x8\] ** ret */ CALLEE (f32, svfloat32_t) @@ -111,8 +111,8 @@ CALLEE (f32, svfloat32_t) /* ** callee_s64: ** ptrue (p[0-7])\.b, vl64 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (s64, svint64_t) @@ -120,8 +120,8 @@ CALLEE (s64, svint64_t) /* ** callee_u64: ** ptrue (p[0-7])\.b, vl64 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (u64, svuint64_t) @@ -129,8 +129,8 @@ CALLEE (u64, svuint64_t) /* ** callee_f64: ** ptrue (p[0-7])\.b, vl64 -** ld1d z0\.d, \1/z, \[x0\] -** st1d z0\.d, \1, \[x8\] +** ld1d (z[0-9]+)\.d, \1/z, \[x0\] +** st1d \2\.d, \1, \[x8\] ** ret */ CALLEE (f64, svfloat64_t) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr89007-1.c b/gcc/testsuite/gcc.target/aarch64/sve/pr89007-1.c index ff9550c9109..d65aa94a52a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pr89007-1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr89007-1.c @@ -15,7 +15,7 @@ unsigned char in2[N]; ** add (z[0-9]+\.b), (\1, \2|\2, \1) ** orr (z[0-9]+)\.d, z[0-9]+\.d, z[0-9]+\.d ** and (z[0-9]+\.b), \5\.b, #0x1 -** add z0\.b, (\3, \6|\6, \3) +** add z[0-9]+\.b, (\3, \6|\6, \3) ** ... */ void diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr89007-2.c b/gcc/testsuite/gcc.target/aarch64/sve/pr89007-2.c index da345fe8bd6..1de44df96c9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pr89007-2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr89007-2.c @@ -15,7 +15,7 @@ unsigned char in2[N]; ** add (z[0-9]+\.b), (\1, \2|\2, \1) ** and (z[0-9]+)\.d, z[0-9]+\.d, z[0-9]+\.d ** and (z[0-9]+\.b), \5\.b, #0x1 -** add z0\.b, (\3, \6|\6, \3) +** add z[0-9]+\.b, (\3, \6|\6, \3) ** ... */ void diff --git a/gcc/testsuite/gcc.target/aarch64/sve/store_scalar_offset_1.c b/gcc/testsuite/gcc.target/aarch64/sve/store_scalar_offset_1.c index 4f0655f6d7c..c742b92b934 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/store_scalar_offset_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/store_scalar_offset_1.c @@ -49,7 +49,7 @@ void sve_store_8_s (signed long i, int8_t *a) asm volatile ("" : "=w" (*(vnx16qi *) &a[i])); } -/* { dg-final { scan-assembler-times {\tst1d\tz0\.d, p[0-7], \[x0, x1, lsl 3\]\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tst1w\tz0\.s, p[0-7], \[x0, x1, lsl 2\]\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tst1h\tz0\.h, p[0-7], \[x0, x1, lsl 1\]\n} 2 } } */ -/* { dg-final { scan-assembler-times {\tst1b\tz0\.b, p[0-7], \[x1, x0\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1d\tz[0-9]+\.d, p[0-7], \[x0, x1, lsl 3\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1w\tz[0-9]+\.s, p[0-7], \[x0, x1, lsl 2\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1h\tz[0-9]+\.h, p[0-7], \[x0, x1, lsl 1\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst1b\tz[0-9]+\.b, p[0-7], \[x1, x0\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vadd_reduc-1.c b/gcc/testsuite/gcc.target/aarch64/vadd_reduc-1.c index 271a1c3e8c3..c158db3aa39 100644 --- a/gcc/testsuite/gcc.target/aarch64/vadd_reduc-1.c +++ b/gcc/testsuite/gcc.target/aarch64/vadd_reduc-1.c @@ -9,8 +9,8 @@ typedef int v4si __attribute__ ((vector_size (16))); /* **bar: ** ... -** addv s0, v0.4s -** fmov w0, s0 +** addv (s[0-9]+), v0.4s +** fmov w0, \1 ** lsr w1, w0, 16 ** add w0, w1, w0, uxth ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/vadd_reduc-2.c b/gcc/testsuite/gcc.target/aarch64/vadd_reduc-2.c index 0ad96954ff7..b4d4face2e9 100644 --- a/gcc/testsuite/gcc.target/aarch64/vadd_reduc-2.c +++ b/gcc/testsuite/gcc.target/aarch64/vadd_reduc-2.c @@ -9,8 +9,8 @@ /* **test: ** ... -** addv s0, v0.4s -** fmov w0, s0 +** addv (s[0-9]+), v[0-9]+.4s +** fmov w0, \1 ** and w1, w0, 65535 ** add w0, w1, w0, lsr 16 ** lsr w0, w0, 1 -- 2.25.1