From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2049.outbound.protection.outlook.com [40.107.105.49]) by sourceware.org (Postfix) with ESMTPS id C2C203852908 for ; Fri, 12 May 2023 09:39:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C2C203852908 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SXKTN16isTHcSeEKyJCXw9RLrrrMiXsZvcNqi3Zg0fs=; b=Kp7DbSaDEhUnPqKbsW4RWcPGQ0mtpnj81K2Hb/sOizD7sojXy+WJGlVvVT1EuAuvK6KYU8y+tIJ1NK9oTY5rdKtUw2xSOdNj8zvHZjLJ61C8LNLOGlupuSnW6opRj7wlljvIvR4DnB1zO+dAC+nfEK3k1LmSWN+tgd3SY9f1tJg= Received: from DU2PR04CA0153.eurprd04.prod.outlook.com (2603:10a6:10:2b0::8) by GV1PR08MB8307.eurprd08.prod.outlook.com (2603:10a6:150:a4::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.21; Fri, 12 May 2023 09:39:33 +0000 Received: from DBAEUR03FT032.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:2b0:cafe::27) by DU2PR04CA0153.outlook.office365.com (2603:10a6:10:2b0::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.23 via Frontend Transport; Fri, 12 May 2023 09:39:33 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT032.mail.protection.outlook.com (100.127.142.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.23 via Frontend Transport; Fri, 12 May 2023 09:39:33 +0000 Received: ("Tessian outbound 945aec65ec65:v136"); Fri, 12 May 2023 09:39:33 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 3156d61e4309cac2 X-CR-MTA-TID: 64aa7808 Received: from b94e32a2016d.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id A1FBBC2E-A5B2-4CEA-9ACD-8E0F1C5B5786.1; Fri, 12 May 2023 09:39:21 +0000 Received: from EUR05-DB8-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id b94e32a2016d.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 12 May 2023 09:39:21 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=OsEeDN3vamEaPtXKYvWmY9wXWSs0/jRpeaEyhzpMfDixPOF4g8JeqX/wk3T1np3fH/FNgU7iUXptZbuSTamw6n00klAXhHWIJRNoJHQ32v7yQEtktIy0VA7M2XrrZpSyLUWc/93wVuSZ1PA2cAUM7DmMF6+xiv0P1eBkbn9TyBwNLCrFsWcoITq54atrt4HQTIjmuKl0zw0cACtreim4zoXre8XsvnkNVLSyvuhuzoMSnnlewasCuyk9FCbs0cZu0vRE4mVDm1V+WQPFcBS1DrrlFVbbOgiVyzDd5pz1l3dtXIkrazTMjKvYuEDOzuZy0NhTH14ud3MVyJLIU2JfvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=SXKTN16isTHcSeEKyJCXw9RLrrrMiXsZvcNqi3Zg0fs=; b=QA4KJYWcDYI/ih4mHwzbHYB894v3/yF996Uy7AqMKZPxJCrPiHCL3mma2HTUz3Jh3PPi3kTAe4niUVKFzH2mTbcoZEh7FJW+Sx7zngCsj+XPYcJtt5BqLBcUZW6mrNumjnAeSIfLHsOnms4KsophxpDcIroXyjP5G6obYb8YCvfcDidcdNw6GEYnDjFON1WhKqPoawd+MJ7ViwyRIPuABKngEromkwS4eSSpxCE2vTKjqGpedjwKBrjXIg5byWjGnTdwJr50n1rvxwwWfT9HsG76POGIuCx+vm6En1DFhetTCu6xOAff5Ziu1whs4YZhWtto/7ttLheRsaTsXC2ceg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SXKTN16isTHcSeEKyJCXw9RLrrrMiXsZvcNqi3Zg0fs=; b=Kp7DbSaDEhUnPqKbsW4RWcPGQ0mtpnj81K2Hb/sOizD7sojXy+WJGlVvVT1EuAuvK6KYU8y+tIJ1NK9oTY5rdKtUw2xSOdNj8zvHZjLJ61C8LNLOGlupuSnW6opRj7wlljvIvR4DnB1zO+dAC+nfEK3k1LmSWN+tgd3SY9f1tJg= Received: from AM6PR0202CA0068.eurprd02.prod.outlook.com (2603:10a6:20b:3a::45) by AS4PR08MB7408.eurprd08.prod.outlook.com (2603:10a6:20b:4e3::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.24; Fri, 12 May 2023 09:39:18 +0000 Received: from AM7EUR03FT008.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:3a:cafe::8b) by AM6PR0202CA0068.outlook.office365.com (2603:10a6:20b:3a::45) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.24 via Frontend Transport; Fri, 12 May 2023 09:39:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT008.mail.protection.outlook.com (100.127.141.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6387.22 via Frontend Transport; Fri, 12 May 2023 09:39:18 +0000 Received: from AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 12 May 2023 09:39:05 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 12 May 2023 09:39:04 +0000 Received: from e129018.arm.com (10.57.21.161) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 12 May 2023 09:39:04 +0000 From: Christophe Lyon To: , , , CC: Christophe Lyon Subject: [PATCH 26/26] arm: [MVE intrinsics] rework vsriq Date: Fri, 12 May 2023 11:38:55 +0200 Message-ID: <20230512093855.79529-26-christophe.lyon@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230512093855.79529-1-christophe.lyon@arm.com> References: <20230512093855.79529-1-christophe.lyon@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT008:EE_|AS4PR08MB7408:EE_|DBAEUR03FT032:EE_|GV1PR08MB8307:EE_ X-MS-Office365-Filtering-Correlation-Id: d60151e1-8c84-43d7-d22b-08db52cccadf x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: Z5A8Io463c+HgVjdU26bOqnZdJgNNPUFS0NYBvdD3P92wfXOi99Jaijq6hmkZy+tx/1PMlo48i2mAhfL0SwUrcQuQTNItR3QbTbZYy8CkLqFXzz3+V5HU9HVKJfOJo/4z2f36mE0bgN4Yb5folCS/TPgvPjEvzoJwERUqVLgoS/VW+sfiSp89p+ck0Rg85G8IXkr4hENgKnrs5dO44B3+Clu+RRKlD347yNmgyYQ48w5UrNiDtzWlfUWVHjX3p2DcUIVIwC+agqHzg0cPSqh67d1fkDL8ct92hjlRpyT2QkCqhHlFgxwh5DKuPO11VtvqrnNIYlaNB4+tSqM+4pUTwkEKU5RWBdMlCChX77KKfLiMfORwF/H/XEcIFclc/n+9rC8GfyZTlMyCnmJ9gOmuyTxAM1Q9sun1BbXGgotPFivLs/NioRdanmzEqEKdDSorVU5pbZHHKNFPR9p21BuX/A+/Iob3zbs9KYSxmLVoj16ElfYIk4rOmjwN1JNkmW04ed0X8SjHSrw5Q87FPc4f3j9m0e/Y91ZpoBXfg4Q80puiMiNw2Hb5yg07OW1yHc+ippaOyueEz/Q58y2U7tVKW/MIoNhcbgi77q0X6x2yRGnsymUEwgdv5YA5XS6FFJTYmGu7LOjNOG4Ir9RkuIIsW+CFQkBFcfUSpvl7yNlcxFEJ03YWgZk0Ht+rNOoVYC1Vtm8Tp3gtj2LV2B0oS9V6FNNunVXKdup8irJD17emAiRecJG7rXxtaUmmlJH64ucPkIuM553baBySIpviyzrDA== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(396003)(376002)(39860400002)(136003)(451199021)(40470700004)(36840700001)(46966006)(356005)(81166007)(82740400003)(40480700001)(36756003)(40460700003)(86362001)(82310400005)(5660300002)(44832011)(8936002)(8676002)(2616005)(1076003)(26005)(2906002)(4001150100001)(70586007)(70206006)(478600001)(110136005)(41300700001)(6636002)(4326008)(6666004)(186003)(316002)(30864003)(7696005)(36860700001)(83380400001)(426003)(336012)(47076005)(36900700001);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS4PR08MB7408 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT032.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: e74400cb-5afd-4c5e-9eaf-08db52ccc248 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GtK5out4Gml6xGsF61DhUpir0E2V35OU6x0HYszjXJTpc9g0VMqkItesINQQJL8NcPD+GcM73n1Af8S7Pd46iGaDl+pc4eniMHdtR8JX4JMdoXOt86vuZrs2n3y69tdSzlMNYMTjtoDQTGYWTNE4tBMIKSaKClEjd9vf11wtzlLk4/4/yjP3sdgxxwV5g/MTw0zWyjLaEh6T7r0dyhwXaBtoubur0ARN2DR2GD1fjtOoDuCov5XulKnMmrcHacDeJVIstmf9HHsL4mqjRYXr2X1rnYI8UjOqzkE/icc9V/dPeDeAKGhoK7FZok8ZtCJ7yIt5u9B1TGx4aqVAHY/qcV+nag76B8MEBp2fjbigjThi9UafHQwhBC2yEeY+Ae0Hm50Nr272irgea8kQb1wMO+REYjxlOHfnZAYSw1DmeNqhfevNooiPrVS4q9SYtNMXpkDvGC/RN7OxBn1QIo5fxCPh3cfvncijIVfAj58Ye5o3utAMQ7aRXwRbwOKcXw34Dy2m2CeZz94SvPdD2UBSQ38TQxCbyoLEaIAk3jnTq4nOMun4Q1hbjHyztaYUx0P8WPW8sUOo3NBMbRAZvL/r9hIcswUgnDD83r0EG6WBVTB7uBwQpsdF/71yago517oHJTUBDKdOPOizHinHSQJWhM7OVFiSvG85gukVCLDGvBgo22TjiWQ0eOQ8lLiuC6l9PqCdcDIgc8jUvhQkZGYeQEuDES+eEDjxSOur9l+Ngoq8VW9w5bYHp2v4z5R+X1ou X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230028)(4636009)(346002)(376002)(396003)(136003)(39860400002)(451199021)(40470700004)(46966006)(36840700001)(40460700003)(70586007)(4326008)(6636002)(478600001)(70206006)(110136005)(316002)(36756003)(7696005)(86362001)(6666004)(426003)(336012)(26005)(186003)(36860700001)(2616005)(1076003)(8936002)(8676002)(5660300002)(4001150100001)(2906002)(44832011)(41300700001)(82310400005)(83380400001)(40480700001)(81166007)(82740400003)(47076005)(30864003);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2023 09:39:33.3372 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d60151e1-8c84-43d7-d22b-08db52cccadf X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT032.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB8307 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Implement vsriq using the new MVE builtins framework. 2022-12-12 Christophe Lyon gcc/ * config/arm/arm-mve-builtins-base.cc (vsriq): New. * config/arm/arm-mve-builtins-base.def (vsriq): New. * config/arm/arm-mve-builtins-base.h (vsriq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vsriq. * config/arm/arm_mve.h (vsriq): Remove. (vsriq_m): Remove. (vsriq_n_u8): Remove. (vsriq_n_s8): Remove. (vsriq_n_u16): Remove. (vsriq_n_s16): Remove. (vsriq_n_u32): Remove. (vsriq_n_s32): Remove. (vsriq_m_n_s8): Remove. (vsriq_m_n_u8): Remove. (vsriq_m_n_s16): Remove. (vsriq_m_n_u16): Remove. (vsriq_m_n_s32): Remove. (vsriq_m_n_u32): Remove. (__arm_vsriq_n_u8): Remove. (__arm_vsriq_n_s8): Remove. (__arm_vsriq_n_u16): Remove. (__arm_vsriq_n_s16): Remove. (__arm_vsriq_n_u32): Remove. (__arm_vsriq_n_s32): Remove. (__arm_vsriq_m_n_s8): Remove. (__arm_vsriq_m_n_u8): Remove. (__arm_vsriq_m_n_s16): Remove. (__arm_vsriq_m_n_u16): Remove. (__arm_vsriq_m_n_s32): Remove. (__arm_vsriq_m_n_u32): Remove. (__arm_vsriq): Remove. (__arm_vsriq_m): Remove. --- gcc/config/arm/arm-mve-builtins-base.cc | 1 + gcc/config/arm/arm-mve-builtins-base.def | 1 + gcc/config/arm/arm-mve-builtins-base.h | 1 + gcc/config/arm/arm-mve-builtins.cc | 3 +- gcc/config/arm/arm_mve.h | 212 ----------------------- 5 files changed, 5 insertions(+), 213 deletions(-) diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc index 873c7d365f3..af02397f1c4 100644 --- a/gcc/config/arm/arm-mve-builtins-base.cc +++ b/gcc/config/arm/arm-mve-builtins-base.cc @@ -388,6 +388,7 @@ FUNCTION_ONLY_N_NO_F (vshrnbq, VSHRNBQ) FUNCTION_ONLY_N_NO_F (vshrntq, VSHRNTQ) FUNCTION_ONLY_N_NO_F (vshrq, VSHRQ) FUNCTION_ONLY_N_NO_F (vsliq, VSLIQ) +FUNCTION_ONLY_N_NO_F (vsriq, VSRIQ) FUNCTION_WITH_RTX_M_N (vsubq, MINUS, VSUBQ) FUNCTION (vuninitializedq, vuninitializedq_impl,) diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def index 2d1b87b90c3..ee08d063407 100644 --- a/gcc/config/arm/arm-mve-builtins-base.def +++ b/gcc/config/arm/arm-mve-builtins-base.def @@ -141,6 +141,7 @@ DEF_MVE_FUNCTION (vshrnbq, binary_rshift_narrow, integer_16_32, m_or_none) DEF_MVE_FUNCTION (vshrntq, binary_rshift_narrow, integer_16_32, m_or_none) DEF_MVE_FUNCTION (vshrq, binary_rshift, all_integer, mx_or_none) DEF_MVE_FUNCTION (vsliq, ternary_lshift, all_integer, m_or_none) +DEF_MVE_FUNCTION (vsriq, ternary_rshift, all_integer, m_or_none) DEF_MVE_FUNCTION (vsubq, binary_opt_n, all_integer, mx_or_none) DEF_MVE_FUNCTION (vuninitializedq, inherent, all_integer_with_64, none) #undef REQUIRES_FLOAT diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h index 84fff0f6d0e..942c8587446 100644 --- a/gcc/config/arm/arm-mve-builtins-base.h +++ b/gcc/config/arm/arm-mve-builtins-base.h @@ -161,6 +161,7 @@ extern const function_base *const vshrnbq; extern const function_base *const vshrntq; extern const function_base *const vshrq; extern const function_base *const vsliq; +extern const function_base *const vsriq; extern const function_base *const vsubq; extern const function_base *const vuninitializedq; diff --git a/gcc/config/arm/arm-mve-builtins.cc b/gcc/config/arm/arm-mve-builtins.cc index f5056bdd1bb..7033e41a571 100644 --- a/gcc/config/arm/arm-mve-builtins.cc +++ b/gcc/config/arm/arm-mve-builtins.cc @@ -720,7 +720,8 @@ function_instance::has_inactive_argument () const || base == functions::vrshrntq || base == functions::vshrnbq || base == functions::vshrntq - || base == functions::vsliq) + || base == functions::vsliq + || base == functions::vsriq) return false; return true; diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 72177f9c53e..1774e6eca2b 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -54,8 +54,6 @@ #define vmullbq_poly(__a, __b) __arm_vmullbq_poly(__a, __b) #define vbicq_m_n(__a, __imm, __p) __arm_vbicq_m_n(__a, __imm, __p) #define vshlcq(__a, __b, __imm) __arm_vshlcq(__a, __b, __imm) -#define vsriq(__a, __b, __imm) __arm_vsriq(__a, __b, __imm) -#define vsriq_m(__a, __b, __imm, __p) __arm_vsriq_m(__a, __b, __imm, __p) #define vbicq_m(__inactive, __a, __b, __p) __arm_vbicq_m(__inactive, __a, __b, __p) #define vcaddq_rot270_m(__inactive, __a, __b, __p) __arm_vcaddq_rot270_m(__inactive, __a, __b, __p) #define vcaddq_rot90_m(__inactive, __a, __b, __p) __arm_vcaddq_rot90_m(__inactive, __a, __b, __p) @@ -338,12 +336,6 @@ #define vshlcq_u16(__a, __b, __imm) __arm_vshlcq_u16(__a, __b, __imm) #define vshlcq_s32(__a, __b, __imm) __arm_vshlcq_s32(__a, __b, __imm) #define vshlcq_u32(__a, __b, __imm) __arm_vshlcq_u32(__a, __b, __imm) -#define vsriq_n_u8(__a, __b, __imm) __arm_vsriq_n_u8(__a, __b, __imm) -#define vsriq_n_s8(__a, __b, __imm) __arm_vsriq_n_s8(__a, __b, __imm) -#define vsriq_n_u16(__a, __b, __imm) __arm_vsriq_n_u16(__a, __b, __imm) -#define vsriq_n_s16(__a, __b, __imm) __arm_vsriq_n_s16(__a, __b, __imm) -#define vsriq_n_u32(__a, __b, __imm) __arm_vsriq_n_u32(__a, __b, __imm) -#define vsriq_n_s32(__a, __b, __imm) __arm_vsriq_n_s32(__a, __b, __imm) #define vcvtbq_m_f16_f32(__a, __b, __p) __arm_vcvtbq_m_f16_f32(__a, __b, __p) #define vcvtbq_m_f32_f16(__inactive, __a, __p) __arm_vcvtbq_m_f32_f16(__inactive, __a, __p) #define vcvttq_m_f16_f32(__a, __b, __p) __arm_vcvttq_m_f16_f32(__a, __b, __p) @@ -372,16 +364,10 @@ #define vcvtnq_m_u32_f32(__inactive, __a, __p) __arm_vcvtnq_m_u32_f32(__inactive, __a, __p) #define vcvtpq_m_u32_f32(__inactive, __a, __p) __arm_vcvtpq_m_u32_f32(__inactive, __a, __p) #define vcvtq_m_u32_f32(__inactive, __a, __p) __arm_vcvtq_m_u32_f32(__inactive, __a, __p) -#define vsriq_m_n_s8(__a, __b, __imm, __p) __arm_vsriq_m_n_s8(__a, __b, __imm, __p) #define vcvtq_m_n_f16_u16(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f16_u16(__inactive, __a, __imm6, __p) -#define vsriq_m_n_u8(__a, __b, __imm, __p) __arm_vsriq_m_n_u8(__a, __b, __imm, __p) #define vcvtq_m_n_f16_s16(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f16_s16(__inactive, __a, __imm6, __p) -#define vsriq_m_n_s16(__a, __b, __imm, __p) __arm_vsriq_m_n_s16(__a, __b, __imm, __p) #define vcvtq_m_n_f32_u32(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f32_u32(__inactive, __a, __imm6, __p) -#define vsriq_m_n_u16(__a, __b, __imm, __p) __arm_vsriq_m_n_u16(__a, __b, __imm, __p) #define vcvtq_m_n_f32_s32(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f32_s32(__inactive, __a, __imm6, __p) -#define vsriq_m_n_s32(__a, __b, __imm, __p) __arm_vsriq_m_n_s32(__a, __b, __imm, __p) -#define vsriq_m_n_u32(__a, __b, __imm, __p) __arm_vsriq_m_n_u32(__a, __b, __imm, __p) #define vbicq_m_s8(__inactive, __a, __b, __p) __arm_vbicq_m_s8(__inactive, __a, __b, __p) #define vbicq_m_s32(__inactive, __a, __b, __p) __arm_vbicq_m_s32(__inactive, __a, __b, __p) #define vbicq_m_s16(__inactive, __a, __b, __p) __arm_vbicq_m_s16(__inactive, __a, __b, __p) @@ -1517,90 +1503,6 @@ __arm_vshlcq_u32 (uint32x4_t __a, uint32_t * __b, const int __imm) return __res; } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm) -{ - return __builtin_mve_vsriq_n_uv16qi (__a, __b, __imm); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm) -{ - return __builtin_mve_vsriq_n_sv16qi (__a, __b, __imm); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm) -{ - return __builtin_mve_vsriq_n_uv8hi (__a, __b, __imm); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_n_s16 (int16x8_t __a, int16x8_t __b, const int __imm) -{ - return __builtin_mve_vsriq_n_sv8hi (__a, __b, __imm); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm) -{ - return __builtin_mve_vsriq_n_uv4si (__a, __b, __imm); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_n_s32 (int32x4_t __a, int32x4_t __b, const int __imm) -{ - return __builtin_mve_vsriq_n_sv4si (__a, __b, __imm); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_m_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vsriq_m_n_sv16qi (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_m_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vsriq_m_n_uv16qi (__a, __b, __imm, __p); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_m_n_s16 (int16x8_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vsriq_m_n_sv8hi (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_m_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vsriq_m_n_uv8hi (__a, __b, __imm, __p); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_m_n_s32 (int32x4_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vsriq_m_n_sv4si (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_m_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __builtin_mve_vsriq_m_n_uv4si (__a, __b, __imm, __p); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vbicq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) @@ -6905,90 +6807,6 @@ __arm_vshlcq (uint32x4_t __a, uint32_t * __b, const int __imm) return __arm_vshlcq_u32 (__a, __b, __imm); } -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq (uint8x16_t __a, uint8x16_t __b, const int __imm) -{ - return __arm_vsriq_n_u8 (__a, __b, __imm); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq (int8x16_t __a, int8x16_t __b, const int __imm) -{ - return __arm_vsriq_n_s8 (__a, __b, __imm); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq (uint16x8_t __a, uint16x8_t __b, const int __imm) -{ - return __arm_vsriq_n_u16 (__a, __b, __imm); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq (int16x8_t __a, int16x8_t __b, const int __imm) -{ - return __arm_vsriq_n_s16 (__a, __b, __imm); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq (uint32x4_t __a, uint32x4_t __b, const int __imm) -{ - return __arm_vsriq_n_u32 (__a, __b, __imm); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq (int32x4_t __a, int32x4_t __b, const int __imm) -{ - return __arm_vsriq_n_s32 (__a, __b, __imm); -} - -__extension__ extern __inline int8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_m (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vsriq_m_n_s8 (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint8x16_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_m (uint8x16_t __a, uint8x16_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vsriq_m_n_u8 (__a, __b, __imm, __p); -} - -__extension__ extern __inline int16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_m (int16x8_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vsriq_m_n_s16 (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint16x8_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_m (uint16x8_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vsriq_m_n_u16 (__a, __b, __imm, __p); -} - -__extension__ extern __inline int32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_m (int32x4_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vsriq_m_n_s32 (__a, __b, __imm, __p); -} - -__extension__ extern __inline uint32x4_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vsriq_m (uint32x4_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) -{ - return __arm_vsriq_m_n_u32 (__a, __b, __imm, __p); -} - __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vbicq_m (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) @@ -11164,16 +10982,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlcq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlcq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) -#define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsriq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsriq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsriq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsriq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsriq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsriq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) - #define __arm_vcvtaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ @@ -11930,16 +11738,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbicq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), p1, p2), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbicq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), p1, p2));}) -#define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsriq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsriq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsriq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsriq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsriq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsriq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) - #define __arm_vbicq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ @@ -12512,16 +12310,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint16x8_t]: __arm_vldrbq_gather_offset_z_u16 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ int (*)[__ARM_mve_type_uint8_t_ptr][__ARM_mve_type_uint32x4_t]: __arm_vldrbq_gather_offset_z_u32 (__ARM_mve_coerce1(p0, uint8_t *), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define __arm_vsriq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsriq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsriq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsriq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsriq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsriq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsriq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) - #define __arm_vhcaddq_rot270_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ -- 2.34.1