From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id 08EFA3858C20 for ; Tue, 16 May 2023 06:52:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 08EFA3858C20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684219950; x=1715755950; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=zGYMHKa2zFZVHx9Qyn29KmeaqVdXMP+IVJKCHI5jLLI=; b=S4GEAAG7+q8pZ+b6YuiRnxe6i6fw2c0CEEjtvOr0FhHjqjZXHr0qmjr3 M1eArEBmGkhgLa02ilBaf/7N6a7Gj0lHYla9wKrGT5/zUX/SunZx8gDp7 e2z5pHdwvEV4qPLCDOywf/c1uIwhpUjbLeLlMIbW3B+Xuw7iVVUnJq0z6 HFqO/H68DoMmSEuUPOlC5GQvs4EMGxoCKICEwQJkj/09bVWY5xohMuAhV Lly8iQrR9jMDoc1lSKQpMz4Uqon76pUHxKAVvcdArX/m/n6FBDn2jMPdR wXkhqP3x/QhDECYOL2YFUTBQ1zvD/dXcSKSE2Az4EskPPsuKQXHbjcFlz g==; X-IronPort-AV: E=McAfee;i="6600,9927,10711"; a="350235961" X-IronPort-AV: E=Sophos;i="5.99,278,1677571200"; d="scan'208";a="350235961" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2023 23:52:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10711"; a="701240775" X-IronPort-AV: E=Sophos;i="5.99,278,1677571200"; d="scan'208";a="701240775" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga002.jf.intel.com with ESMTP; 15 May 2023 23:52:03 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 3B697100562D; Tue, 16 May 2023 14:52:03 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com, jeffreyalaw@gmail.com Subject: [PATCH] RISC-V: Adjust stdint.h to stdint-gcc.h for rvv tests Date: Tue, 16 May 2023 14:52:01 +0800 Message-Id: <20230516065201.751821-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch would like to align the stdint.h to the stdint-gcc.h for all the RVV test files. Aka: stdint.h => stdint-gcc.h Signed-off-by: Pan Li gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h: Replace stdint.h with stdint-gcc.h. * gcc.target/riscv/rvv/autovec/binop/shift-template.h: Ditto. * gcc.target/riscv/rvv/autovec/binop/vadd-template.h: Ditto. * gcc.target/riscv/rvv/autovec/binop/vand-template.h: Ditto. * gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmax-template.h: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmin-template.h: Ditto. * gcc.target/riscv/rvv/autovec/binop/vmul-template.h: Ditto. * gcc.target/riscv/rvv/autovec/binop/vor-template.h: Ditto. * gcc.target/riscv/rvv/autovec/binop/vrem-template.h: Ditto. * gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Ditto. * gcc.target/riscv/rvv/autovec/binop/vxor-template.h: Ditto. * gcc.target/riscv/rvv/autovec/series-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vmv-imm-template.h: Ditto. --- .../gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h | 2 +- .../gcc.target/riscv/rvv/autovec/binop/shift-template.h | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vadd-template.h | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vand-template.h | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vdiv-template.h | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vmax-template.h | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vmin-template.h | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vmul-template.h | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vrem-template.h | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vsub-template.h | 2 +- .../gcc.target/riscv/rvv/autovec/binop/vxor-template.h | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h index a0ddc00849d..8d1cefdca85 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h @@ -2,7 +2,7 @@ /* { dg-do run } */ /* { dg-additional-options "-std=c99 --param=riscv-autovec-preference=scalable -fno-vect-cost-model --save-temps" } */ -#include +#include #include #define SHIFTL(TYPE,VAL) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h index 64e0a386b06..16ae48c8ede 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h @@ -1,4 +1,4 @@ -#include +#include #define TEST1_TYPE(TYPE) \ __attribute__((noipa)) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h index 5ed79329138..cd945d471d2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h @@ -1,4 +1,4 @@ -#include +#include #define TEST_TYPE(TYPE) \ __attribute__((noipa)) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h index 7d02c83d164..5cabe073097 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h @@ -1,4 +1,4 @@ -#include +#include #define TEST_TYPE(TYPE) \ __attribute__((noipa)) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h index 7fbba7b4133..12a1de32874 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h @@ -1,4 +1,4 @@ -#include +#include #define TEST_TYPE(TYPE) \ __attribute__((noipa)) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h index df0f9f2aeeb..fc6a07e3ce9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h @@ -1,4 +1,4 @@ -#include +#include #define TEST_TYPE(TYPE) \ __attribute__((noipa)) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h index 459f58ddec1..06f6b95461e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h @@ -1,4 +1,4 @@ -#include +#include #define TEST_TYPE(TYPE) \ __attribute__((noipa)) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h index b029c06efd6..37f77972101 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h @@ -1,4 +1,4 @@ -#include +#include #define TEST_TYPE(TYPE) \ __attribute__((noipa)) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h index 859ae67c5ee..e60146cc232 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h @@ -1,4 +1,4 @@ -#include +#include #define TEST_TYPE(TYPE) \ __attribute__((noipa)) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h index 71eebc8b645..d5ef40667ff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h @@ -1,4 +1,4 @@ -#include +#include #define TEST_TYPE(TYPE) \ __attribute__((noipa)) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h index 0566f3dcbfb..8c0a9c99217 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h @@ -1,4 +1,4 @@ -#include +#include #define TEST_TYPE(TYPE) \ __attribute__((noipa)) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h index 954a247f539..370b242f197 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h @@ -1,4 +1,4 @@ -#include +#include #define TEST_TYPE(TYPE) \ __attribute__((noipa)) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c index a01f6ce7411..1c697228e9b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/series-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4" } */ -#include +#include #define NUM_ELEMS(TYPE) (64 / sizeof (TYPE)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c index 309a296b686..6764110d461 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c @@ -3,7 +3,7 @@ #include "vmv-imm-template.h" -#include +#include #include #define SZ 512 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h index 93ba5204c2e..855343d7e3e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h @@ -1,4 +1,4 @@ -#include +#include #include #define VMV_POS(TYPE,VAL) \ -- 2.34.1